src/mesa/drivers/dri/i965/brw_binding_tables.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * \file brw_binding_tables.c
  26  *
  27  * State atoms which upload the "binding table" for each shader stage.
  28  *
  29  * Binding tables map a numeric "surface index" to the SURFACE_STATE structure
  30  * for a currently bound surface.  This allows SEND messages (such as sampler
  31  * or data port messages) to refer to a particular surface by number, rather
  32  * than by pointer.
  33  *
  34  * The binding table is stored as a (sparse) array of SURFACE_STATE entries;
  35  * surface indexes are simply indexes into the array.  The ordering of the
  36  * entries is entirely left up to software; see the SURF_INDEX_* macros in
  37  * brw_context.h to see our current layout.
  38  */
  39
  40 #include "main/mtypes.h"
  41
  42 #include "brw_context.h"
  43 #include "brw_defines.h"
  44 #include "brw_state.h"
  45 #include "intel_batchbuffer.h"
  46
  47 static const GLuint stage_to_bt_edit[MESA_SHADER_FRAGMENT + 1] = {
  48    _3DSTATE_BINDING_TABLE_EDIT_VS,
  49    _3DSTATE_BINDING_TABLE_EDIT_GS,
  50    _3DSTATE_BINDING_TABLE_EDIT_PS,
  51 };
  52
  53 /**
  54  * Upload a shader stage's binding table as indirect state.
  55  *
  56  * This copies brw_stage_state::surf_offset[] into the indirect state section
  57  * of the batchbuffer (allocated by brw_state_batch()).
  58  */
  59 void
  60 brw_upload_binding_table(struct brw_context *brw,
  61                          uint32_t packet_name,
  62                          GLbitfield brw_new_binding_table,
  63                          const struct brw_stage_prog_data *prog_data,
  64                          struct brw_stage_state *stage_state)
  65 {
  66    if (prog_data->binding_table.size_bytes == 0) {
  67       /* There are no surfaces; skip making the binding table altogether. */
  68       if (stage_state->bind_bo_offset == 0 && brw->gen < 9)
  69          return;
  70
  71       stage_state->bind_bo_offset = 0;
  72    } else {
  73       /* Upload a new binding table. */
  74       if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
  75          brw->vtbl.emit_buffer_surface_state(
  76             brw, &stage_state->surf_offset[
  77                     prog_data->binding_table.shader_time_start],
  78             brw->shader_time.bo, 0, BRW_SURFACEFORMAT_RAW,
  79             brw->shader_time.bo->size, 1, true);
  80       }
  81
  82       uint32_t *bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
  83                                        prog_data->binding_table.size_bytes, 32,
  84                                        &stage_state->bind_bo_offset);
  85
  86       /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
  87       memcpy(bind, stage_state->surf_offset,
  88              prog_data->binding_table.size_bytes);
  89    }
  90
  91    brw->ctx.NewDriverState |= brw_new_binding_table;
  92
  93    if (brw->gen >= 7) {
  94       BEGIN_BATCH(2);
  95       OUT_BATCH(packet_name << 16 | (2 - 2));
  96       OUT_BATCH(stage_state->bind_bo_offset);
  97       ADVANCE_BATCH();
  98    }
  99 }
 100
 101 /**
 102  * State atoms which upload the binding table for a particular shader stage.
 103  *  @{
 104  */
 105
 106 /** Upload the VS binding table. */
 107 static void
 108 brw_vs_upload_binding_table(struct brw_context *brw)
 109 {
 110    /* BRW_NEW_VS_PROG_DATA */
 111    const struct brw_stage_prog_data *prog_data = brw->vs.base.prog_data;
 112    brw_upload_binding_table(brw,
 113                             _3DSTATE_BINDING_TABLE_POINTERS_VS,
 114                             BRW_NEW_VS_BINDING_TABLE, prog_data,
 115                             &brw->vs.base);
 116 }
 117
 118 const struct brw_tracked_state brw_vs_binding_table = {
 119    .dirty = {
 120       .mesa = 0,
 121       .brw = BRW_NEW_BATCH |
 122              BRW_NEW_VS_CONSTBUF |
 123              BRW_NEW_VS_PROG_DATA |
 124              BRW_NEW_SURFACES,
 125    },
 126    .emit = brw_vs_upload_binding_table,
 127 };
 128
 129
 130 /** Upload the PS binding table. */
 131 static void
 132 brw_upload_wm_binding_table(struct brw_context *brw)
 133 {
 134    /* BRW_NEW_FS_PROG_DATA */
 135    const struct brw_stage_prog_data *prog_data = brw->wm.base.prog_data;
 136    brw_upload_binding_table(brw,
 137                             _3DSTATE_BINDING_TABLE_POINTERS_PS,
 138                             BRW_NEW_PS_BINDING_TABLE, prog_data,
 139                             &brw->wm.base);
 140 }
 141
 142 const struct brw_tracked_state brw_wm_binding_table = {
 143    .dirty = {
 144       .mesa = 0,
 145       .brw = BRW_NEW_BATCH |
 146              BRW_NEW_FS_PROG_DATA |
 147              BRW_NEW_SURFACES,
 148    },
 149    .emit = brw_upload_wm_binding_table,
 150 };
 151
 152 /** Upload the GS binding table (if GS is active). */
 153 static void
 154 brw_gs_upload_binding_table(struct brw_context *brw)
 155 {
 156    /* If there's no GS, skip changing anything. */
 157    if (brw->geometry_program == NULL)
 158       return;
 159
 160    /* BRW_NEW_GS_PROG_DATA */
 161    const struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data;
 162    brw_upload_binding_table(brw,
 163                             _3DSTATE_BINDING_TABLE_POINTERS_GS,
 164                             BRW_NEW_GS_BINDING_TABLE, prog_data,
 165                             &brw->gs.base);
 166 }
 167
 168 const struct brw_tracked_state brw_gs_binding_table = {
 169    .dirty = {
 170       .mesa = 0,
 171       .brw = BRW_NEW_BATCH |
 172              BRW_NEW_GS_CONSTBUF |
 173              BRW_NEW_GS_PROG_DATA |
 174              BRW_NEW_SURFACES,
 175    },
 176    .emit = brw_gs_upload_binding_table,
 177 };
 178
 179 /**
 180  * Edit a single entry in a hardware-generated binding table
 181  */
 182 void
 183 gen7_edit_hw_binding_table_entry(struct brw_context *brw,
 184                                  gl_shader_stage stage,
 185                                  uint32_t index,
 186                                  uint32_t surf_offset)
 187 {
 188    assert(stage <= MESA_SHADER_FRAGMENT);
 189
 190    uint32_t dw2 = SET_FIELD(index, BRW_BINDING_TABLE_INDEX) |
 191       (brw->gen >= 8 ? GEN8_SURFACE_STATE_EDIT(surf_offset) :
 192        HSW_SURFACE_STATE_EDIT(surf_offset));
 193
 194    BEGIN_BATCH(3);
 195    OUT_BATCH(stage_to_bt_edit[stage] << 16 | (3 - 2));
 196    OUT_BATCH(BRW_BINDING_TABLE_EDIT_TARGET_ALL);
 197    OUT_BATCH(dw2);
 198    ADVANCE_BATCH();
 199 }
 200
 201 /**
 202  * Upload a whole hardware binding table for the given stage.
 203  *
 204  * Takes an array of surface offsets and the number of binding table
 205  * entries.
 206  */
 207 void
 208 gen7_update_binding_table_from_array(struct brw_context *brw,
 209                                      gl_shader_stage stage,
 210                                      const uint32_t* binding_table,
 211                                      int num_surfaces)
 212 {
 213    uint32_t dw2 = 0;
 214    assert(stage <= MESA_SHADER_FRAGMENT);
 215
 216    BEGIN_BATCH(num_surfaces + 2);
 217    OUT_BATCH(stage_to_bt_edit[stage] << 16 | num_surfaces);
 218    OUT_BATCH(BRW_BINDING_TABLE_EDIT_TARGET_ALL);
 219    for (int i = 0; i < num_surfaces; i++) {
 220       dw2 = SET_FIELD(i, BRW_BINDING_TABLE_INDEX) |
 221          (brw->gen >= 8 ? GEN8_SURFACE_STATE_EDIT(binding_table[i]) :
 222           HSW_SURFACE_STATE_EDIT(binding_table[i]));
 223       OUT_BATCH(dw2);
 224    }
 225    ADVANCE_BATCH();
 226 }
 227
 228 /**
 229  * Disable hardware binding table support, falling back to the
 230  * older software-generated binding table mechanism.
 231  */
 232 void
 233 gen7_disable_hw_binding_tables(struct brw_context *brw)
 234 {
 235    if (!brw->use_resource_streamer)
 236       return;
 237    /* From the Haswell PRM, Volume 7: 3D Media GPGPU,
 238     * 3DSTATE_BINDING_TABLE_POOL_ALLOC > Programming Note:
 239     *
 240     * "When switching between HW and SW binding table generation, SW must
 241     * issue a state cache invalidate."
 242     */
 243    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
 244
 245    int pkt_len = brw->gen >= 8 ? 4 : 3;
 246
 247    BEGIN_BATCH(pkt_len);
 248    OUT_BATCH(_3DSTATE_BINDING_TABLE_POOL_ALLOC << 16 | (pkt_len - 2));
 249    if (brw->gen >= 8) {
 250       OUT_BATCH(0);
 251       OUT_BATCH(0);
 252       OUT_BATCH(0);
 253    } else {
 254       OUT_BATCH(HSW_BT_POOL_ALLOC_MUST_BE_ONE);
 255       OUT_BATCH(0);
 256    }
 257    ADVANCE_BATCH();
 258 }
 259
 260 /**
 261  * Enable hardware binding tables and set up the binding table pool.
 262  */
 263 void
 264 gen7_enable_hw_binding_tables(struct brw_context *brw)
 265 {
 266    if (!brw->use_resource_streamer)
 267       return;
 268
 269    if (!brw->hw_bt_pool.bo) {
 270       /* We use a single re-usable buffer object for the lifetime of the
 271        * context and size it to maximum allowed binding tables that can be
 272        * programmed per batch:
 273        *
 274        * From the Haswell PRM, Volume 7: 3D Media GPGPU,
 275        * 3DSTATE_BINDING_TABLE_POOL_ALLOC > Programming Note:
 276        * "A maximum of 16,383 Binding tables are allowed in any batch buffer"
 277        */
 278       static const int max_size = 16383 * 4;
 279       brw->hw_bt_pool.bo = drm_intel_bo_alloc(brw->bufmgr, "hw_bt",
 280                                               max_size, 64);
 281       brw->hw_bt_pool.next_offset = 0;
 282    }
 283
 284    /* From the Haswell PRM, Volume 7: 3D Media GPGPU,
 285     * 3DSTATE_BINDING_TABLE_POOL_ALLOC > Programming Note:
 286     *
 287     * "When switching between HW and SW binding table generation, SW must
 288     * issue a state cache invalidate."
 289     */
 290    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
 291
 292    int pkt_len = brw->gen >= 8 ? 4 : 3;
 293    uint32_t dw1 = BRW_HW_BINDING_TABLE_ENABLE;
 294    if (brw->is_haswell) {
 295       dw1 |= SET_FIELD(GEN7_MOCS_L3, GEN7_HW_BT_POOL_MOCS) |
 296              HSW_BT_POOL_ALLOC_MUST_BE_ONE;
 297    } else if (brw->gen >= 8) {
 298       dw1 |= BDW_MOCS_WB;
 299    }
 300
 301    BEGIN_BATCH(pkt_len);
 302    OUT_BATCH(_3DSTATE_BINDING_TABLE_POOL_ALLOC << 16 | (pkt_len - 2));
 303    if (brw->gen >= 8) {
 304       OUT_RELOC64(brw->hw_bt_pool.bo, I915_GEM_DOMAIN_SAMPLER, 0, dw1);
 305       OUT_BATCH(brw->hw_bt_pool.bo->size);
 306    } else {
 307       OUT_RELOC(brw->hw_bt_pool.bo, I915_GEM_DOMAIN_SAMPLER, 0, dw1);
 308       OUT_RELOC(brw->hw_bt_pool.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 309              brw->hw_bt_pool.bo->size);
 310    }
 311    ADVANCE_BATCH();
 312 }
 313
 314 void
 315 gen7_reset_hw_bt_pool_offsets(struct brw_context *brw)
 316 {
 317    brw->hw_bt_pool.next_offset = 0;
 318 }
 319
 320 const struct brw_tracked_state gen7_hw_binding_tables = {
 321    .dirty = {
 322       .mesa = 0,
 323       .brw = BRW_NEW_BATCH,
 324    },
 325    .emit = gen7_enable_hw_binding_tables
 326 };
 327
 328 /** @} */
 329
 330 /**
 331  * State atoms which emit 3DSTATE packets to update the binding table pointers.
 332  *  @{
 333  */
 334
 335 /**
 336  * (Gen4-5) Upload the binding table pointers for all shader stages.
 337  *
 338  * The binding table pointers are relative to the surface state base address,
 339  * which points at the batchbuffer containing the streamed batch state.
 340  */
 341 static void
 342 gen4_upload_binding_table_pointers(struct brw_context *brw)
 343 {
 344    BEGIN_BATCH(6);
 345    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2));
 346    OUT_BATCH(brw->vs.base.bind_bo_offset);
 347    OUT_BATCH(0); /* gs */
 348    OUT_BATCH(0); /* clip */
 349    OUT_BATCH(0); /* sf */
 350    OUT_BATCH(brw->wm.base.bind_bo_offset);
 351    ADVANCE_BATCH();
 352 }
 353
 354 const struct brw_tracked_state brw_binding_table_pointers = {
 355    .dirty = {
 356       .mesa = 0,
 357       .brw = BRW_NEW_BATCH |
 358              BRW_NEW_GS_BINDING_TABLE |
 359              BRW_NEW_PS_BINDING_TABLE |
 360              BRW_NEW_STATE_BASE_ADDRESS |
 361              BRW_NEW_VS_BINDING_TABLE,
 362    },
 363    .emit = gen4_upload_binding_table_pointers,
 364 };
 365
 366 /**
 367  * (Sandybridge Only) Upload the binding table pointers for all shader stages.
 368  *
 369  * The binding table pointers are relative to the surface state base address,
 370  * which points at the batchbuffer containing the streamed batch state.
 371  */
 372 static void
 373 gen6_upload_binding_table_pointers(struct brw_context *brw)
 374 {
 375    BEGIN_BATCH(4);
 376    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 |
 377              GEN6_BINDING_TABLE_MODIFY_VS |
 378              GEN6_BINDING_TABLE_MODIFY_GS |
 379              GEN6_BINDING_TABLE_MODIFY_PS |
 380              (4 - 2));
 381    OUT_BATCH(brw->vs.base.bind_bo_offset); /* vs */
 382    if (brw->ff_gs.prog_active)
 383       OUT_BATCH(brw->ff_gs.bind_bo_offset); /* gs */
 384    else
 385       OUT_BATCH(brw->gs.base.bind_bo_offset); /* gs */
 386    OUT_BATCH(brw->wm.base.bind_bo_offset); /* wm/ps */
 387    ADVANCE_BATCH();
 388 }
 389
 390 const struct brw_tracked_state gen6_binding_table_pointers = {
 391    .dirty = {
 392       .mesa = 0,
 393       .brw = BRW_NEW_BATCH |
 394              BRW_NEW_GS_BINDING_TABLE |
 395              BRW_NEW_PS_BINDING_TABLE |
 396              BRW_NEW_STATE_BASE_ADDRESS |
 397              BRW_NEW_VS_BINDING_TABLE,
 398    },
 399    .emit = gen6_upload_binding_table_pointers,
 400 };
 401
 402 /** @} */