src/mesa/drivers/dri/i965/brw_binding_tables.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * \file brw_binding_tables.c
  26  *
  27  * State atoms which upload the "binding table" for each shader stage.
  28  *
  29  * Binding tables map a numeric "surface index" to the SURFACE_STATE structure
  30  * for a currently bound surface.  This allows SEND messages (such as sampler
  31  * or data port messages) to refer to a particular surface by number, rather
  32  * than by pointer.
  33  *
  34  * The binding table is stored as a (sparse) array of SURFACE_STATE entries;
  35  * surface indexes are simply indexes into the array.  The ordering of the
  36  * entries is entirely left up to software; see the SURF_INDEX_* macros in
  37  * brw_context.h to see our current layout.
  38  */
  39
  40 #include "main/mtypes.h"
  41
  42 #include "brw_context.h"
  43 #include "brw_defines.h"
  44 #include "brw_state.h"
  45 #include "intel_batchbuffer.h"
  46
  47 static const GLuint stage_to_bt_edit[] = {
  48    [MESA_SHADER_VERTEX] = _3DSTATE_BINDING_TABLE_EDIT_VS,
  49    [MESA_SHADER_GEOMETRY] = _3DSTATE_BINDING_TABLE_EDIT_GS,
  50    [MESA_SHADER_FRAGMENT] = _3DSTATE_BINDING_TABLE_EDIT_PS,
  51 };
  52
  53 static uint32_t
  54 reserve_hw_bt_space(struct brw_context *brw, unsigned bytes)
  55 {
  56    /* From the Broadwell PRM, Volume 16, "Workarounds",
  57     * WaStateBindingTableOverfetch:
  58     * "HW over-fetches two cache lines of binding table indices.  When
  59     *  using the resource streamer, SW needs to pad binding table pointer
  60     *  updates with an additional two cache lines."
  61     *
  62     * Cache lines are 64 bytes, so we subtract 128 bytes from the size of
  63     * the binding table pool buffer.
  64     */
  65    if (brw->hw_bt_pool.next_offset + bytes >= brw->hw_bt_pool.bo->size - 128) {
  66       gen7_reset_hw_bt_pool_offsets(brw);
  67    }
  68
  69    uint32_t offset = brw->hw_bt_pool.next_offset;
  70
  71    /* From the Haswell PRM, Volume 2b: Command Reference: Instructions,
  72     * 3DSTATE_BINDING_TABLE_POINTERS_xS:
  73     *
  74     * "If HW Binding Table is enabled, the offset is relative to the
  75     *  Binding Table Pool Base Address and the alignment is 64 bytes."
  76     */
  77    brw->hw_bt_pool.next_offset += ALIGN(bytes, 64);
  78
  79    return offset;
  80 }
  81
  82 /**
  83  * Upload a shader stage's binding table as indirect state.
  84  *
  85  * This copies brw_stage_state::surf_offset[] into the indirect state section
  86  * of the batchbuffer (allocated by brw_state_batch()).
  87  */
  88 void
  89 brw_upload_binding_table(struct brw_context *brw,
  90                          uint32_t packet_name,
  91                          GLbitfield brw_new_binding_table,
  92                          const struct brw_stage_prog_data *prog_data,
  93                          struct brw_stage_state *stage_state)
  94 {
  95    if (prog_data->binding_table.size_bytes == 0) {
  96       /* There are no surfaces; skip making the binding table altogether. */
  97       if (stage_state->bind_bo_offset == 0 && brw->gen < 9)
  98          return;
  99
 100       stage_state->bind_bo_offset = 0;
 101    } else {
 102       /* Upload a new binding table. */
 103       if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
 104          brw->vtbl.emit_buffer_surface_state(
 105             brw, &stage_state->surf_offset[
 106                     prog_data->binding_table.shader_time_start],
 107             brw->shader_time.bo, 0, BRW_SURFACEFORMAT_RAW,
 108             brw->shader_time.bo->size, 1, true);
 109       }
 110       /* When RS is enabled use hw-binding table uploads, otherwise fallback to
 111        * software-uploads.
 112        */
 113       if (brw->use_resource_streamer) {
 114          gen7_update_binding_table_from_array(brw, stage_state->stage,
 115                                               stage_state->surf_offset,
 116                                               prog_data->binding_table
 117                                               .size_bytes / 4);
 118       } else {
 119          uint32_t *bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
 120                                           prog_data->binding_table.size_bytes,
 121                                           32,
 122                                           &stage_state->bind_bo_offset);
 123
 124          /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
 125          memcpy(bind, stage_state->surf_offset,
 126                 prog_data->binding_table.size_bytes);
 127       }
 128    }
 129
 130    brw->ctx.NewDriverState |= brw_new_binding_table;
 131
 132    if (brw->gen >= 7) {
 133       if (brw->use_resource_streamer) {
 134          stage_state->bind_bo_offset =
 135             reserve_hw_bt_space(brw, prog_data->binding_table.size_bytes);
 136       }
 137       BEGIN_BATCH(2);
 138       OUT_BATCH(packet_name << 16 | (2 - 2));
 139       /* Align SurfaceStateOffset[16:6] format to [15:5] PS Binding Table field
 140        * when hw-generated binding table is enabled.
 141        */
 142       OUT_BATCH(brw->use_resource_streamer ?
 143                 (stage_state->bind_bo_offset >> 1) :
 144                 stage_state->bind_bo_offset);
 145       ADVANCE_BATCH();
 146    }
 147 }
 148
 149 /**
 150  * State atoms which upload the binding table for a particular shader stage.
 151  *  @{
 152  */
 153
 154 /** Upload the VS binding table. */
 155 static void
 156 brw_vs_upload_binding_table(struct brw_context *brw)
 157 {
 158    /* BRW_NEW_VS_PROG_DATA */
 159    const struct brw_stage_prog_data *prog_data = brw->vs.base.prog_data;
 160    brw_upload_binding_table(brw,
 161                             _3DSTATE_BINDING_TABLE_POINTERS_VS,
 162                             BRW_NEW_VS_BINDING_TABLE, prog_data,
 163                             &brw->vs.base);
 164 }
 165
 166 const struct brw_tracked_state brw_vs_binding_table = {
 167    .dirty = {
 168       .mesa = 0,
 169       .brw = BRW_NEW_BATCH |
 170              BRW_NEW_VS_CONSTBUF |
 171              BRW_NEW_VS_PROG_DATA |
 172              BRW_NEW_SURFACES,
 173    },
 174    .emit = brw_vs_upload_binding_table,
 175 };
 176
 177
 178 /** Upload the PS binding table. */
 179 static void
 180 brw_upload_wm_binding_table(struct brw_context *brw)
 181 {
 182    /* BRW_NEW_FS_PROG_DATA */
 183    const struct brw_stage_prog_data *prog_data = brw->wm.base.prog_data;
 184    brw_upload_binding_table(brw,
 185                             _3DSTATE_BINDING_TABLE_POINTERS_PS,
 186                             BRW_NEW_PS_BINDING_TABLE, prog_data,
 187                             &brw->wm.base);
 188 }
 189
 190 const struct brw_tracked_state brw_wm_binding_table = {
 191    .dirty = {
 192       .mesa = 0,
 193       .brw = BRW_NEW_BATCH |
 194              BRW_NEW_FS_PROG_DATA |
 195              BRW_NEW_SURFACES,
 196    },
 197    .emit = brw_upload_wm_binding_table,
 198 };
 199
 200 /** Upload the GS binding table (if GS is active). */
 201 static void
 202 brw_gs_upload_binding_table(struct brw_context *brw)
 203 {
 204    /* If there's no GS, skip changing anything. */
 205    if (brw->geometry_program == NULL)
 206       return;
 207
 208    /* BRW_NEW_GS_PROG_DATA */
 209    const struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data;
 210    brw_upload_binding_table(brw,
 211                             _3DSTATE_BINDING_TABLE_POINTERS_GS,
 212                             BRW_NEW_GS_BINDING_TABLE, prog_data,
 213                             &brw->gs.base);
 214 }
 215
 216 const struct brw_tracked_state brw_gs_binding_table = {
 217    .dirty = {
 218       .mesa = 0,
 219       .brw = BRW_NEW_BATCH |
 220              BRW_NEW_GS_CONSTBUF |
 221              BRW_NEW_GS_PROG_DATA |
 222              BRW_NEW_SURFACES,
 223    },
 224    .emit = brw_gs_upload_binding_table,
 225 };
 226
 227 /**
 228  * Edit a single entry in a hardware-generated binding table
 229  */
 230 void
 231 gen7_edit_hw_binding_table_entry(struct brw_context *brw,
 232                                  gl_shader_stage stage,
 233                                  uint32_t index,
 234                                  uint32_t surf_offset)
 235 {
 236    assert(stage < ARRAY_SIZE(stage_to_bt_edit));
 237    assert(stage_to_bt_edit[stage]);
 238
 239    uint32_t dw2 = SET_FIELD(index, BRW_BINDING_TABLE_INDEX) |
 240       (brw->gen >= 8 ? GEN8_SURFACE_STATE_EDIT(surf_offset) :
 241        HSW_SURFACE_STATE_EDIT(surf_offset));
 242
 243    BEGIN_BATCH(3);
 244    OUT_BATCH(stage_to_bt_edit[stage] << 16 | (3 - 2));
 245    OUT_BATCH(BRW_BINDING_TABLE_EDIT_TARGET_ALL);
 246    OUT_BATCH(dw2);
 247    ADVANCE_BATCH();
 248 }
 249
 250 /**
 251  * Upload a whole hardware binding table for the given stage.
 252  *
 253  * Takes an array of surface offsets and the number of binding table
 254  * entries.
 255  */
 256 void
 257 gen7_update_binding_table_from_array(struct brw_context *brw,
 258                                      gl_shader_stage stage,
 259                                      const uint32_t* binding_table,
 260                                      int num_surfaces)
 261 {
 262    uint32_t dw2 = 0;
 263
 264    assert(stage < ARRAY_SIZE(stage_to_bt_edit));
 265    assert(stage_to_bt_edit[stage]);
 266
 267    BEGIN_BATCH(num_surfaces + 2);
 268    OUT_BATCH(stage_to_bt_edit[stage] << 16 | num_surfaces);
 269    OUT_BATCH(BRW_BINDING_TABLE_EDIT_TARGET_ALL);
 270    for (int i = 0; i < num_surfaces; i++) {
 271       dw2 = SET_FIELD(i, BRW_BINDING_TABLE_INDEX) |
 272          (brw->gen >= 8 ? GEN8_SURFACE_STATE_EDIT(binding_table[i]) :
 273           HSW_SURFACE_STATE_EDIT(binding_table[i]));
 274       OUT_BATCH(dw2);
 275    }
 276    ADVANCE_BATCH();
 277 }
 278
 279 /**
 280  * Disable hardware binding table support, falling back to the
 281  * older software-generated binding table mechanism.
 282  */
 283 void
 284 gen7_disable_hw_binding_tables(struct brw_context *brw)
 285 {
 286    if (!brw->use_resource_streamer)
 287       return;
 288    /* From the Haswell PRM, Volume 7: 3D Media GPGPU,
 289     * 3DSTATE_BINDING_TABLE_POOL_ALLOC > Programming Note:
 290     *
 291     * "When switching between HW and SW binding table generation, SW must
 292     * issue a state cache invalidate."
 293     */
 294    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
 295
 296    int pkt_len = brw->gen >= 8 ? 4 : 3;
 297
 298    BEGIN_BATCH(pkt_len);
 299    OUT_BATCH(_3DSTATE_BINDING_TABLE_POOL_ALLOC << 16 | (pkt_len - 2));
 300    if (brw->gen >= 8) {
 301       OUT_BATCH(0);
 302       OUT_BATCH(0);
 303       OUT_BATCH(0);
 304    } else {
 305       OUT_BATCH(HSW_BT_POOL_ALLOC_MUST_BE_ONE);
 306       OUT_BATCH(0);
 307    }
 308    ADVANCE_BATCH();
 309 }
 310
 311 /**
 312  * Enable hardware binding tables and set up the binding table pool.
 313  */
 314 static void
 315 gen7_enable_hw_binding_tables(struct brw_context *brw)
 316 {
 317    if (!brw->use_resource_streamer)
 318       return;
 319
 320    if (!brw->hw_bt_pool.bo) {
 321       /* We use a single re-usable buffer object for the lifetime of the
 322        * context and size it to maximum allowed binding tables that can be
 323        * programmed per batch:
 324        *
 325        * From the Haswell PRM, Volume 7: 3D Media GPGPU,
 326        * 3DSTATE_BINDING_TABLE_POOL_ALLOC > Programming Note:
 327        * "A maximum of 16,383 Binding tables are allowed in any batch buffer"
 328        */
 329       static const int max_size = 16383 * 4;
 330       brw->hw_bt_pool.bo = drm_intel_bo_alloc(brw->bufmgr, "hw_bt",
 331                                               max_size, 64);
 332       brw->hw_bt_pool.next_offset = 0;
 333    }
 334
 335    /* From the Haswell PRM, Volume 7: 3D Media GPGPU,
 336     * 3DSTATE_BINDING_TABLE_POOL_ALLOC > Programming Note:
 337     *
 338     * "When switching between HW and SW binding table generation, SW must
 339     * issue a state cache invalidate."
 340     */
 341    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
 342
 343    int pkt_len = brw->gen >= 8 ? 4 : 3;
 344    uint32_t dw1 = BRW_HW_BINDING_TABLE_ENABLE;
 345    if (brw->is_haswell) {
 346       dw1 |= SET_FIELD(GEN7_MOCS_L3, GEN7_HW_BT_POOL_MOCS) |
 347              HSW_BT_POOL_ALLOC_MUST_BE_ONE;
 348    } else if (brw->gen >= 8) {
 349       dw1 |= BDW_MOCS_WB;
 350    }
 351
 352    BEGIN_BATCH(pkt_len);
 353    OUT_BATCH(_3DSTATE_BINDING_TABLE_POOL_ALLOC << 16 | (pkt_len - 2));
 354    if (brw->gen >= 8) {
 355       OUT_RELOC64(brw->hw_bt_pool.bo, I915_GEM_DOMAIN_SAMPLER, 0, dw1);
 356       OUT_BATCH(brw->hw_bt_pool.bo->size);
 357    } else {
 358       OUT_RELOC(brw->hw_bt_pool.bo, I915_GEM_DOMAIN_SAMPLER, 0, dw1);
 359       OUT_RELOC(brw->hw_bt_pool.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 360              brw->hw_bt_pool.bo->size);
 361    }
 362    ADVANCE_BATCH();
 363 }
 364
 365 void
 366 gen7_reset_hw_bt_pool_offsets(struct brw_context *brw)
 367 {
 368    brw->hw_bt_pool.next_offset = 0;
 369 }
 370
 371 const struct brw_tracked_state gen7_hw_binding_tables = {
 372    .dirty = {
 373       .mesa = 0,
 374       .brw = BRW_NEW_BATCH,
 375    },
 376    .emit = gen7_enable_hw_binding_tables
 377 };
 378
 379 /** @} */
 380
 381 /**
 382  * State atoms which emit 3DSTATE packets to update the binding table pointers.
 383  *  @{
 384  */
 385
 386 /**
 387  * (Gen4-5) Upload the binding table pointers for all shader stages.
 388  *
 389  * The binding table pointers are relative to the surface state base address,
 390  * which points at the batchbuffer containing the streamed batch state.
 391  */
 392 static void
 393 gen4_upload_binding_table_pointers(struct brw_context *brw)
 394 {
 395    BEGIN_BATCH(6);
 396    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2));
 397    OUT_BATCH(brw->vs.base.bind_bo_offset);
 398    OUT_BATCH(0); /* gs */
 399    OUT_BATCH(0); /* clip */
 400    OUT_BATCH(0); /* sf */
 401    OUT_BATCH(brw->wm.base.bind_bo_offset);
 402    ADVANCE_BATCH();
 403 }
 404
 405 const struct brw_tracked_state brw_binding_table_pointers = {
 406    .dirty = {
 407       .mesa = 0,
 408       .brw = BRW_NEW_BATCH |
 409              BRW_NEW_GS_BINDING_TABLE |
 410              BRW_NEW_PS_BINDING_TABLE |
 411              BRW_NEW_STATE_BASE_ADDRESS |
 412              BRW_NEW_VS_BINDING_TABLE,
 413    },
 414    .emit = gen4_upload_binding_table_pointers,
 415 };
 416
 417 /**
 418  * (Sandybridge Only) Upload the binding table pointers for all shader stages.
 419  *
 420  * The binding table pointers are relative to the surface state base address,
 421  * which points at the batchbuffer containing the streamed batch state.
 422  */
 423 static void
 424 gen6_upload_binding_table_pointers(struct brw_context *brw)
 425 {
 426    BEGIN_BATCH(4);
 427    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 |
 428              GEN6_BINDING_TABLE_MODIFY_VS |
 429              GEN6_BINDING_TABLE_MODIFY_GS |
 430              GEN6_BINDING_TABLE_MODIFY_PS |
 431              (4 - 2));
 432    OUT_BATCH(brw->vs.base.bind_bo_offset); /* vs */
 433    if (brw->ff_gs.prog_active)
 434       OUT_BATCH(brw->ff_gs.bind_bo_offset); /* gs */
 435    else
 436       OUT_BATCH(brw->gs.base.bind_bo_offset); /* gs */
 437    OUT_BATCH(brw->wm.base.bind_bo_offset); /* wm/ps */
 438    ADVANCE_BATCH();
 439 }
 440
 441 const struct brw_tracked_state gen6_binding_table_pointers = {
 442    .dirty = {
 443       .mesa = 0,
 444       .brw = BRW_NEW_BATCH |
 445              BRW_NEW_GS_BINDING_TABLE |
 446              BRW_NEW_PS_BINDING_TABLE |
 447              BRW_NEW_STATE_BASE_ADDRESS |
 448              BRW_NEW_VS_BINDING_TABLE,
 449    },
 450    .emit = gen6_upload_binding_table_pointers,
 451 };
 452
 453 /** @} */