src/mesa/drivers/dri/i965/brw_binding_tables.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * \file brw_binding_tables.c
  26  *
  27  * State atoms which upload the "binding table" for each shader stage.
  28  *
  29  * Binding tables map a numeric "surface index" to the SURFACE_STATE structure
  30  * for a currently bound surface.  This allows SEND messages (such as sampler
  31  * or data port messages) to refer to a particular surface by number, rather
  32  * than by pointer.
  33  *
  34  * The binding table is stored as a (sparse) array of SURFACE_STATE entries;
  35  * surface indexes are simply indexes into the array.  The ordering of the
  36  * entries is entirely left up to software; see the SURF_INDEX_* macros in
  37  * brw_context.h to see our current layout.
  38  */
  39
  40 #include "main/mtypes.h"
  41
  42 #include "brw_context.h"
  43 #include "brw_defines.h"
  44 #include "brw_state.h"
  45 #include "intel_batchbuffer.h"
  46
  47 /**
  48  * Upload a shader stage's binding table as indirect state.
  49  *
  50  * This copies brw_stage_state::surf_offset[] into the indirect state section
  51  * of the batchbuffer (allocated by brw_state_batch()).
  52  */
  53 void
  54 brw_upload_binding_table(struct brw_context *brw,
  55                          uint32_t packet_name,
  56                          GLbitfield brw_new_binding_table,
  57                          const struct brw_stage_prog_data *prog_data,
  58                          struct brw_stage_state *stage_state)
  59 {
  60    if (prog_data->binding_table.size_bytes == 0) {
  61       /* There are no surfaces; skip making the binding table altogether. */
  62       if (stage_state->bind_bo_offset == 0 && brw->gen < 9)
  63          return;
  64
  65       stage_state->bind_bo_offset = 0;
  66    } else {
  67       /* Upload a new binding table. */
  68       if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
  69          brw->vtbl.emit_buffer_surface_state(
  70             brw, &stage_state->surf_offset[
  71                     prog_data->binding_table.shader_time_start],
  72             brw->shader_time.bo, 0, BRW_SURFACEFORMAT_RAW,
  73             brw->shader_time.bo->size, 1, true);
  74       }
  75
  76       uint32_t *bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
  77                                        prog_data->binding_table.size_bytes, 32,
  78                                        &stage_state->bind_bo_offset);
  79
  80       /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
  81       memcpy(bind, stage_state->surf_offset,
  82              prog_data->binding_table.size_bytes);
  83    }
  84
  85    brw->ctx.NewDriverState |= brw_new_binding_table;
  86
  87    if (brw->gen >= 7) {
  88       BEGIN_BATCH(2);
  89       OUT_BATCH(packet_name << 16 | (2 - 2));
  90       OUT_BATCH(stage_state->bind_bo_offset);
  91       ADVANCE_BATCH();
  92    }
  93 }
  94
  95 /**
  96  * State atoms which upload the binding table for a particular shader stage.
  97  *  @{
  98  */
  99
 100 /** Upload the VS binding table. */
 101 static void
 102 brw_vs_upload_binding_table(struct brw_context *brw)
 103 {
 104    /* BRW_NEW_VS_PROG_DATA */
 105    const struct brw_stage_prog_data *prog_data = brw->vs.base.prog_data;
 106    brw_upload_binding_table(brw,
 107                             _3DSTATE_BINDING_TABLE_POINTERS_VS,
 108                             BRW_NEW_VS_BINDING_TABLE, prog_data,
 109                             &brw->vs.base);
 110 }
 111
 112 const struct brw_tracked_state brw_vs_binding_table = {
 113    .dirty = {
 114       .mesa = 0,
 115       .brw = BRW_NEW_BATCH |
 116              BRW_NEW_VS_CONSTBUF |
 117              BRW_NEW_VS_PROG_DATA |
 118              BRW_NEW_SURFACES,
 119    },
 120    .emit = brw_vs_upload_binding_table,
 121 };
 122
 123
 124 /** Upload the PS binding table. */
 125 static void
 126 brw_upload_wm_binding_table(struct brw_context *brw)
 127 {
 128    /* BRW_NEW_FS_PROG_DATA */
 129    const struct brw_stage_prog_data *prog_data = brw->wm.base.prog_data;
 130    brw_upload_binding_table(brw,
 131                             _3DSTATE_BINDING_TABLE_POINTERS_PS,
 132                             BRW_NEW_PS_BINDING_TABLE, prog_data,
 133                             &brw->wm.base);
 134 }
 135
 136 const struct brw_tracked_state brw_wm_binding_table = {
 137    .dirty = {
 138       .mesa = 0,
 139       .brw = BRW_NEW_BATCH |
 140              BRW_NEW_FS_PROG_DATA |
 141              BRW_NEW_SURFACES,
 142    },
 143    .emit = brw_upload_wm_binding_table,
 144 };
 145
 146 /** Upload the GS binding table (if GS is active). */
 147 static void
 148 brw_gs_upload_binding_table(struct brw_context *brw)
 149 {
 150    /* If there's no GS, skip changing anything. */
 151    if (brw->geometry_program == NULL)
 152       return;
 153
 154    /* BRW_NEW_GS_PROG_DATA */
 155    const struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data;
 156    brw_upload_binding_table(brw,
 157                             _3DSTATE_BINDING_TABLE_POINTERS_GS,
 158                             BRW_NEW_GS_BINDING_TABLE, prog_data,
 159                             &brw->gs.base);
 160 }
 161
 162 const struct brw_tracked_state brw_gs_binding_table = {
 163    .dirty = {
 164       .mesa = 0,
 165       .brw = BRW_NEW_BATCH |
 166              BRW_NEW_GS_CONSTBUF |
 167              BRW_NEW_GS_PROG_DATA |
 168              BRW_NEW_SURFACES,
 169    },
 170    .emit = brw_gs_upload_binding_table,
 171 };
 172
 173 /**
 174  * Disable hardware binding table support, falling back to the
 175  * older software-generated binding table mechanism.
 176  */
 177 void
 178 gen7_disable_hw_binding_tables(struct brw_context *brw)
 179 {
 180    if (!brw->use_resource_streamer)
 181       return;
 182    /* From the Haswell PRM, Volume 7: 3D Media GPGPU,
 183     * 3DSTATE_BINDING_TABLE_POOL_ALLOC > Programming Note:
 184     *
 185     * "When switching between HW and SW binding table generation, SW must
 186     * issue a state cache invalidate."
 187     */
 188    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
 189
 190    int pkt_len = brw->gen >= 8 ? 4 : 3;
 191
 192    BEGIN_BATCH(pkt_len);
 193    OUT_BATCH(_3DSTATE_BINDING_TABLE_POOL_ALLOC << 16 | (pkt_len - 2));
 194    if (brw->gen >= 8) {
 195       OUT_BATCH(0);
 196       OUT_BATCH(0);
 197       OUT_BATCH(0);
 198    } else {
 199       OUT_BATCH(HSW_BT_POOL_ALLOC_MUST_BE_ONE);
 200       OUT_BATCH(0);
 201    }
 202    ADVANCE_BATCH();
 203 }
 204
 205 /**
 206  * Enable hardware binding tables and set up the binding table pool.
 207  */
 208 void
 209 gen7_enable_hw_binding_tables(struct brw_context *brw)
 210 {
 211    if (!brw->use_resource_streamer)
 212       return;
 213
 214    if (!brw->hw_bt_pool.bo) {
 215       /* We use a single re-usable buffer object for the lifetime of the
 216        * context and size it to maximum allowed binding tables that can be
 217        * programmed per batch:
 218        *
 219        * From the Haswell PRM, Volume 7: 3D Media GPGPU,
 220        * 3DSTATE_BINDING_TABLE_POOL_ALLOC > Programming Note:
 221        * "A maximum of 16,383 Binding tables are allowed in any batch buffer"
 222        */
 223       static const int max_size = 16383 * 4;
 224       brw->hw_bt_pool.bo = drm_intel_bo_alloc(brw->bufmgr, "hw_bt",
 225                                               max_size, 64);
 226       brw->hw_bt_pool.next_offset = 0;
 227    }
 228
 229    /* From the Haswell PRM, Volume 7: 3D Media GPGPU,
 230     * 3DSTATE_BINDING_TABLE_POOL_ALLOC > Programming Note:
 231     *
 232     * "When switching between HW and SW binding table generation, SW must
 233     * issue a state cache invalidate."
 234     */
 235    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
 236
 237    int pkt_len = brw->gen >= 8 ? 4 : 3;
 238    uint32_t dw1 = BRW_HW_BINDING_TABLE_ENABLE;
 239    if (brw->is_haswell) {
 240       dw1 |= SET_FIELD(GEN7_MOCS_L3, GEN7_HW_BT_POOL_MOCS) |
 241              HSW_BT_POOL_ALLOC_MUST_BE_ONE;
 242    } else if (brw->gen >= 8) {
 243       dw1 |= BDW_MOCS_WB;
 244    }
 245
 246    BEGIN_BATCH(pkt_len);
 247    OUT_BATCH(_3DSTATE_BINDING_TABLE_POOL_ALLOC << 16 | (pkt_len - 2));
 248    if (brw->gen >= 8) {
 249       OUT_RELOC64(brw->hw_bt_pool.bo, I915_GEM_DOMAIN_SAMPLER, 0, dw1);
 250       OUT_BATCH(brw->hw_bt_pool.bo->size);
 251    } else {
 252       OUT_RELOC(brw->hw_bt_pool.bo, I915_GEM_DOMAIN_SAMPLER, 0, dw1);
 253       OUT_RELOC(brw->hw_bt_pool.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 254              brw->hw_bt_pool.bo->size);
 255    }
 256    ADVANCE_BATCH();
 257 }
 258
 259 void
 260 gen7_reset_hw_bt_pool_offsets(struct brw_context *brw)
 261 {
 262    brw->hw_bt_pool.next_offset = 0;
 263 }
 264
 265 const struct brw_tracked_state gen7_hw_binding_tables = {
 266    .dirty = {
 267       .mesa = 0,
 268       .brw = BRW_NEW_BATCH,
 269    },
 270    .emit = gen7_enable_hw_binding_tables
 271 };
 272
 273 /** @} */
 274
 275 /**
 276  * State atoms which emit 3DSTATE packets to update the binding table pointers.
 277  *  @{
 278  */
 279
 280 /**
 281  * (Gen4-5) Upload the binding table pointers for all shader stages.
 282  *
 283  * The binding table pointers are relative to the surface state base address,
 284  * which points at the batchbuffer containing the streamed batch state.
 285  */
 286 static void
 287 gen4_upload_binding_table_pointers(struct brw_context *brw)
 288 {
 289    BEGIN_BATCH(6);
 290    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2));
 291    OUT_BATCH(brw->vs.base.bind_bo_offset);
 292    OUT_BATCH(0); /* gs */
 293    OUT_BATCH(0); /* clip */
 294    OUT_BATCH(0); /* sf */
 295    OUT_BATCH(brw->wm.base.bind_bo_offset);
 296    ADVANCE_BATCH();
 297 }
 298
 299 const struct brw_tracked_state brw_binding_table_pointers = {
 300    .dirty = {
 301       .mesa = 0,
 302       .brw = BRW_NEW_BATCH |
 303              BRW_NEW_GS_BINDING_TABLE |
 304              BRW_NEW_PS_BINDING_TABLE |
 305              BRW_NEW_STATE_BASE_ADDRESS |
 306              BRW_NEW_VS_BINDING_TABLE,
 307    },
 308    .emit = gen4_upload_binding_table_pointers,
 309 };
 310
 311 /**
 312  * (Sandybridge Only) Upload the binding table pointers for all shader stages.
 313  *
 314  * The binding table pointers are relative to the surface state base address,
 315  * which points at the batchbuffer containing the streamed batch state.
 316  */
 317 static void
 318 gen6_upload_binding_table_pointers(struct brw_context *brw)
 319 {
 320    BEGIN_BATCH(4);
 321    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 |
 322              GEN6_BINDING_TABLE_MODIFY_VS |
 323              GEN6_BINDING_TABLE_MODIFY_GS |
 324              GEN6_BINDING_TABLE_MODIFY_PS |
 325              (4 - 2));
 326    OUT_BATCH(brw->vs.base.bind_bo_offset); /* vs */
 327    if (brw->ff_gs.prog_active)
 328       OUT_BATCH(brw->ff_gs.bind_bo_offset); /* gs */
 329    else
 330       OUT_BATCH(brw->gs.base.bind_bo_offset); /* gs */
 331    OUT_BATCH(brw->wm.base.bind_bo_offset); /* wm/ps */
 332    ADVANCE_BATCH();
 333 }
 334
 335 const struct brw_tracked_state gen6_binding_table_pointers = {
 336    .dirty = {
 337       .mesa = 0,
 338       .brw = BRW_NEW_BATCH |
 339              BRW_NEW_GS_BINDING_TABLE |
 340              BRW_NEW_PS_BINDING_TABLE |
 341              BRW_NEW_STATE_BASE_ADDRESS |
 342              BRW_NEW_VS_BINDING_TABLE,
 343    },
 344    .emit = gen6_upload_binding_table_pointers,
 345 };
 346
 347 /** @} */