2 * Copyright © 2013 Intel Corporation
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25 * \file brw_binding_tables.c
27 * State atoms which upload the "binding table" for each shader stage.
29 * Binding tables map a numeric "surface index" to the SURFACE_STATE structure
30 * for a currently bound surface. This allows SEND messages (such as sampler
31 * or data port messages) to refer to a particular surface by number, rather
34 * The binding table is stored as a (sparse) array of SURFACE_STATE entries;
35 * surface indexes are simply indexes into the array. The ordering of the
36 * entries is entirely left up to software; see the SURF_INDEX_* macros in
37 * brw_context.h to see our current layout.
40 #include "main/mtypes.h"
42 #include "brw_context.h"
43 #include "brw_defines.h"
44 #include "brw_state.h"
45 #include "intel_batchbuffer.h"
47 static const GLuint stage_to_bt_edit
[] = {
48 [MESA_SHADER_VERTEX
] = _3DSTATE_BINDING_TABLE_EDIT_VS
,
49 [MESA_SHADER_GEOMETRY
] = _3DSTATE_BINDING_TABLE_EDIT_GS
,
50 [MESA_SHADER_FRAGMENT
] = _3DSTATE_BINDING_TABLE_EDIT_PS
,
54 reserve_hw_bt_space(struct brw_context
*brw
, unsigned bytes
)
56 /* From the Broadwell PRM, Volume 16, "Workarounds",
57 * WaStateBindingTableOverfetch:
58 * "HW over-fetches two cache lines of binding table indices. When
59 * using the resource streamer, SW needs to pad binding table pointer
60 * updates with an additional two cache lines."
62 * Cache lines are 64 bytes, so we subtract 128 bytes from the size of
63 * the binding table pool buffer.
65 if (brw
->hw_bt_pool
.next_offset
+ bytes
>= brw
->hw_bt_pool
.bo
->size
- 128) {
66 gen7_reset_hw_bt_pool_offsets(brw
);
69 uint32_t offset
= brw
->hw_bt_pool
.next_offset
;
71 /* From the Haswell PRM, Volume 2b: Command Reference: Instructions,
72 * 3DSTATE_BINDING_TABLE_POINTERS_xS:
74 * "If HW Binding Table is enabled, the offset is relative to the
75 * Binding Table Pool Base Address and the alignment is 64 bytes."
77 brw
->hw_bt_pool
.next_offset
+= ALIGN(bytes
, 64);
83 * Upload a shader stage's binding table as indirect state.
85 * This copies brw_stage_state::surf_offset[] into the indirect state section
86 * of the batchbuffer (allocated by brw_state_batch()).
89 brw_upload_binding_table(struct brw_context
*brw
,
91 const struct brw_stage_prog_data
*prog_data
,
92 struct brw_stage_state
*stage_state
)
94 if (prog_data
->binding_table
.size_bytes
== 0) {
95 /* There are no surfaces; skip making the binding table altogether. */
96 if (stage_state
->bind_bo_offset
== 0 && brw
->gen
< 9)
99 stage_state
->bind_bo_offset
= 0;
101 /* Upload a new binding table. */
102 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
103 brw
->vtbl
.emit_buffer_surface_state(
104 brw
, &stage_state
->surf_offset
[
105 prog_data
->binding_table
.shader_time_start
],
106 brw
->shader_time
.bo
, 0, BRW_SURFACEFORMAT_RAW
,
107 brw
->shader_time
.bo
->size
, 1, true);
109 /* When RS is enabled use hw-binding table uploads, otherwise fallback to
112 if (brw
->use_resource_streamer
) {
113 gen7_update_binding_table_from_array(brw
, stage_state
->stage
,
114 stage_state
->surf_offset
,
115 prog_data
->binding_table
118 uint32_t *bind
= brw_state_batch(brw
, AUB_TRACE_BINDING_TABLE
,
119 prog_data
->binding_table
.size_bytes
,
121 &stage_state
->bind_bo_offset
);
123 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
124 memcpy(bind
, stage_state
->surf_offset
,
125 prog_data
->binding_table
.size_bytes
);
129 brw
->ctx
.NewDriverState
|= BRW_NEW_BINDING_TABLE_POINTERS
;
132 if (brw
->use_resource_streamer
) {
133 stage_state
->bind_bo_offset
=
134 reserve_hw_bt_space(brw
, prog_data
->binding_table
.size_bytes
);
137 OUT_BATCH(packet_name
<< 16 | (2 - 2));
138 /* Align SurfaceStateOffset[16:6] format to [15:5] PS Binding Table field
139 * when hw-generated binding table is enabled.
141 OUT_BATCH(brw
->use_resource_streamer
?
142 (stage_state
->bind_bo_offset
>> 1) :
143 stage_state
->bind_bo_offset
);
149 * State atoms which upload the binding table for a particular shader stage.
153 /** Upload the VS binding table. */
155 brw_vs_upload_binding_table(struct brw_context
*brw
)
157 /* BRW_NEW_VS_PROG_DATA */
158 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
159 brw_upload_binding_table(brw
,
160 _3DSTATE_BINDING_TABLE_POINTERS_VS
,
165 const struct brw_tracked_state brw_vs_binding_table
= {
168 .brw
= BRW_NEW_BATCH
|
169 BRW_NEW_VS_CONSTBUF
|
170 BRW_NEW_VS_PROG_DATA
|
173 .emit
= brw_vs_upload_binding_table
,
177 /** Upload the PS binding table. */
179 brw_upload_wm_binding_table(struct brw_context
*brw
)
181 /* BRW_NEW_FS_PROG_DATA */
182 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
183 brw_upload_binding_table(brw
,
184 _3DSTATE_BINDING_TABLE_POINTERS_PS
,
189 const struct brw_tracked_state brw_wm_binding_table
= {
192 .brw
= BRW_NEW_BATCH
|
193 BRW_NEW_FS_PROG_DATA
|
196 .emit
= brw_upload_wm_binding_table
,
199 /** Upload the GS binding table (if GS is active). */
201 brw_gs_upload_binding_table(struct brw_context
*brw
)
203 /* If there's no GS, skip changing anything. */
204 if (brw
->geometry_program
== NULL
)
207 /* BRW_NEW_GS_PROG_DATA */
208 const struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
209 brw_upload_binding_table(brw
,
210 _3DSTATE_BINDING_TABLE_POINTERS_GS
,
215 const struct brw_tracked_state brw_gs_binding_table
= {
218 .brw
= BRW_NEW_BATCH
|
219 BRW_NEW_GS_CONSTBUF
|
220 BRW_NEW_GS_PROG_DATA
|
223 .emit
= brw_gs_upload_binding_table
,
227 * Edit a single entry in a hardware-generated binding table
230 gen7_edit_hw_binding_table_entry(struct brw_context
*brw
,
231 gl_shader_stage stage
,
233 uint32_t surf_offset
)
235 assert(stage
< ARRAY_SIZE(stage_to_bt_edit
));
236 assert(stage_to_bt_edit
[stage
]);
238 uint32_t dw2
= SET_FIELD(index
, BRW_BINDING_TABLE_INDEX
) |
239 (brw
->gen
>= 8 ? GEN8_SURFACE_STATE_EDIT(surf_offset
) :
240 HSW_SURFACE_STATE_EDIT(surf_offset
));
243 OUT_BATCH(stage_to_bt_edit
[stage
] << 16 | (3 - 2));
244 OUT_BATCH(BRW_BINDING_TABLE_EDIT_TARGET_ALL
);
250 * Upload a whole hardware binding table for the given stage.
252 * Takes an array of surface offsets and the number of binding table
256 gen7_update_binding_table_from_array(struct brw_context
*brw
,
257 gl_shader_stage stage
,
258 const uint32_t* binding_table
,
263 assert(stage
< ARRAY_SIZE(stage_to_bt_edit
));
264 assert(stage_to_bt_edit
[stage
]);
266 BEGIN_BATCH(num_surfaces
+ 2);
267 OUT_BATCH(stage_to_bt_edit
[stage
] << 16 | num_surfaces
);
268 OUT_BATCH(BRW_BINDING_TABLE_EDIT_TARGET_ALL
);
269 for (int i
= 0; i
< num_surfaces
; i
++) {
270 dw2
= SET_FIELD(i
, BRW_BINDING_TABLE_INDEX
) |
271 (brw
->gen
>= 8 ? GEN8_SURFACE_STATE_EDIT(binding_table
[i
]) :
272 HSW_SURFACE_STATE_EDIT(binding_table
[i
]));
279 * Disable hardware binding table support, falling back to the
280 * older software-generated binding table mechanism.
283 gen7_disable_hw_binding_tables(struct brw_context
*brw
)
285 if (!brw
->use_resource_streamer
)
287 /* From the Haswell PRM, Volume 7: 3D Media GPGPU,
288 * 3DSTATE_BINDING_TABLE_POOL_ALLOC > Programming Note:
290 * "When switching between HW and SW binding table generation, SW must
291 * issue a state cache invalidate."
293 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
295 int pkt_len
= brw
->gen
>= 8 ? 4 : 3;
297 BEGIN_BATCH(pkt_len
);
298 OUT_BATCH(_3DSTATE_BINDING_TABLE_POOL_ALLOC
<< 16 | (pkt_len
- 2));
304 OUT_BATCH(HSW_BT_POOL_ALLOC_MUST_BE_ONE
);
311 * Enable hardware binding tables and set up the binding table pool.
314 gen7_enable_hw_binding_tables(struct brw_context
*brw
)
316 if (!brw
->use_resource_streamer
)
319 if (!brw
->hw_bt_pool
.bo
) {
320 /* We use a single re-usable buffer object for the lifetime of the
321 * context and size it to maximum allowed binding tables that can be
322 * programmed per batch:
324 * From the Haswell PRM, Volume 7: 3D Media GPGPU,
325 * 3DSTATE_BINDING_TABLE_POOL_ALLOC > Programming Note:
326 * "A maximum of 16,383 Binding tables are allowed in any batch buffer"
328 static const int max_size
= 16383 * 4;
329 brw
->hw_bt_pool
.bo
= drm_intel_bo_alloc(brw
->bufmgr
, "hw_bt",
331 brw
->hw_bt_pool
.next_offset
= 0;
334 /* From the Haswell PRM, Volume 7: 3D Media GPGPU,
335 * 3DSTATE_BINDING_TABLE_POOL_ALLOC > Programming Note:
337 * "When switching between HW and SW binding table generation, SW must
338 * issue a state cache invalidate."
340 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
342 int pkt_len
= brw
->gen
>= 8 ? 4 : 3;
343 uint32_t dw1
= BRW_HW_BINDING_TABLE_ENABLE
;
344 if (brw
->is_haswell
) {
345 dw1
|= SET_FIELD(GEN7_MOCS_L3
, GEN7_HW_BT_POOL_MOCS
) |
346 HSW_BT_POOL_ALLOC_MUST_BE_ONE
;
347 } else if (brw
->gen
>= 8) {
351 BEGIN_BATCH(pkt_len
);
352 OUT_BATCH(_3DSTATE_BINDING_TABLE_POOL_ALLOC
<< 16 | (pkt_len
- 2));
354 OUT_RELOC64(brw
->hw_bt_pool
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, dw1
);
355 OUT_BATCH(brw
->hw_bt_pool
.bo
->size
);
357 OUT_RELOC(brw
->hw_bt_pool
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, dw1
);
358 OUT_RELOC(brw
->hw_bt_pool
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
359 brw
->hw_bt_pool
.bo
->size
);
365 gen7_reset_hw_bt_pool_offsets(struct brw_context
*brw
)
367 brw
->hw_bt_pool
.next_offset
= 0;
370 const struct brw_tracked_state gen7_hw_binding_tables
= {
373 .brw
= BRW_NEW_BATCH
,
375 .emit
= gen7_enable_hw_binding_tables
381 * State atoms which emit 3DSTATE packets to update the binding table pointers.
386 * (Gen4-5) Upload the binding table pointers for all shader stages.
388 * The binding table pointers are relative to the surface state base address,
389 * which points at the batchbuffer containing the streamed batch state.
392 gen4_upload_binding_table_pointers(struct brw_context
*brw
)
395 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 | (6 - 2));
396 OUT_BATCH(brw
->vs
.base
.bind_bo_offset
);
397 OUT_BATCH(0); /* gs */
398 OUT_BATCH(0); /* clip */
399 OUT_BATCH(0); /* sf */
400 OUT_BATCH(brw
->wm
.base
.bind_bo_offset
);
404 const struct brw_tracked_state brw_binding_table_pointers
= {
407 .brw
= BRW_NEW_BATCH
|
408 BRW_NEW_BINDING_TABLE_POINTERS
|
409 BRW_NEW_STATE_BASE_ADDRESS
,
411 .emit
= gen4_upload_binding_table_pointers
,
415 * (Sandybridge Only) Upload the binding table pointers for all shader stages.
417 * The binding table pointers are relative to the surface state base address,
418 * which points at the batchbuffer containing the streamed batch state.
421 gen6_upload_binding_table_pointers(struct brw_context
*brw
)
424 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 |
425 GEN6_BINDING_TABLE_MODIFY_VS
|
426 GEN6_BINDING_TABLE_MODIFY_GS
|
427 GEN6_BINDING_TABLE_MODIFY_PS
|
429 OUT_BATCH(brw
->vs
.base
.bind_bo_offset
); /* vs */
430 if (brw
->ff_gs
.prog_active
)
431 OUT_BATCH(brw
->ff_gs
.bind_bo_offset
); /* gs */
433 OUT_BATCH(brw
->gs
.base
.bind_bo_offset
); /* gs */
434 OUT_BATCH(brw
->wm
.base
.bind_bo_offset
); /* wm/ps */
438 const struct brw_tracked_state gen6_binding_table_pointers
= {
441 .brw
= BRW_NEW_BATCH
|
442 BRW_NEW_BINDING_TABLE_POINTERS
|
443 BRW_NEW_STATE_BASE_ADDRESS
,
445 .emit
= gen6_upload_binding_table_pointers
,