2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * \file brw_binding_tables.c
27 * State atoms which upload the "binding table" for each shader stage.
29 * Binding tables map a numeric "surface index" to the SURFACE_STATE structure
30 * for a currently bound surface. This allows SEND messages (such as sampler
31 * or data port messages) to refer to a particular surface by number, rather
34 * The binding table is stored as a (sparse) array of SURFACE_STATE entries;
35 * surface indexes are simply indexes into the array. The ordering of the
36 * entries is entirely left up to software; see the SURF_INDEX_* macros in
37 * brw_context.h to see our current layout.
40 #include "main/mtypes.h"
42 #include "brw_context.h"
43 #include "brw_defines.h"
44 #include "brw_state.h"
45 #include "intel_batchbuffer.h"
47 static const GLuint stage_to_bt_edit
[] = {
48 [MESA_SHADER_VERTEX
] = _3DSTATE_BINDING_TABLE_EDIT_VS
,
49 [MESA_SHADER_GEOMETRY
] = _3DSTATE_BINDING_TABLE_EDIT_GS
,
50 [MESA_SHADER_FRAGMENT
] = _3DSTATE_BINDING_TABLE_EDIT_PS
,
54 reserve_hw_bt_space(struct brw_context
*brw
, unsigned bytes
)
56 /* From the Broadwell PRM, Volume 16, "Workarounds",
57 * WaStateBindingTableOverfetch:
58 * "HW over-fetches two cache lines of binding table indices. When
59 * using the resource streamer, SW needs to pad binding table pointer
60 * updates with an additional two cache lines."
62 * Cache lines are 64 bytes, so we subtract 128 bytes from the size of
63 * the binding table pool buffer.
65 if (brw
->hw_bt_pool
.next_offset
+ bytes
>= brw
->hw_bt_pool
.bo
->size
- 128) {
66 gen7_reset_hw_bt_pool_offsets(brw
);
69 uint32_t offset
= brw
->hw_bt_pool
.next_offset
;
71 /* From the Haswell PRM, Volume 2b: Command Reference: Instructions,
72 * 3DSTATE_BINDING_TABLE_POINTERS_xS:
74 * "If HW Binding Table is enabled, the offset is relative to the
75 * Binding Table Pool Base Address and the alignment is 64 bytes."
77 brw
->hw_bt_pool
.next_offset
+= ALIGN(bytes
, 64);
83 * Upload a shader stage's binding table as indirect state.
85 * This copies brw_stage_state::surf_offset[] into the indirect state section
86 * of the batchbuffer (allocated by brw_state_batch()).
89 brw_upload_binding_table(struct brw_context
*brw
,
91 const struct brw_stage_prog_data
*prog_data
,
92 struct brw_stage_state
*stage_state
)
94 if (prog_data
->binding_table
.size_bytes
== 0) {
95 /* There are no surfaces; skip making the binding table altogether. */
96 if (stage_state
->bind_bo_offset
== 0 && brw
->gen
< 9)
99 stage_state
->bind_bo_offset
= 0;
101 /* Upload a new binding table. */
102 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
103 brw
->vtbl
.emit_buffer_surface_state(
104 brw
, &stage_state
->surf_offset
[
105 prog_data
->binding_table
.shader_time_start
],
106 brw
->shader_time
.bo
, 0, BRW_SURFACEFORMAT_RAW
,
107 brw
->shader_time
.bo
->size
, 1, true);
109 /* When RS is enabled use hw-binding table uploads, otherwise fallback to
112 if (brw
->use_resource_streamer
) {
113 gen7_update_binding_table_from_array(brw
, stage_state
->stage
,
114 stage_state
->surf_offset
,
115 prog_data
->binding_table
118 uint32_t *bind
= brw_state_batch(brw
, AUB_TRACE_BINDING_TABLE
,
119 prog_data
->binding_table
.size_bytes
,
121 &stage_state
->bind_bo_offset
);
123 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
124 memcpy(bind
, stage_state
->surf_offset
,
125 prog_data
->binding_table
.size_bytes
);
129 brw
->ctx
.NewDriverState
|= BRW_NEW_BINDING_TABLE_POINTERS
;
132 if (brw
->use_resource_streamer
) {
133 stage_state
->bind_bo_offset
=
134 reserve_hw_bt_space(brw
, prog_data
->binding_table
.size_bytes
);
137 OUT_BATCH(packet_name
<< 16 | (2 - 2));
138 /* Align SurfaceStateOffset[16:6] format to [15:5] PS Binding Table field
139 * when hw-generated binding table is enabled.
141 OUT_BATCH(brw
->use_resource_streamer
?
142 (stage_state
->bind_bo_offset
>> 1) :
143 stage_state
->bind_bo_offset
);
149 * State atoms which upload the binding table for a particular shader stage.
153 /** Upload the VS binding table. */
155 brw_vs_upload_binding_table(struct brw_context
*brw
)
157 /* BRW_NEW_VS_PROG_DATA */
158 const struct brw_stage_prog_data
*prog_data
= brw
->vs
.base
.prog_data
;
159 brw_upload_binding_table(brw
,
160 _3DSTATE_BINDING_TABLE_POINTERS_VS
,
165 const struct brw_tracked_state brw_vs_binding_table
= {
168 .brw
= BRW_NEW_BATCH
|
169 BRW_NEW_VS_CONSTBUF
|
170 BRW_NEW_VS_PROG_DATA
|
173 .emit
= brw_vs_upload_binding_table
,
177 /** Upload the PS binding table. */
179 brw_upload_wm_binding_table(struct brw_context
*brw
)
181 /* BRW_NEW_FS_PROG_DATA */
182 const struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
183 brw_upload_binding_table(brw
,
184 _3DSTATE_BINDING_TABLE_POINTERS_PS
,
189 const struct brw_tracked_state brw_wm_binding_table
= {
192 .brw
= BRW_NEW_BATCH
|
193 BRW_NEW_FS_PROG_DATA
|
196 .emit
= brw_upload_wm_binding_table
,
199 /** Upload the TCS binding table (if tessellation stages are active). */
201 brw_tcs_upload_binding_table(struct brw_context
*brw
)
203 /* Skip if the tessellation stages are disabled. */
204 if (brw
->tess_eval_program
== NULL
)
207 /* BRW_NEW_TCS_PROG_DATA */
208 const struct brw_stage_prog_data
*prog_data
= brw
->tcs
.base
.prog_data
;
209 brw_upload_binding_table(brw
,
210 _3DSTATE_BINDING_TABLE_POINTERS_HS
,
215 const struct brw_tracked_state brw_tcs_binding_table
= {
218 .brw
= BRW_NEW_BATCH
|
219 BRW_NEW_DEFAULT_TESS_LEVELS
|
221 BRW_NEW_TCS_CONSTBUF
|
222 BRW_NEW_TCS_PROG_DATA
,
224 .emit
= brw_tcs_upload_binding_table
,
227 /** Upload the TES binding table (if TES is active). */
229 brw_tes_upload_binding_table(struct brw_context
*brw
)
231 /* If there's no TES, skip changing anything. */
232 if (brw
->tess_eval_program
== NULL
)
235 /* BRW_NEW_TES_PROG_DATA */
236 const struct brw_stage_prog_data
*prog_data
= brw
->tes
.base
.prog_data
;
237 brw_upload_binding_table(brw
,
238 _3DSTATE_BINDING_TABLE_POINTERS_DS
,
243 const struct brw_tracked_state brw_tes_binding_table
= {
246 .brw
= BRW_NEW_BATCH
|
248 BRW_NEW_TES_CONSTBUF
|
249 BRW_NEW_TES_PROG_DATA
,
251 .emit
= brw_tes_upload_binding_table
,
254 /** Upload the GS binding table (if GS is active). */
256 brw_gs_upload_binding_table(struct brw_context
*brw
)
258 /* If there's no GS, skip changing anything. */
259 if (brw
->geometry_program
== NULL
)
262 /* BRW_NEW_GS_PROG_DATA */
263 const struct brw_stage_prog_data
*prog_data
= brw
->gs
.base
.prog_data
;
264 brw_upload_binding_table(brw
,
265 _3DSTATE_BINDING_TABLE_POINTERS_GS
,
270 const struct brw_tracked_state brw_gs_binding_table
= {
273 .brw
= BRW_NEW_BATCH
|
274 BRW_NEW_GS_CONSTBUF
|
275 BRW_NEW_GS_PROG_DATA
|
278 .emit
= brw_gs_upload_binding_table
,
282 * Edit a single entry in a hardware-generated binding table
285 gen7_edit_hw_binding_table_entry(struct brw_context
*brw
,
286 gl_shader_stage stage
,
288 uint32_t surf_offset
)
290 assert(stage
< ARRAY_SIZE(stage_to_bt_edit
));
291 assert(stage_to_bt_edit
[stage
]);
293 uint32_t dw2
= SET_FIELD(index
, BRW_BINDING_TABLE_INDEX
) |
294 (brw
->gen
>= 8 ? GEN8_SURFACE_STATE_EDIT(surf_offset
) :
295 HSW_SURFACE_STATE_EDIT(surf_offset
));
298 OUT_BATCH(stage_to_bt_edit
[stage
] << 16 | (3 - 2));
299 OUT_BATCH(BRW_BINDING_TABLE_EDIT_TARGET_ALL
);
305 * Upload a whole hardware binding table for the given stage.
307 * Takes an array of surface offsets and the number of binding table
311 gen7_update_binding_table_from_array(struct brw_context
*brw
,
312 gl_shader_stage stage
,
313 const uint32_t* binding_table
,
318 assert(stage
< ARRAY_SIZE(stage_to_bt_edit
));
319 assert(stage_to_bt_edit
[stage
]);
321 BEGIN_BATCH(num_surfaces
+ 2);
322 OUT_BATCH(stage_to_bt_edit
[stage
] << 16 | num_surfaces
);
323 OUT_BATCH(BRW_BINDING_TABLE_EDIT_TARGET_ALL
);
324 for (int i
= 0; i
< num_surfaces
; i
++) {
325 dw2
= SET_FIELD(i
, BRW_BINDING_TABLE_INDEX
) |
326 (brw
->gen
>= 8 ? GEN8_SURFACE_STATE_EDIT(binding_table
[i
]) :
327 HSW_SURFACE_STATE_EDIT(binding_table
[i
]));
334 * Disable hardware binding table support, falling back to the
335 * older software-generated binding table mechanism.
338 gen7_disable_hw_binding_tables(struct brw_context
*brw
)
340 if (!brw
->use_resource_streamer
)
342 /* From the Haswell PRM, Volume 7: 3D Media GPGPU,
343 * 3DSTATE_BINDING_TABLE_POOL_ALLOC > Programming Note:
345 * "When switching between HW and SW binding table generation, SW must
346 * issue a state cache invalidate."
348 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
350 int pkt_len
= brw
->gen
>= 8 ? 4 : 3;
352 BEGIN_BATCH(pkt_len
);
353 OUT_BATCH(_3DSTATE_BINDING_TABLE_POOL_ALLOC
<< 16 | (pkt_len
- 2));
359 OUT_BATCH(HSW_BT_POOL_ALLOC_MUST_BE_ONE
);
366 * Enable hardware binding tables and set up the binding table pool.
369 gen7_enable_hw_binding_tables(struct brw_context
*brw
)
371 if (!brw
->use_resource_streamer
)
374 if (!brw
->hw_bt_pool
.bo
) {
375 /* We use a single re-usable buffer object for the lifetime of the
376 * context and size it to maximum allowed binding tables that can be
377 * programmed per batch:
379 * From the Haswell PRM, Volume 7: 3D Media GPGPU,
380 * 3DSTATE_BINDING_TABLE_POOL_ALLOC > Programming Note:
381 * "A maximum of 16,383 Binding tables are allowed in any batch buffer"
383 static const int max_size
= 16383 * 4;
384 brw
->hw_bt_pool
.bo
= drm_intel_bo_alloc(brw
->bufmgr
, "hw_bt",
386 brw
->hw_bt_pool
.next_offset
= 0;
389 /* From the Haswell PRM, Volume 7: 3D Media GPGPU,
390 * 3DSTATE_BINDING_TABLE_POOL_ALLOC > Programming Note:
392 * "When switching between HW and SW binding table generation, SW must
393 * issue a state cache invalidate."
395 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
397 int pkt_len
= brw
->gen
>= 8 ? 4 : 3;
398 uint32_t dw1
= BRW_HW_BINDING_TABLE_ENABLE
;
399 if (brw
->is_haswell
) {
400 dw1
|= SET_FIELD(GEN7_MOCS_L3
, GEN7_HW_BT_POOL_MOCS
) |
401 HSW_BT_POOL_ALLOC_MUST_BE_ONE
;
402 } else if (brw
->gen
>= 8) {
406 BEGIN_BATCH(pkt_len
);
407 OUT_BATCH(_3DSTATE_BINDING_TABLE_POOL_ALLOC
<< 16 | (pkt_len
- 2));
409 OUT_RELOC64(brw
->hw_bt_pool
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, dw1
);
410 OUT_BATCH(brw
->hw_bt_pool
.bo
->size
);
412 OUT_RELOC(brw
->hw_bt_pool
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, dw1
);
413 OUT_RELOC(brw
->hw_bt_pool
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
414 brw
->hw_bt_pool
.bo
->size
);
420 gen7_reset_hw_bt_pool_offsets(struct brw_context
*brw
)
422 brw
->hw_bt_pool
.next_offset
= 0;
425 const struct brw_tracked_state gen7_hw_binding_tables
= {
428 .brw
= BRW_NEW_BATCH
,
430 .emit
= gen7_enable_hw_binding_tables
436 * State atoms which emit 3DSTATE packets to update the binding table pointers.
441 * (Gen4-5) Upload the binding table pointers for all shader stages.
443 * The binding table pointers are relative to the surface state base address,
444 * which points at the batchbuffer containing the streamed batch state.
447 gen4_upload_binding_table_pointers(struct brw_context
*brw
)
450 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 | (6 - 2));
451 OUT_BATCH(brw
->vs
.base
.bind_bo_offset
);
452 OUT_BATCH(0); /* gs */
453 OUT_BATCH(0); /* clip */
454 OUT_BATCH(0); /* sf */
455 OUT_BATCH(brw
->wm
.base
.bind_bo_offset
);
459 const struct brw_tracked_state brw_binding_table_pointers
= {
462 .brw
= BRW_NEW_BATCH
|
463 BRW_NEW_BINDING_TABLE_POINTERS
|
464 BRW_NEW_STATE_BASE_ADDRESS
,
466 .emit
= gen4_upload_binding_table_pointers
,
470 * (Sandybridge Only) Upload the binding table pointers for all shader stages.
472 * The binding table pointers are relative to the surface state base address,
473 * which points at the batchbuffer containing the streamed batch state.
476 gen6_upload_binding_table_pointers(struct brw_context
*brw
)
479 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 |
480 GEN6_BINDING_TABLE_MODIFY_VS
|
481 GEN6_BINDING_TABLE_MODIFY_GS
|
482 GEN6_BINDING_TABLE_MODIFY_PS
|
484 OUT_BATCH(brw
->vs
.base
.bind_bo_offset
); /* vs */
485 if (brw
->ff_gs
.prog_active
)
486 OUT_BATCH(brw
->ff_gs
.bind_bo_offset
); /* gs */
488 OUT_BATCH(brw
->gs
.base
.bind_bo_offset
); /* gs */
489 OUT_BATCH(brw
->wm
.base
.bind_bo_offset
); /* wm/ps */
493 const struct brw_tracked_state gen6_binding_table_pointers
= {
496 .brw
= BRW_NEW_BATCH
|
497 BRW_NEW_BINDING_TABLE_POINTERS
|
498 BRW_NEW_STATE_BASE_ADDRESS
,
500 .emit
= gen6_upload_binding_table_pointers
,