2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/blend.h"
27 #include "main/bufferobj.h"
28 #include "main/enums.h"
29 #include "main/fbobject.h"
30 #include "main/image.h"
31 #include "main/renderbuffer.h"
32 #include "main/glformats.h"
34 #include "brw_blorp.h"
35 #include "brw_context.h"
36 #include "brw_defines.h"
37 #include "brw_meta_util.h"
38 #include "brw_state.h"
39 #include "intel_buffer_objects.h"
40 #include "intel_fbo.h"
41 #include "dev/gen_debug.h"
43 #define FILE_DEBUG_FLAG DEBUG_BLORP
46 brw_blorp_lookup_shader(struct blorp_batch
*batch
,
47 const void *key
, uint32_t key_size
,
48 uint32_t *kernel_out
, void *prog_data_out
)
50 struct brw_context
*brw
= batch
->driver_batch
;
51 return brw_search_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
, key
, key_size
,
52 kernel_out
, prog_data_out
, true);
56 brw_blorp_upload_shader(struct blorp_batch
*batch
,
57 const void *key
, uint32_t key_size
,
58 const void *kernel
, uint32_t kernel_size
,
59 const struct brw_stage_prog_data
*prog_data
,
60 uint32_t prog_data_size
,
61 uint32_t *kernel_out
, void *prog_data_out
)
63 struct brw_context
*brw
= batch
->driver_batch
;
64 brw_upload_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
, key
, key_size
,
65 kernel
, kernel_size
, prog_data
, prog_data_size
,
66 kernel_out
, prog_data_out
);
71 brw_blorp_init(struct brw_context
*brw
)
73 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
75 blorp_init(&brw
->blorp
, brw
, &brw
->isl_dev
);
77 brw
->blorp
.compiler
= brw
->screen
->compiler
;
79 switch (devinfo
->gen
) {
81 if (devinfo
->is_g4x
) {
82 brw
->blorp
.exec
= gen45_blorp_exec
;
84 brw
->blorp
.exec
= gen4_blorp_exec
;
88 brw
->blorp
.exec
= gen5_blorp_exec
;
91 brw
->blorp
.exec
= gen6_blorp_exec
;
94 if (devinfo
->is_haswell
) {
95 brw
->blorp
.exec
= gen75_blorp_exec
;
97 brw
->blorp
.exec
= gen7_blorp_exec
;
101 brw
->blorp
.exec
= gen8_blorp_exec
;
104 brw
->blorp
.exec
= gen9_blorp_exec
;
107 brw
->blorp
.exec
= gen10_blorp_exec
;
110 brw
->blorp
.exec
= gen11_blorp_exec
;
114 unreachable("Invalid gen");
117 brw
->blorp
.lookup_shader
= brw_blorp_lookup_shader
;
118 brw
->blorp
.upload_shader
= brw_blorp_upload_shader
;
122 blorp_surf_for_miptree(struct brw_context
*brw
,
123 struct blorp_surf
*surf
,
124 const struct intel_mipmap_tree
*mt
,
125 enum isl_aux_usage aux_usage
,
126 bool is_render_target
,
128 unsigned start_layer
, unsigned num_layers
)
130 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
132 if (mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
) {
133 const unsigned num_samples
= mt
->surf
.samples
;
134 for (unsigned i
= 0; i
< num_layers
; i
++) {
135 for (unsigned s
= 0; s
< num_samples
; s
++) {
136 const unsigned phys_layer
= (start_layer
+ i
) * num_samples
+ s
;
137 intel_miptree_check_level_layer(mt
, *level
, phys_layer
);
141 for (unsigned i
= 0; i
< num_layers
; i
++)
142 intel_miptree_check_level_layer(mt
, *level
, start_layer
+ i
);
145 *surf
= (struct blorp_surf
) {
147 .addr
= (struct blorp_address
) {
149 .offset
= mt
->offset
,
150 .reloc_flags
= is_render_target
? EXEC_OBJECT_WRITE
: 0,
151 .mocs
= brw_get_bo_mocs(devinfo
, mt
->bo
),
153 .aux_usage
= aux_usage
,
154 .tile_x_sa
= mt
->level
[*level
].level_x
,
155 .tile_y_sa
= mt
->level
[*level
].level_y
,
158 if (surf
->aux_usage
== ISL_AUX_USAGE_HIZ
&&
159 !intel_miptree_level_has_hiz(mt
, *level
))
160 surf
->aux_usage
= ISL_AUX_USAGE_NONE
;
162 if (surf
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
163 /* We only really need a clear color if we also have an auxiliary
164 * surface. Without one, it does nothing.
167 intel_miptree_get_clear_color(devinfo
, mt
, mt
->surf
.format
,
168 !is_render_target
, (struct brw_bo
**)
169 &surf
->clear_color_addr
.buffer
,
170 &surf
->clear_color_addr
.offset
);
172 surf
->aux_surf
= &mt
->aux_buf
->surf
;
173 surf
->aux_addr
= (struct blorp_address
) {
174 .reloc_flags
= is_render_target
? EXEC_OBJECT_WRITE
: 0,
175 .mocs
= surf
->addr
.mocs
,
178 surf
->aux_addr
.buffer
= mt
->aux_buf
->bo
;
179 surf
->aux_addr
.offset
= mt
->aux_buf
->offset
;
181 surf
->aux_addr
= (struct blorp_address
) {
184 memset(&surf
->clear_color
, 0, sizeof(surf
->clear_color
));
186 assert((surf
->aux_usage
== ISL_AUX_USAGE_NONE
) ==
187 (surf
->aux_addr
.buffer
== NULL
));
189 if (!is_render_target
&& brw
->screen
->devinfo
.gen
== 9)
190 gen9_apply_single_tex_astc5x5_wa(brw
, mt
->format
, surf
->aux_usage
);
192 /* ISL wants real levels, not offset ones. */
193 *level
-= mt
->first_level
;
197 brw_blorp_supports_dst_format(struct brw_context
*brw
, mesa_format format
)
199 /* If it's renderable, it's definitely supported. */
200 if (brw
->mesa_format_supports_render
[format
])
203 /* BLORP can't compress anything */
204 if (_mesa_is_format_compressed(format
))
207 /* No exotic formats such as GL_LUMINANCE_ALPHA */
208 if (_mesa_get_format_bits(format
, GL_RED_BITS
) == 0 &&
209 _mesa_get_format_bits(format
, GL_DEPTH_BITS
) == 0 &&
210 _mesa_get_format_bits(format
, GL_STENCIL_BITS
) == 0)
216 static enum isl_format
217 brw_blorp_to_isl_format(struct brw_context
*brw
, mesa_format format
,
218 bool is_render_target
)
221 case MESA_FORMAT_NONE
:
222 return ISL_FORMAT_UNSUPPORTED
;
223 case MESA_FORMAT_S_UINT8
:
224 return ISL_FORMAT_R8_UINT
;
225 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
226 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
227 return ISL_FORMAT_R24_UNORM_X8_TYPELESS
;
228 case MESA_FORMAT_Z_FLOAT32
:
229 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
230 return ISL_FORMAT_R32_FLOAT
;
231 case MESA_FORMAT_Z_UNORM16
:
232 return ISL_FORMAT_R16_UNORM
;
234 if (is_render_target
) {
235 assert(brw_blorp_supports_dst_format(brw
, format
));
236 if (brw
->mesa_format_supports_render
[format
]) {
237 return brw
->mesa_to_isl_render_format
[format
];
239 return brw_isl_format_for_mesa_format(format
);
242 /* Some destinations (is_render_target == true) are supported by
243 * blorp even though we technically can't render to them.
245 return brw_isl_format_for_mesa_format(format
);
251 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
252 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
254 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
257 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
259 * which is simply adding 4 then modding by 8 (or anding with 7).
261 * We then may need to apply workarounds for textureGather hardware bugs.
263 static enum isl_channel_select
264 swizzle_to_scs(GLenum swizzle
)
266 return (enum isl_channel_select
)((swizzle
+ 4) & 7);
270 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
271 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
272 * the physical layer holding sample 0. So, for example, if
273 * src_mt->surf.samples == 4, then logical layer n corresponds to src_layer ==
277 brw_blorp_blit_miptrees(struct brw_context
*brw
,
278 struct intel_mipmap_tree
*src_mt
,
279 unsigned src_level
, unsigned src_layer
,
280 mesa_format src_format
, int src_swizzle
,
281 struct intel_mipmap_tree
*dst_mt
,
282 unsigned dst_level
, unsigned dst_layer
,
283 mesa_format dst_format
,
284 float src_x0
, float src_y0
,
285 float src_x1
, float src_y1
,
286 float dst_x0
, float dst_y0
,
287 float dst_x1
, float dst_y1
,
288 GLenum gl_filter
, bool mirror_x
, bool mirror_y
,
289 bool decode_srgb
, bool encode_srgb
)
291 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
293 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f) "
294 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
296 src_mt
->surf
.samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
297 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
298 dst_mt
->surf
.samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
299 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
303 src_format
= _mesa_get_srgb_format_linear(src_format
);
306 dst_format
= _mesa_get_srgb_format_linear(dst_format
);
308 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
309 * texture, the above code configures the source format for L32_FLOAT or
310 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
311 * the SAMPLE message appears to handle multisampled L32_FLOAT and
312 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
313 * around the problem by using a source format of R32_FLOAT. This
314 * shouldn't affect rendering correctness, since the destination format is
315 * R32_FLOAT, so only the contents of the red channel matters.
317 if (devinfo
->gen
== 6 &&
318 src_mt
->surf
.samples
> 1 && dst_mt
->surf
.samples
<= 1 &&
319 src_mt
->format
== dst_mt
->format
&&
320 (dst_format
== MESA_FORMAT_L_FLOAT32
||
321 dst_format
== MESA_FORMAT_I_FLOAT32
)) {
322 src_format
= dst_format
= MESA_FORMAT_R_FLOAT32
;
325 enum blorp_filter blorp_filter
;
326 if (fabsf(dst_x1
- dst_x0
) == fabsf(src_x1
- src_x0
) &&
327 fabsf(dst_y1
- dst_y0
) == fabsf(src_y1
- src_y0
)) {
328 if (src_mt
->surf
.samples
> 1 && dst_mt
->surf
.samples
<= 1) {
329 /* From the OpenGL ES 3.2 specification, section 16.2.1:
331 * "If the read framebuffer is multisampled (its effective value
332 * of SAMPLE_BUFFERS is one) and the draw framebuffer is not (its
333 * value of SAMPLE_BUFFERS is zero), the samples corresponding to
334 * each pixel location in the source are converted to a single
335 * sample before being written to the destination. The filter
336 * parameter is ignored. If the source formats are integer types
337 * or stencil values, a single sample’s value is selected for each
338 * pixel. If the source formats are floating-point or normalized
339 * types, the sample values for each pixel are resolved in an
340 * implementation-dependent manner. If the source formats are
341 * depth values, sample values are resolved in an implementation-
342 * dependent manner where the result will be between the minimum
343 * and maximum depth values in the pixel."
345 * For depth and stencil resolves, we choose to always use the value
348 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
349 if (base_format
== GL_DEPTH_COMPONENT
||
350 base_format
== GL_STENCIL_INDEX
||
351 base_format
== GL_DEPTH_STENCIL
||
352 _mesa_is_format_integer(src_mt
->format
)) {
353 /* The OpenGL ES 3.2 spec says:
355 * "If the source formats are integer types or stencil values,
356 * a single sample's value is selected for each pixel."
358 * Just take sample 0 in this case.
360 blorp_filter
= BLORP_FILTER_SAMPLE_0
;
362 blorp_filter
= BLORP_FILTER_AVERAGE
;
365 /* From the OpenGL 4.6 specification, section 18.3.1:
367 * "If the source and destination dimensions are identical, no
368 * filtering is applied."
370 * Using BLORP_FILTER_NONE will also handle the upsample case by
371 * replicating the one value in the source to all values in the
374 blorp_filter
= BLORP_FILTER_NONE
;
376 } else if (gl_filter
== GL_LINEAR
||
377 gl_filter
== GL_SCALED_RESOLVE_FASTEST_EXT
||
378 gl_filter
== GL_SCALED_RESOLVE_NICEST_EXT
) {
379 blorp_filter
= BLORP_FILTER_BILINEAR
;
381 blorp_filter
= BLORP_FILTER_NEAREST
;
384 enum isl_format src_isl_format
=
385 brw_blorp_to_isl_format(brw
, src_format
, false);
386 enum isl_aux_usage src_aux_usage
=
387 intel_miptree_texture_aux_usage(brw
, src_mt
, src_isl_format
,
388 0 /* The astc5x5 WA isn't needed */);
389 /* We do format workarounds for some depth formats so we can't reliably
390 * sample with HiZ. One of these days, we should fix that.
392 if (src_aux_usage
== ISL_AUX_USAGE_HIZ
)
393 src_aux_usage
= ISL_AUX_USAGE_NONE
;
394 const bool src_clear_supported
=
395 src_aux_usage
!= ISL_AUX_USAGE_NONE
&& src_mt
->format
== src_format
;
396 intel_miptree_prepare_access(brw
, src_mt
, src_level
, 1, src_layer
, 1,
397 src_aux_usage
, src_clear_supported
);
399 enum isl_format dst_isl_format
=
400 brw_blorp_to_isl_format(brw
, dst_format
, true);
401 enum isl_aux_usage dst_aux_usage
=
402 intel_miptree_render_aux_usage(brw
, dst_mt
, dst_isl_format
,
404 const bool dst_clear_supported
= dst_aux_usage
!= ISL_AUX_USAGE_NONE
;
405 intel_miptree_prepare_access(brw
, dst_mt
, dst_level
, 1, dst_layer
, 1,
406 dst_aux_usage
, dst_clear_supported
);
408 struct blorp_surf src_surf
, dst_surf
;
409 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, src_aux_usage
, false,
410 &src_level
, src_layer
, 1);
411 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, dst_aux_usage
, true,
412 &dst_level
, dst_layer
, 1);
414 struct isl_swizzle src_isl_swizzle
= {
415 .r
= swizzle_to_scs(GET_SWZ(src_swizzle
, 0)),
416 .g
= swizzle_to_scs(GET_SWZ(src_swizzle
, 1)),
417 .b
= swizzle_to_scs(GET_SWZ(src_swizzle
, 2)),
418 .a
= swizzle_to_scs(GET_SWZ(src_swizzle
, 3)),
421 struct blorp_batch batch
;
422 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
423 blorp_blit(&batch
, &src_surf
, src_level
, src_layer
,
424 src_isl_format
, src_isl_swizzle
,
425 &dst_surf
, dst_level
, dst_layer
,
426 dst_isl_format
, ISL_SWIZZLE_IDENTITY
,
427 src_x0
, src_y0
, src_x1
, src_y1
,
428 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
429 blorp_filter
, mirror_x
, mirror_y
);
430 blorp_batch_finish(&batch
);
432 intel_miptree_finish_write(brw
, dst_mt
, dst_level
, dst_layer
, 1,
437 brw_blorp_copy_miptrees(struct brw_context
*brw
,
438 struct intel_mipmap_tree
*src_mt
,
439 unsigned src_level
, unsigned src_layer
,
440 struct intel_mipmap_tree
*dst_mt
,
441 unsigned dst_level
, unsigned dst_layer
,
442 unsigned src_x
, unsigned src_y
,
443 unsigned dst_x
, unsigned dst_y
,
444 unsigned src_width
, unsigned src_height
)
446 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
448 DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
449 "to %dx %s mt %p %d %d (%d,%d)\n",
451 src_mt
->surf
.samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
452 src_level
, src_layer
, src_x
, src_y
, src_width
, src_height
,
453 dst_mt
->surf
.samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
454 dst_level
, dst_layer
, dst_x
, dst_y
);
456 enum isl_aux_usage src_aux_usage
, dst_aux_usage
;
457 bool src_clear_supported
, dst_clear_supported
;
459 switch (src_mt
->aux_usage
) {
460 case ISL_AUX_USAGE_MCS
:
461 case ISL_AUX_USAGE_CCS_E
:
462 src_aux_usage
= src_mt
->aux_usage
;
463 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
464 * we're going to re-interpret the format as an integer format possibly
465 * with a different number of components, we can't handle clear colors
468 src_clear_supported
= devinfo
->gen
>= 9;
471 src_aux_usage
= ISL_AUX_USAGE_NONE
;
472 src_clear_supported
= false;
476 switch (dst_mt
->aux_usage
) {
477 case ISL_AUX_USAGE_MCS
:
478 case ISL_AUX_USAGE_CCS_E
:
479 dst_aux_usage
= dst_mt
->aux_usage
;
480 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
481 * we're going to re-interpret the format as an integer format possibly
482 * with a different number of components, we can't handle clear colors
485 dst_clear_supported
= devinfo
->gen
>= 9;
488 dst_aux_usage
= ISL_AUX_USAGE_NONE
;
489 dst_clear_supported
= false;
493 intel_miptree_prepare_access(brw
, src_mt
, src_level
, 1, src_layer
, 1,
494 src_aux_usage
, src_clear_supported
);
495 intel_miptree_prepare_access(brw
, dst_mt
, dst_level
, 1, dst_layer
, 1,
496 dst_aux_usage
, dst_clear_supported
);
498 struct blorp_surf src_surf
, dst_surf
;
499 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, src_aux_usage
, false,
500 &src_level
, src_layer
, 1);
501 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, dst_aux_usage
, true,
502 &dst_level
, dst_layer
, 1);
504 /* The hardware seems to have issues with having a two different format
505 * views of the same texture in the sampler cache at the same time. It's
506 * unclear exactly what the issue is but it hurts glCopyImageSubData
507 * particularly badly because it does a lot of format reinterprets. We
508 * badly need better understanding of the issue and a better fix but this
509 * works for now and fixes CTS tests.
511 * TODO: Remove this hack!
513 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
|
514 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
516 struct blorp_batch batch
;
517 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
518 blorp_copy(&batch
, &src_surf
, src_level
, src_layer
,
519 &dst_surf
, dst_level
, dst_layer
,
520 src_x
, src_y
, dst_x
, dst_y
, src_width
, src_height
);
521 blorp_batch_finish(&batch
);
523 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
|
524 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
526 intel_miptree_finish_write(brw
, dst_mt
, dst_level
, dst_layer
, 1,
531 brw_blorp_copy_buffers(struct brw_context
*brw
,
532 struct brw_bo
*src_bo
,
534 struct brw_bo
*dst_bo
,
538 DBG("%s %d bytes from %p[%d] to %p[%d]",
539 __func__
, size
, src_bo
, src_offset
, dst_bo
, dst_offset
);
541 struct blorp_batch batch
;
542 struct blorp_address src
= { .buffer
= src_bo
, .offset
= src_offset
};
543 struct blorp_address dst
= { .buffer
= dst_bo
, .offset
= dst_offset
};
545 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
546 blorp_buffer_copy(&batch
, src
, dst
, size
);
547 blorp_batch_finish(&batch
);
551 static struct intel_mipmap_tree
*
552 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
554 struct intel_mipmap_tree
*mt
= irb
->mt
;
555 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
561 blorp_get_texture_swizzle(const struct intel_renderbuffer
*irb
)
563 return irb
->Base
.Base
._BaseFormat
== GL_RGB
?
564 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ONE
) :
569 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
570 struct intel_renderbuffer
*src_irb
, mesa_format src_format
,
571 struct intel_renderbuffer
*dst_irb
, mesa_format dst_format
,
572 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
573 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
574 GLenum filter
, bool mirror_x
, bool mirror_y
)
576 const struct gl_context
*ctx
= &brw
->ctx
;
578 /* Find source/dst miptrees */
579 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
580 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
582 const bool do_srgb
= ctx
->Color
.sRGBEnabled
;
585 brw_blorp_blit_miptrees(brw
,
586 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
587 src_format
, blorp_get_texture_swizzle(src_irb
),
588 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
590 srcX0
, srcY0
, srcX1
, srcY1
,
591 dstX0
, dstY0
, dstX1
, dstY1
,
592 filter
, mirror_x
, mirror_y
,
595 dst_irb
->need_downsample
= true;
599 try_blorp_blit(struct brw_context
*brw
,
600 const struct gl_framebuffer
*read_fb
,
601 const struct gl_framebuffer
*draw_fb
,
602 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
603 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
604 GLenum filter
, GLbitfield buffer_bit
)
606 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
607 struct gl_context
*ctx
= &brw
->ctx
;
609 /* Sync up the state of window system buffers. We need to do this before
610 * we go looking for the buffers.
612 intel_prepare_render(brw
);
614 bool mirror_x
, mirror_y
;
615 if (brw_meta_mirror_clip_and_scissor(ctx
, read_fb
, draw_fb
,
616 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
617 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
618 &mirror_x
, &mirror_y
))
622 struct intel_renderbuffer
*src_irb
;
623 struct intel_renderbuffer
*dst_irb
;
624 struct intel_mipmap_tree
*src_mt
;
625 struct intel_mipmap_tree
*dst_mt
;
626 switch (buffer_bit
) {
627 case GL_COLOR_BUFFER_BIT
:
628 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
629 for (unsigned i
= 0; i
< draw_fb
->_NumColorDrawBuffers
; ++i
) {
630 dst_irb
= intel_renderbuffer(draw_fb
->_ColorDrawBuffers
[i
]);
632 do_blorp_blit(brw
, buffer_bit
,
633 src_irb
, src_irb
->Base
.Base
.Format
,
634 dst_irb
, dst_irb
->Base
.Base
.Format
,
635 srcX0
, srcY0
, srcX1
, srcY1
,
636 dstX0
, dstY0
, dstX1
, dstY1
,
637 filter
, mirror_x
, mirror_y
);
640 case GL_DEPTH_BUFFER_BIT
:
642 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
644 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
645 src_mt
= find_miptree(buffer_bit
, src_irb
);
646 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
648 /* We also can't handle any combined depth-stencil formats because we
649 * have to reinterpret as a color format.
651 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
652 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
655 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
656 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
657 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
658 filter
, mirror_x
, mirror_y
);
660 case GL_STENCIL_BUFFER_BIT
:
661 /* Blorp doesn't support combined depth stencil which is all we have
664 if (devinfo
->gen
< 6)
668 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
670 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
671 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
672 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
673 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
674 filter
, mirror_x
, mirror_y
);
677 unreachable("not reached");
684 apply_y_flip(int *y0
, int *y1
, int height
)
686 int tmp
= height
- *y0
;
692 brw_blorp_copytexsubimage(struct brw_context
*brw
,
693 struct gl_renderbuffer
*src_rb
,
694 struct gl_texture_image
*dst_image
,
696 int srcX0
, int srcY0
,
697 int dstX0
, int dstY0
,
698 int width
, int height
)
700 struct gl_context
*ctx
= &brw
->ctx
;
701 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
702 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
704 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
705 if (brw
->ctx
._ImageTransferState
)
708 /* Sync up the state of window system buffers. We need to do this before
709 * we go looking at the src renderbuffer's miptree.
711 intel_prepare_render(brw
);
713 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
714 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
716 /* We can't handle any combined depth-stencil formats because we have to
717 * reinterpret as a color format.
719 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
720 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
723 if (!brw_blorp_supports_dst_format(brw
, dst_image
->TexFormat
))
726 /* Source clipping shouldn't be necessary, since copytexsubimage (in
727 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
730 * Destination clipping shouldn't be necessary since the restrictions on
731 * glCopyTexSubImage prevent the user from specifying a destination rectangle
732 * that falls outside the bounds of the destination texture.
733 * See error_check_subtexture_dimensions().
736 int srcY1
= srcY0
+ height
;
737 int srcX1
= srcX0
+ width
;
738 int dstX1
= dstX0
+ width
;
739 int dstY1
= dstY0
+ height
;
741 /* Account for the fact that in the system framebuffer, the origin is at
744 bool mirror_y
= ctx
->ReadBuffer
->FlipY
;
746 apply_y_flip(&srcY0
, &srcY1
, src_rb
->Height
);
748 /* Account for face selection and texture view MinLayer */
749 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
750 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
752 brw_blorp_blit_miptrees(brw
,
753 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
754 src_rb
->Format
, blorp_get_texture_swizzle(src_irb
),
755 dst_mt
, dst_level
, dst_slice
,
756 dst_image
->TexFormat
,
757 srcX0
, srcY0
, srcX1
, srcY1
,
758 dstX0
, dstY0
, dstX1
, dstY1
,
759 GL_NEAREST
, false, mirror_y
,
762 /* If we're copying to a packed depth stencil texture and the source
763 * framebuffer has separate stencil, we need to also copy the stencil data
766 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
767 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
769 src_irb
= intel_renderbuffer(src_rb
);
770 src_mt
= src_irb
->mt
;
772 if (src_mt
->stencil_mt
)
773 src_mt
= src_mt
->stencil_mt
;
774 if (dst_mt
->stencil_mt
)
775 dst_mt
= dst_mt
->stencil_mt
;
777 if (src_mt
!= dst_mt
) {
778 brw_blorp_blit_miptrees(brw
,
779 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
781 blorp_get_texture_swizzle(src_irb
),
782 dst_mt
, dst_level
, dst_slice
,
784 srcX0
, srcY0
, srcX1
, srcY1
,
785 dstX0
, dstY0
, dstX1
, dstY1
,
786 GL_NEAREST
, false, mirror_y
,
796 brw_blorp_framebuffer(struct brw_context
*brw
,
797 struct gl_framebuffer
*readFb
,
798 struct gl_framebuffer
*drawFb
,
799 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
800 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
801 GLbitfield mask
, GLenum filter
)
803 static GLbitfield buffer_bits
[] = {
806 GL_STENCIL_BUFFER_BIT
,
809 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
810 if ((mask
& buffer_bits
[i
]) &&
811 try_blorp_blit(brw
, readFb
, drawFb
,
812 srcX0
, srcY0
, srcX1
, srcY1
,
813 dstX0
, dstY0
, dstX1
, dstY1
,
814 filter
, buffer_bits
[i
])) {
815 mask
&= ~buffer_bits
[i
];
822 static struct brw_bo
*
823 blorp_get_client_bo(struct brw_context
*brw
,
824 unsigned w
, unsigned h
, unsigned d
,
825 GLenum target
, GLenum format
, GLenum type
,
827 const struct gl_pixelstore_attrib
*packing
,
828 uint32_t *offset_out
, uint32_t *row_stride_out
,
829 uint32_t *image_stride_out
, bool read_only
)
831 /* Account for SKIP_PIXELS, SKIP_ROWS, ALIGNMENT, and SKIP_IMAGES */
832 const GLuint dims
= _mesa_get_texture_dimensions(target
);
833 const uint32_t first_pixel
= _mesa_image_offset(dims
, packing
, w
, h
,
834 format
, type
, 0, 0, 0);
835 const uint32_t last_pixel
= _mesa_image_offset(dims
, packing
, w
, h
,
838 const uint32_t stride
= _mesa_image_row_stride(packing
, w
, format
, type
);
839 const uint32_t cpp
= _mesa_bytes_per_pixel(format
, type
);
840 const uint32_t size
= last_pixel
- first_pixel
;
842 *row_stride_out
= stride
;
843 *image_stride_out
= _mesa_image_image_stride(packing
, w
, h
, format
, type
);
845 if (_mesa_is_bufferobj(packing
->BufferObj
)) {
846 const uint32_t offset
= first_pixel
+ (intptr_t)pixels
;
847 if (!read_only
&& ((offset
% cpp
) || (stride
% cpp
))) {
848 perf_debug("Bad PBO alignment; fallback to CPU mapping\n");
852 /* This is a user-provided PBO. We just need to get the BO out */
853 struct intel_buffer_object
*intel_pbo
=
854 intel_buffer_object(packing
->BufferObj
);
856 intel_bufferobj_buffer(brw
, intel_pbo
, offset
, size
, !read_only
);
858 /* We take a reference to the BO so that the caller can just always
859 * unref without having to worry about whether it's a user PBO or one
862 brw_bo_reference(bo
);
864 *offset_out
= offset
;
867 /* Someone should have already checked that there is data to upload. */
870 /* Creating a temp buffer currently only works for upload */
873 /* This is not a user-provided PBO. Instead, pixels is a pointer to CPU
874 * data which we need to copy into a BO.
877 brw_bo_alloc(brw
->bufmgr
, "tmp_tex_subimage_src", size
,
880 perf_debug("intel_texsubimage: temp bo creation failed: size = %u\n",
885 if (brw_bo_subdata(bo
, 0, size
, pixels
+ first_pixel
)) {
886 perf_debug("intel_texsubimage: temp bo upload failed\n");
887 brw_bo_unreference(bo
);
896 /* Consider all the restrictions and determine the format of the source. */
898 blorp_get_client_format(struct brw_context
*brw
,
899 GLenum format
, GLenum type
,
900 const struct gl_pixelstore_attrib
*packing
)
902 if (brw
->ctx
._ImageTransferState
)
903 return MESA_FORMAT_NONE
;
905 if (packing
->SwapBytes
|| packing
->LsbFirst
|| packing
->Invert
) {
906 perf_debug("intel_texsubimage_blorp: unsupported gl_pixelstore_attrib\n");
907 return MESA_FORMAT_NONE
;
910 if (format
!= GL_RED
&&
916 format
!= GL_ALPHA
&&
917 format
!= GL_RED_INTEGER
&&
918 format
!= GL_RG_INTEGER
&&
919 format
!= GL_RGB_INTEGER
&&
920 format
!= GL_BGR_INTEGER
&&
921 format
!= GL_RGBA_INTEGER
&&
922 format
!= GL_BGRA_INTEGER
) {
923 perf_debug("intel_texsubimage_blorp: %s not supported",
924 _mesa_enum_to_string(format
));
925 return MESA_FORMAT_NONE
;
928 return _mesa_tex_format_from_format_and_type(&brw
->ctx
, format
, type
);
932 brw_blorp_upload_miptree(struct brw_context
*brw
,
933 struct intel_mipmap_tree
*dst_mt
,
934 mesa_format dst_format
,
935 uint32_t level
, uint32_t x
, uint32_t y
, uint32_t z
,
936 uint32_t width
, uint32_t height
, uint32_t depth
,
937 GLenum target
, GLenum format
, GLenum type
,
939 const struct gl_pixelstore_attrib
*packing
)
941 const mesa_format src_format
=
942 blorp_get_client_format(brw
, format
, type
, packing
);
943 if (src_format
== MESA_FORMAT_NONE
)
946 if (!brw
->mesa_format_supports_render
[dst_format
]) {
947 perf_debug("intel_texsubimage: can't use %s as render target\n",
948 _mesa_get_format_name(dst_format
));
952 uint32_t src_offset
, src_row_stride
, src_image_stride
;
953 struct brw_bo
*src_bo
=
954 blorp_get_client_bo(brw
, width
, height
, depth
,
955 target
, format
, type
, pixels
, packing
,
956 &src_offset
, &src_row_stride
,
957 &src_image_stride
, true);
961 /* Now that source is offset to correct starting point, adjust the
962 * given dimensions to treat 1D arrays as 2D.
964 if (target
== GL_TEXTURE_1D_ARRAY
) {
971 src_image_stride
= src_row_stride
;
974 intel_miptree_check_level_layer(dst_mt
, level
, z
+ depth
- 1);
978 /* Blit slice-by-slice creating a single-slice miptree for each layer. Even
979 * in case of linear buffers hardware wants image arrays to be aligned by
980 * four rows. This way hardware only gets one image at a time and any
981 * source alignment will do.
983 for (unsigned i
= 0; i
< depth
; ++i
) {
984 struct intel_mipmap_tree
*src_mt
= intel_miptree_create_for_bo(
985 brw
, src_bo
, src_format
,
986 src_offset
+ i
* src_image_stride
,
989 ISL_TILING_LINEAR
, 0);
992 perf_debug("intel_texsubimage: miptree creation for src failed\n");
996 /* In case exact match is needed, copy using equivalent UINT formats
997 * preventing hardware from changing presentation for SNORM -1.
999 if (src_mt
->format
== dst_format
) {
1000 brw_blorp_copy_miptrees(brw
, src_mt
, 0, 0,
1001 dst_mt
, level
, z
+ i
,
1002 0, 0, x
, y
, width
, height
);
1004 brw_blorp_blit_miptrees(brw
, src_mt
, 0, 0,
1005 src_format
, SWIZZLE_XYZW
,
1006 dst_mt
, level
, z
+ i
,
1008 0, 0, width
, height
,
1009 x
, y
, x
+ width
, y
+ height
,
1010 GL_NEAREST
, false, false, false, false);
1013 intel_miptree_release(&src_mt
);
1019 brw_bo_unreference(src_bo
);
1025 brw_blorp_download_miptree(struct brw_context
*brw
,
1026 struct intel_mipmap_tree
*src_mt
,
1027 mesa_format src_format
, uint32_t src_swizzle
,
1028 uint32_t level
, uint32_t x
, uint32_t y
, uint32_t z
,
1029 uint32_t width
, uint32_t height
, uint32_t depth
,
1030 GLenum target
, GLenum format
, GLenum type
,
1031 bool y_flip
, const void *pixels
,
1032 const struct gl_pixelstore_attrib
*packing
)
1034 const mesa_format dst_format
=
1035 blorp_get_client_format(brw
, format
, type
, packing
);
1036 if (dst_format
== MESA_FORMAT_NONE
)
1039 if (!brw
->mesa_format_supports_render
[dst_format
]) {
1040 perf_debug("intel_texsubimage: can't use %s as render target\n",
1041 _mesa_get_format_name(dst_format
));
1045 /* We can't fetch from LUMINANCE or intensity as that would require a
1046 * non-trivial swizzle.
1048 switch (_mesa_get_format_base_format(src_format
)) {
1050 case GL_LUMINANCE_ALPHA
:
1057 /* This pass only works for PBOs */
1058 assert(_mesa_is_bufferobj(packing
->BufferObj
));
1060 uint32_t dst_offset
, dst_row_stride
, dst_image_stride
;
1061 struct brw_bo
*dst_bo
=
1062 blorp_get_client_bo(brw
, width
, height
, depth
,
1063 target
, format
, type
, pixels
, packing
,
1064 &dst_offset
, &dst_row_stride
,
1065 &dst_image_stride
, false);
1069 /* Now that source is offset to correct starting point, adjust the
1070 * given dimensions to treat 1D arrays as 2D.
1072 if (target
== GL_TEXTURE_1D_ARRAY
) {
1079 dst_image_stride
= dst_row_stride
;
1082 intel_miptree_check_level_layer(src_mt
, level
, z
+ depth
- 1);
1085 int y1
= y
+ height
;
1087 apply_y_flip(&y0
, &y1
, minify(src_mt
->surf
.phys_level0_sa
.height
,
1088 level
- src_mt
->first_level
));
1091 bool result
= false;
1093 /* Blit slice-by-slice creating a single-slice miptree for each layer. Even
1094 * in case of linear buffers hardware wants image arrays to be aligned by
1095 * four rows. This way hardware only gets one image at a time and any
1096 * source alignment will do.
1098 for (unsigned i
= 0; i
< depth
; ++i
) {
1099 struct intel_mipmap_tree
*dst_mt
= intel_miptree_create_for_bo(
1100 brw
, dst_bo
, dst_format
,
1101 dst_offset
+ i
* dst_image_stride
,
1104 ISL_TILING_LINEAR
, 0);
1107 perf_debug("intel_texsubimage: miptree creation for src failed\n");
1111 /* In case exact match is needed, copy using equivalent UINT formats
1112 * preventing hardware from changing presentation for SNORM -1.
1114 if (dst_mt
->format
== src_format
&& !y_flip
&&
1115 src_swizzle
== SWIZZLE_XYZW
) {
1116 brw_blorp_copy_miptrees(brw
, src_mt
, level
, z
+ i
,
1118 x
, y
, 0, 0, width
, height
);
1120 brw_blorp_blit_miptrees(brw
, src_mt
, level
, z
+ i
,
1121 src_format
, src_swizzle
,
1122 dst_mt
, 0, 0, dst_format
,
1123 x
, y0
, x
+ width
, y1
,
1124 0, 0, width
, height
,
1125 GL_NEAREST
, false, y_flip
, false, false);
1128 intel_miptree_release(&dst_mt
);
1133 /* As we implement PBO transfers by binding the user-provided BO as a
1134 * fake framebuffer and rendering to it. This breaks the invariant of the
1135 * GL that nothing is able to render to a BO, causing nondeterministic
1136 * corruption issues because the render cache is not coherent with a
1137 * number of other caches that the BO could potentially be bound to
1140 * This could be solved in the same way that we guarantee texture
1141 * coherency after a texture is attached to a framebuffer and
1142 * rendered to, but that would involve checking *all* BOs bound to
1143 * the pipeline for the case we need to emit a cache flush due to
1144 * previous rendering to any of them -- Including vertex, index,
1145 * uniform, atomic counter, shader image, transform feedback,
1146 * indirect draw buffers, etc.
1148 * That would increase the per-draw call overhead even though it's
1149 * very unlikely that any of the BOs bound to the pipeline has been
1150 * rendered to via a PBO at any point, so it seems better to just
1151 * flush here unconditionally.
1153 brw_emit_mi_flush(brw
);
1156 brw_bo_unreference(dst_bo
);
1162 set_write_disables(const struct intel_renderbuffer
*irb
,
1163 const unsigned color_mask
, bool *color_write_disable
)
1165 /* Format information in the renderbuffer represents the requirements
1166 * given by the client. There are cases where the backing miptree uses,
1167 * for example, RGBA to represent RGBX. Since the client is only expecting
1168 * RGB we can treat alpha as not used and write whatever we like into it.
1170 const GLenum base_format
= irb
->Base
.Base
._BaseFormat
;
1171 const int components
= _mesa_components_in_format(base_format
);
1172 bool disables
= false;
1174 assert(components
> 0);
1176 for (int i
= 0; i
< components
; i
++) {
1177 color_write_disable
[i
] = !(color_mask
& (1 << i
));
1178 disables
= disables
|| color_write_disable
[i
];
1185 do_single_blorp_clear(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
1186 struct gl_renderbuffer
*rb
, unsigned buf
,
1187 bool partial_clear
, bool encode_srgb
)
1189 struct gl_context
*ctx
= &brw
->ctx
;
1190 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
1191 uint32_t x0
, x1
, y0
, y1
;
1193 mesa_format format
= irb
->Base
.Base
.Format
;
1195 format
= _mesa_get_srgb_format_linear(format
);
1196 enum isl_format isl_format
= brw
->mesa_to_isl_render_format
[format
];
1201 y0
= rb
->Height
- fb
->_Ymax
;
1202 y1
= rb
->Height
- fb
->_Ymin
;
1208 /* If the clear region is empty, just return. */
1209 if (x0
== x1
|| y0
== y1
)
1212 bool can_fast_clear
= !partial_clear
;
1214 bool color_write_disable
[4] = { false, false, false, false };
1215 if (set_write_disables(irb
, GET_COLORMASK(ctx
->Color
.ColorMask
, buf
),
1216 color_write_disable
))
1217 can_fast_clear
= false;
1219 /* We store clear colors as floats or uints as needed. If there are
1220 * texture views in play, the formats will not properly be respected
1221 * during resolves because the resolve operations only know about the
1222 * miptree and not the renderbuffer.
1224 if (irb
->Base
.Base
.Format
!= irb
->mt
->format
)
1225 can_fast_clear
= false;
1227 if (!irb
->mt
->supports_fast_clear
||
1228 !brw_is_color_fast_clear_compatible(brw
, irb
->mt
, &ctx
->Color
.ClearColor
))
1229 can_fast_clear
= false;
1231 /* Surface state can only record one fast clear color value. Therefore
1232 * unless different levels/layers agree on the color it can be used to
1233 * represent only single level/layer. Here it will be reserved for the
1234 * first slice (level 0, layer 0).
1236 if (irb
->layer_count
> 1 || irb
->mt_level
|| irb
->mt_layer
)
1237 can_fast_clear
= false;
1239 unsigned level
= irb
->mt_level
;
1240 const unsigned num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1242 /* If the MCS buffer hasn't been allocated yet, we need to allocate it now.
1244 if (can_fast_clear
&& !irb
->mt
->aux_buf
) {
1245 assert(irb
->mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1246 if (!intel_miptree_alloc_aux(brw
, irb
->mt
)) {
1247 /* We're out of memory. Fall back to a non-fast clear. */
1248 can_fast_clear
= false;
1252 if (can_fast_clear
) {
1253 const enum isl_aux_state aux_state
=
1254 intel_miptree_get_aux_state(irb
->mt
, irb
->mt_level
, irb
->mt_layer
);
1255 union isl_color_value clear_color
=
1256 brw_meta_convert_fast_clear_color(brw
, irb
->mt
,
1257 &ctx
->Color
.ClearColor
);
1259 /* If the buffer is already in ISL_AUX_STATE_CLEAR and the clear color
1260 * hasn't changed, the clear is redundant and can be skipped.
1262 if (!intel_miptree_set_clear_color(brw
, irb
->mt
, clear_color
) &&
1263 aux_state
== ISL_AUX_STATE_CLEAR
) {
1267 DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__
,
1268 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
1270 /* We can't setup the blorp_surf until we've allocated the MCS above */
1271 struct blorp_surf surf
;
1272 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, irb
->mt
->aux_usage
, true,
1273 &level
, irb
->mt_layer
, num_layers
);
1275 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1277 * "Any transition from any value in {Clear, Render, Resolve} to a
1278 * different value in {Clear, Render, Resolve} requires end of pipe
1281 * In other words, fast clear ops are not properly synchronized with
1282 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1283 * contents of the previous draw hit the render target before we resolve
1284 * and again afterwards to ensure that the resolve is complete before we
1285 * do any more regular drawing.
1287 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1289 struct blorp_batch batch
;
1290 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1291 blorp_fast_clear(&batch
, &surf
, isl_format_srgb_to_linear(isl_format
),
1292 level
, irb
->mt_layer
, num_layers
, x0
, y0
, x1
, y1
);
1293 blorp_batch_finish(&batch
);
1295 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1297 /* Now that the fast clear has occurred, put the buffer in
1298 * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
1301 intel_miptree_set_aux_state(brw
, irb
->mt
, irb
->mt_level
,
1302 irb
->mt_layer
, num_layers
,
1303 ISL_AUX_STATE_CLEAR
);
1305 DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__
,
1306 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
1308 enum isl_aux_usage aux_usage
=
1309 intel_miptree_render_aux_usage(brw
, irb
->mt
, isl_format
,
1311 intel_miptree_prepare_render(brw
, irb
->mt
, level
, irb
->mt_layer
,
1312 num_layers
, aux_usage
);
1314 struct blorp_surf surf
;
1315 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, aux_usage
, true,
1316 &level
, irb
->mt_layer
, num_layers
);
1318 union isl_color_value clear_color
;
1319 memcpy(clear_color
.f32
, ctx
->Color
.ClearColor
.f
, sizeof(float) * 4);
1321 struct blorp_batch batch
;
1322 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1323 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
1324 level
, irb
->mt_layer
, num_layers
,
1326 clear_color
, color_write_disable
);
1327 blorp_batch_finish(&batch
);
1329 intel_miptree_finish_render(brw
, irb
->mt
, level
, irb
->mt_layer
,
1330 num_layers
, aux_usage
);
1337 brw_blorp_clear_color(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
1338 GLbitfield mask
, bool partial_clear
, bool encode_srgb
)
1340 for (unsigned buf
= 0; buf
< fb
->_NumColorDrawBuffers
; buf
++) {
1341 struct gl_renderbuffer
*rb
= fb
->_ColorDrawBuffers
[buf
];
1342 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
1344 /* Only clear the buffers present in the provided mask */
1345 if (((1 << fb
->_ColorDrawBufferIndexes
[buf
]) & mask
) == 0)
1348 /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
1349 * the framebuffer can be complete with some attachments missing. In
1350 * this case the _ColorDrawBuffers pointer will be NULL.
1355 do_single_blorp_clear(brw
, fb
, rb
, buf
, partial_clear
, encode_srgb
);
1356 irb
->need_downsample
= true;
1363 brw_blorp_clear_depth_stencil(struct brw_context
*brw
,
1364 struct gl_framebuffer
*fb
,
1365 GLbitfield mask
, bool partial_clear
)
1367 const struct gl_context
*ctx
= &brw
->ctx
;
1368 struct gl_renderbuffer
*depth_rb
=
1369 fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
;
1370 struct gl_renderbuffer
*stencil_rb
=
1371 fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
1373 if (!depth_rb
|| ctx
->Depth
.Mask
== GL_FALSE
)
1374 mask
&= ~BUFFER_BIT_DEPTH
;
1376 if (!stencil_rb
|| (ctx
->Stencil
.WriteMask
[0] & 0xff) == 0)
1377 mask
&= ~BUFFER_BIT_STENCIL
;
1379 if (!(mask
& (BUFFER_BITS_DEPTH_STENCIL
)))
1382 uint32_t x0
, x1
, y0
, y1
, rb_height
;
1384 rb_height
= depth_rb
->Height
;
1386 assert(depth_rb
->Width
== stencil_rb
->Width
);
1387 assert(depth_rb
->Height
== stencil_rb
->Height
);
1391 rb_height
= stencil_rb
->Height
;
1397 y0
= rb_height
- fb
->_Ymax
;
1398 y1
= rb_height
- fb
->_Ymin
;
1404 /* If the clear region is empty, just return. */
1405 if (x0
== x1
|| y0
== y1
)
1408 uint32_t level
, start_layer
, num_layers
;
1409 struct blorp_surf depth_surf
, stencil_surf
;
1411 struct intel_mipmap_tree
*depth_mt
= NULL
;
1412 if (mask
& BUFFER_BIT_DEPTH
) {
1413 struct intel_renderbuffer
*irb
= intel_renderbuffer(depth_rb
);
1414 depth_mt
= find_miptree(GL_DEPTH_BUFFER_BIT
, irb
);
1416 level
= irb
->mt_level
;
1417 start_layer
= irb
->mt_layer
;
1418 num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1420 intel_miptree_prepare_depth(brw
, depth_mt
, level
,
1421 start_layer
, num_layers
);
1423 unsigned depth_level
= level
;
1424 blorp_surf_for_miptree(brw
, &depth_surf
, depth_mt
, depth_mt
->aux_usage
,
1425 true, &depth_level
, start_layer
, num_layers
);
1426 assert(depth_level
== level
);
1429 uint8_t stencil_mask
= 0;
1430 struct intel_mipmap_tree
*stencil_mt
= NULL
;
1431 if (mask
& BUFFER_BIT_STENCIL
) {
1432 struct intel_renderbuffer
*irb
= intel_renderbuffer(stencil_rb
);
1433 stencil_mt
= find_miptree(GL_STENCIL_BUFFER_BIT
, irb
);
1435 if (mask
& BUFFER_BIT_DEPTH
) {
1436 assert(level
== irb
->mt_level
);
1437 assert(start_layer
== irb
->mt_layer
);
1438 assert(num_layers
== fb
->MaxNumLayers
? irb
->layer_count
: 1);
1441 level
= irb
->mt_level
;
1442 start_layer
= irb
->mt_layer
;
1443 num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1445 stencil_mask
= ctx
->Stencil
.WriteMask
[0] & 0xff;
1447 intel_miptree_prepare_access(brw
, stencil_mt
, level
, 1,
1448 start_layer
, num_layers
,
1449 ISL_AUX_USAGE_NONE
, false);
1451 unsigned stencil_level
= level
;
1452 blorp_surf_for_miptree(brw
, &stencil_surf
, stencil_mt
,
1453 ISL_AUX_USAGE_NONE
, true,
1454 &stencil_level
, start_layer
, num_layers
);
1457 assert((mask
& BUFFER_BIT_DEPTH
) || stencil_mask
);
1459 struct blorp_batch batch
;
1460 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1461 blorp_clear_depth_stencil(&batch
, &depth_surf
, &stencil_surf
,
1462 level
, start_layer
, num_layers
,
1464 (mask
& BUFFER_BIT_DEPTH
), ctx
->Depth
.Clear
,
1465 stencil_mask
, ctx
->Stencil
.Clear
);
1466 blorp_batch_finish(&batch
);
1468 if (mask
& BUFFER_BIT_DEPTH
) {
1469 intel_miptree_finish_depth(brw
, depth_mt
, level
,
1470 start_layer
, num_layers
, true);
1474 intel_miptree_finish_write(brw
, stencil_mt
, level
,
1475 start_layer
, num_layers
,
1476 ISL_AUX_USAGE_NONE
);
1481 brw_blorp_resolve_color(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1482 unsigned level
, unsigned layer
,
1483 enum isl_aux_op resolve_op
)
1485 DBG("%s to mt %p level %u layer %u\n", __FUNCTION__
, mt
, level
, layer
);
1487 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
1489 struct blorp_surf surf
;
1490 blorp_surf_for_miptree(brw
, &surf
, mt
, mt
->aux_usage
, true,
1491 &level
, layer
, 1 /* num_layers */);
1493 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1495 * "Any transition from any value in {Clear, Render, Resolve} to a
1496 * different value in {Clear, Render, Resolve} requires end of pipe
1499 * In other words, fast clear ops are not properly synchronized with
1500 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1501 * contents of the previous draw hit the render target before we resolve
1502 * and again afterwards to ensure that the resolve is complete before we
1503 * do any more regular drawing.
1505 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1508 struct blorp_batch batch
;
1509 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1510 blorp_ccs_resolve(&batch
, &surf
, level
, layer
, 1,
1511 brw_blorp_to_isl_format(brw
, format
, true),
1513 blorp_batch_finish(&batch
);
1515 /* See comment above */
1516 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1520 brw_blorp_mcs_partial_resolve(struct brw_context
*brw
,
1521 struct intel_mipmap_tree
*mt
,
1522 uint32_t start_layer
, uint32_t num_layers
)
1524 DBG("%s to mt %p layers %u-%u\n", __FUNCTION__
, mt
,
1525 start_layer
, start_layer
+ num_layers
- 1);
1527 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1529 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
1530 enum isl_format isl_format
= brw_blorp_to_isl_format(brw
, format
, true);
1532 struct blorp_surf surf
;
1534 blorp_surf_for_miptree(brw
, &surf
, mt
, ISL_AUX_USAGE_MCS
, true,
1535 &level
, start_layer
, num_layers
);
1537 struct blorp_batch batch
;
1538 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1539 blorp_mcs_partial_resolve(&batch
, &surf
, isl_format
,
1540 start_layer
, num_layers
);
1541 blorp_batch_finish(&batch
);
1545 * Perform a HiZ or depth resolve operation.
1547 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
1548 * PRM, Volume 1, Part 2:
1549 * - 7.5.3.1 Depth Buffer Clear
1550 * - 7.5.3.2 Depth Buffer Resolve
1551 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1554 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1555 unsigned int level
, unsigned int start_layer
,
1556 unsigned int num_layers
, enum isl_aux_op op
)
1558 assert(intel_miptree_level_has_hiz(mt
, level
));
1559 assert(op
!= ISL_AUX_OP_NONE
);
1560 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1561 const char *opname
= NULL
;
1564 case ISL_AUX_OP_FULL_RESOLVE
:
1565 opname
= "depth resolve";
1567 case ISL_AUX_OP_AMBIGUATE
:
1568 opname
= "hiz ambiguate";
1570 case ISL_AUX_OP_FAST_CLEAR
:
1571 opname
= "depth clear";
1573 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1574 case ISL_AUX_OP_NONE
:
1575 unreachable("Invalid HiZ op");
1578 DBG("%s %s to mt %p level %d layers %d-%d\n",
1579 __func__
, opname
, mt
, level
, start_layer
, start_layer
+ num_layers
- 1);
1581 /* The following stalls and flushes are only documented to be required for
1582 * HiZ clear operations. However, they also seem to be required for
1583 * resolve operations.
1585 if (devinfo
->gen
== 6) {
1586 /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
1588 * "If other rendering operations have preceded this clear, a
1589 * PIPE_CONTROL with write cache flush enabled and Z-inhibit
1590 * disabled must be issued before the rectangle primitive used for
1591 * the depth buffer clear operation.
1593 brw_emit_pipe_control_flush(brw
,
1594 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1595 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1596 PIPE_CONTROL_CS_STALL
);
1597 } else if (devinfo
->gen
>= 7) {
1599 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
1601 * If other rendering operations have preceded this clear, a
1602 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
1603 * enabled must be issued before the rectangle primitive used for
1604 * the depth buffer clear operation.
1606 * Same applies for Gen8 and Gen9.
1608 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
1609 * PIPE_CONTROL, Depth Cache Flush Enable:
1611 * This bit must not be set when Depth Stall Enable bit is set in
1614 * This is confirmed to hold for real, HSW gets immediate gpu hangs.
1616 * Therefore issue two pipe control flushes, one for cache flush and
1617 * another for depth stall.
1619 brw_emit_pipe_control_flush(brw
,
1620 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1621 PIPE_CONTROL_CS_STALL
);
1623 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
1626 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
&& mt
->aux_buf
);
1628 struct blorp_surf surf
;
1629 blorp_surf_for_miptree(brw
, &surf
, mt
, ISL_AUX_USAGE_HIZ
, true,
1630 &level
, start_layer
, num_layers
);
1632 struct blorp_batch batch
;
1633 blorp_batch_init(&brw
->blorp
, &batch
, brw
,
1634 BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
);
1635 blorp_hiz_op(&batch
, &surf
, level
, start_layer
, num_layers
, op
);
1636 blorp_batch_finish(&batch
);
1638 /* The following stalls and flushes are only documented to be required for
1639 * HiZ clear operations. However, they also seem to be required for
1640 * resolve operations.
1642 if (devinfo
->gen
== 6) {
1643 /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
1645 * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be
1646 * followed by a PIPE_CONTROL command with DEPTH_STALL bit set
1647 * and Then followed by Depth FLUSH'
1649 brw_emit_pipe_control_flush(brw
,
1650 PIPE_CONTROL_DEPTH_STALL
);
1652 brw_emit_pipe_control_flush(brw
,
1653 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1654 PIPE_CONTROL_CS_STALL
);
1655 } else if (devinfo
->gen
>= 8) {
1657 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
1659 * "Depth buffer clear pass using any of the methods (WM_STATE,
1660 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
1661 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
1662 * "set" before starting to render. DepthStall and DepthFlush are
1663 * not needed between consecutive depth clear passes nor is it
1664 * required if the depth clear pass was done with
1665 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
1667 * TODO: Such as the spec says, this could be conditional.
1669 brw_emit_pipe_control_flush(brw
,
1670 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1671 PIPE_CONTROL_DEPTH_STALL
);