2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/blend.h"
27 #include "main/fbobject.h"
28 #include "main/renderbuffer.h"
29 #include "main/glformats.h"
31 #include "brw_blorp.h"
32 #include "brw_context.h"
33 #include "brw_defines.h"
34 #include "brw_meta_util.h"
35 #include "brw_state.h"
36 #include "intel_fbo.h"
37 #include "common/gen_debug.h"
39 #define FILE_DEBUG_FLAG DEBUG_BLORP
42 brw_blorp_lookup_shader(struct blorp_context
*blorp
,
43 const void *key
, uint32_t key_size
,
44 uint32_t *kernel_out
, void *prog_data_out
)
46 struct brw_context
*brw
= blorp
->driver_ctx
;
47 return brw_search_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
,
48 key
, key_size
, kernel_out
, prog_data_out
);
52 brw_blorp_upload_shader(struct blorp_context
*blorp
,
53 const void *key
, uint32_t key_size
,
54 const void *kernel
, uint32_t kernel_size
,
55 const struct brw_stage_prog_data
*prog_data
,
56 uint32_t prog_data_size
,
57 uint32_t *kernel_out
, void *prog_data_out
)
59 struct brw_context
*brw
= blorp
->driver_ctx
;
60 brw_upload_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
, key
, key_size
,
61 kernel
, kernel_size
, prog_data
, prog_data_size
,
62 kernel_out
, prog_data_out
);
67 brw_blorp_init(struct brw_context
*brw
)
69 blorp_init(&brw
->blorp
, brw
, &brw
->isl_dev
);
71 brw
->blorp
.compiler
= brw
->screen
->compiler
;
76 brw
->blorp
.exec
= gen45_blorp_exec
;
78 brw
->blorp
.exec
= gen4_blorp_exec
;
82 brw
->blorp
.exec
= gen5_blorp_exec
;
85 brw
->blorp
.mocs
.tex
= 0;
86 brw
->blorp
.mocs
.rb
= 0;
87 brw
->blorp
.mocs
.vb
= 0;
88 brw
->blorp
.exec
= gen6_blorp_exec
;
91 brw
->blorp
.mocs
.tex
= GEN7_MOCS_L3
;
92 brw
->blorp
.mocs
.rb
= GEN7_MOCS_L3
;
93 brw
->blorp
.mocs
.vb
= GEN7_MOCS_L3
;
94 if (brw
->is_haswell
) {
95 brw
->blorp
.exec
= gen75_blorp_exec
;
97 brw
->blorp
.exec
= gen7_blorp_exec
;
101 brw
->blorp
.mocs
.tex
= BDW_MOCS_WB
;
102 brw
->blorp
.mocs
.rb
= BDW_MOCS_PTE
;
103 brw
->blorp
.mocs
.vb
= BDW_MOCS_WB
;
104 brw
->blorp
.exec
= gen8_blorp_exec
;
107 brw
->blorp
.mocs
.tex
= SKL_MOCS_WB
;
108 brw
->blorp
.mocs
.rb
= SKL_MOCS_PTE
;
109 brw
->blorp
.mocs
.vb
= SKL_MOCS_WB
;
110 brw
->blorp
.exec
= gen9_blorp_exec
;
113 brw
->blorp
.mocs
.tex
= CNL_MOCS_WB
;
114 brw
->blorp
.mocs
.rb
= CNL_MOCS_PTE
;
115 brw
->blorp
.mocs
.vb
= CNL_MOCS_WB
;
116 brw
->blorp
.exec
= gen10_blorp_exec
;
119 unreachable("Invalid gen");
122 brw
->blorp
.lookup_shader
= brw_blorp_lookup_shader
;
123 brw
->blorp
.upload_shader
= brw_blorp_upload_shader
;
127 blorp_surf_for_miptree(struct brw_context
*brw
,
128 struct blorp_surf
*surf
,
129 struct intel_mipmap_tree
*mt
,
130 enum isl_aux_usage aux_usage
,
131 bool is_render_target
,
133 unsigned start_layer
, unsigned num_layers
,
134 struct isl_surf tmp_surfs
[1])
136 if (mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
) {
137 const unsigned num_samples
= mt
->surf
.samples
;
138 for (unsigned i
= 0; i
< num_layers
; i
++) {
139 for (unsigned s
= 0; s
< num_samples
; s
++) {
140 const unsigned phys_layer
= (start_layer
+ i
) * num_samples
+ s
;
141 intel_miptree_check_level_layer(mt
, *level
, phys_layer
);
145 for (unsigned i
= 0; i
< num_layers
; i
++)
146 intel_miptree_check_level_layer(mt
, *level
, start_layer
+ i
);
149 surf
->surf
= &mt
->surf
;
150 surf
->addr
= (struct blorp_address
) {
152 .offset
= mt
->offset
,
153 .read_domains
= is_render_target
? I915_GEM_DOMAIN_RENDER
:
154 I915_GEM_DOMAIN_SAMPLER
,
155 .write_domain
= is_render_target
? I915_GEM_DOMAIN_RENDER
: 0,
158 surf
->aux_usage
= aux_usage
;
160 struct isl_surf
*aux_surf
= NULL
;
162 aux_surf
= &mt
->mcs_buf
->surf
;
163 else if (mt
->hiz_buf
)
164 aux_surf
= &mt
->hiz_buf
->surf
;
166 if (surf
->aux_usage
== ISL_AUX_USAGE_HIZ
&&
167 !intel_miptree_level_has_hiz(mt
, *level
))
168 surf
->aux_usage
= ISL_AUX_USAGE_NONE
;
170 if (surf
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
171 /* We only really need a clear color if we also have an auxiliary
172 * surface. Without one, it does nothing.
174 surf
->clear_color
= mt
->fast_clear_color
;
176 surf
->aux_surf
= aux_surf
;
177 surf
->aux_addr
= (struct blorp_address
) {
178 .read_domains
= is_render_target
? I915_GEM_DOMAIN_RENDER
:
179 I915_GEM_DOMAIN_SAMPLER
,
180 .write_domain
= is_render_target
? I915_GEM_DOMAIN_RENDER
: 0,
184 surf
->aux_addr
.buffer
= mt
->mcs_buf
->bo
;
185 surf
->aux_addr
.offset
= mt
->mcs_buf
->offset
;
187 assert(surf
->aux_usage
== ISL_AUX_USAGE_HIZ
);
189 surf
->aux_addr
.buffer
= mt
->hiz_buf
->bo
;
190 surf
->aux_addr
.offset
= mt
->hiz_buf
->offset
;
193 surf
->aux_addr
= (struct blorp_address
) {
196 memset(&surf
->clear_color
, 0, sizeof(surf
->clear_color
));
198 assert((surf
->aux_usage
== ISL_AUX_USAGE_NONE
) ==
199 (surf
->aux_addr
.buffer
== NULL
));
201 /* ISL wants real levels, not offset ones. */
202 *level
-= mt
->first_level
;
205 static enum isl_format
206 brw_blorp_to_isl_format(struct brw_context
*brw
, mesa_format format
,
207 bool is_render_target
)
210 case MESA_FORMAT_NONE
:
211 return ISL_FORMAT_UNSUPPORTED
;
212 case MESA_FORMAT_S_UINT8
:
213 return ISL_FORMAT_R8_UINT
;
214 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
215 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
216 return ISL_FORMAT_R24_UNORM_X8_TYPELESS
;
217 case MESA_FORMAT_Z_FLOAT32
:
218 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
219 return ISL_FORMAT_R32_FLOAT
;
220 case MESA_FORMAT_Z_UNORM16
:
221 return ISL_FORMAT_R16_UNORM
;
223 if (is_render_target
) {
224 assert(brw
->mesa_format_supports_render
[format
]);
225 return brw
->mesa_to_isl_render_format
[format
];
227 return brw_isl_format_for_mesa_format(format
);
235 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
236 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
238 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
241 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
243 * which is simply adding 4 then modding by 8 (or anding with 7).
245 * We then may need to apply workarounds for textureGather hardware bugs.
247 static enum isl_channel_select
248 swizzle_to_scs(GLenum swizzle
)
250 return (enum isl_channel_select
)((swizzle
+ 4) & 7);
254 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
255 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
256 * the physical layer holding sample 0. So, for example, if
257 * src_mt->surf.samples == 4, then logical layer n corresponds to src_layer ==
261 brw_blorp_blit_miptrees(struct brw_context
*brw
,
262 struct intel_mipmap_tree
*src_mt
,
263 unsigned src_level
, unsigned src_layer
,
264 mesa_format src_format
, int src_swizzle
,
265 struct intel_mipmap_tree
*dst_mt
,
266 unsigned dst_level
, unsigned dst_layer
,
267 mesa_format dst_format
,
268 float src_x0
, float src_y0
,
269 float src_x1
, float src_y1
,
270 float dst_x0
, float dst_y0
,
271 float dst_x1
, float dst_y1
,
272 GLenum filter
, bool mirror_x
, bool mirror_y
,
273 bool decode_srgb
, bool encode_srgb
)
275 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
276 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
278 src_mt
->surf
.samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
279 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
280 dst_mt
->surf
.samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
281 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
284 if (!decode_srgb
&& _mesa_get_format_color_encoding(src_format
) == GL_SRGB
)
285 src_format
= _mesa_get_srgb_format_linear(src_format
);
287 if (!encode_srgb
&& _mesa_get_format_color_encoding(dst_format
) == GL_SRGB
)
288 dst_format
= _mesa_get_srgb_format_linear(dst_format
);
290 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
291 * texture, the above code configures the source format for L32_FLOAT or
292 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
293 * the SAMPLE message appears to handle multisampled L32_FLOAT and
294 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
295 * around the problem by using a source format of R32_FLOAT. This
296 * shouldn't affect rendering correctness, since the destination format is
297 * R32_FLOAT, so only the contents of the red channel matters.
300 src_mt
->surf
.samples
> 1 && dst_mt
->surf
.samples
<= 1 &&
301 src_mt
->format
== dst_mt
->format
&&
302 (dst_format
== MESA_FORMAT_L_FLOAT32
||
303 dst_format
== MESA_FORMAT_I_FLOAT32
)) {
304 src_format
= dst_format
= MESA_FORMAT_R_FLOAT32
;
307 enum isl_aux_usage src_aux_usage
=
308 intel_miptree_texture_aux_usage(brw
, src_mt
, src_format
);
309 /* We do format workarounds for some depth formats so we can't reliably
310 * sample with HiZ. One of these days, we should fix that.
312 if (src_aux_usage
== ISL_AUX_USAGE_HIZ
)
313 src_aux_usage
= ISL_AUX_USAGE_NONE
;
314 const bool src_clear_supported
=
315 src_aux_usage
!= ISL_AUX_USAGE_NONE
&& src_mt
->format
== src_format
;
316 intel_miptree_prepare_access(brw
, src_mt
, src_level
, 1, src_layer
, 1,
317 src_aux_usage
, src_clear_supported
);
319 enum isl_aux_usage dst_aux_usage
=
320 intel_miptree_render_aux_usage(brw
, dst_mt
, encode_srgb
, false);
321 const bool dst_clear_supported
= dst_aux_usage
!= ISL_AUX_USAGE_NONE
;
322 intel_miptree_prepare_access(brw
, dst_mt
, dst_level
, 1, dst_layer
, 1,
323 dst_aux_usage
, dst_clear_supported
);
325 struct isl_surf tmp_surfs
[2];
326 struct blorp_surf src_surf
, dst_surf
;
327 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, src_aux_usage
, false,
328 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
329 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, dst_aux_usage
, true,
330 &dst_level
, dst_layer
, 1, &tmp_surfs
[1]);
332 struct isl_swizzle src_isl_swizzle
= {
333 .r
= swizzle_to_scs(GET_SWZ(src_swizzle
, 0)),
334 .g
= swizzle_to_scs(GET_SWZ(src_swizzle
, 1)),
335 .b
= swizzle_to_scs(GET_SWZ(src_swizzle
, 2)),
336 .a
= swizzle_to_scs(GET_SWZ(src_swizzle
, 3)),
339 struct blorp_batch batch
;
340 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
341 blorp_blit(&batch
, &src_surf
, src_level
, src_layer
,
342 brw_blorp_to_isl_format(brw
, src_format
, false), src_isl_swizzle
,
343 &dst_surf
, dst_level
, dst_layer
,
344 brw_blorp_to_isl_format(brw
, dst_format
, true),
345 ISL_SWIZZLE_IDENTITY
,
346 src_x0
, src_y0
, src_x1
, src_y1
,
347 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
348 filter
, mirror_x
, mirror_y
);
349 blorp_batch_finish(&batch
);
351 intel_miptree_finish_write(brw
, dst_mt
, dst_level
, dst_layer
, 1,
356 brw_blorp_copy_miptrees(struct brw_context
*brw
,
357 struct intel_mipmap_tree
*src_mt
,
358 unsigned src_level
, unsigned src_layer
,
359 struct intel_mipmap_tree
*dst_mt
,
360 unsigned dst_level
, unsigned dst_layer
,
361 unsigned src_x
, unsigned src_y
,
362 unsigned dst_x
, unsigned dst_y
,
363 unsigned src_width
, unsigned src_height
)
365 DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
366 "to %dx %s mt %p %d %d (%d,%d)\n",
368 src_mt
->surf
.samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
369 src_level
, src_layer
, src_x
, src_y
, src_width
, src_height
,
370 dst_mt
->surf
.samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
371 dst_level
, dst_layer
, dst_x
, dst_y
);
373 enum isl_aux_usage src_aux_usage
, dst_aux_usage
;
374 bool src_clear_supported
, dst_clear_supported
;
376 switch (src_mt
->aux_usage
) {
377 case ISL_AUX_USAGE_MCS
:
378 case ISL_AUX_USAGE_CCS_E
:
379 src_aux_usage
= src_mt
->aux_usage
;
380 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
381 * we're going to re-interpret the format as an integer format possibly
382 * with a different number of components, we can't handle clear colors
385 src_clear_supported
= brw
->gen
>= 9;
388 src_aux_usage
= ISL_AUX_USAGE_NONE
;
389 src_clear_supported
= false;
393 switch (dst_mt
->aux_usage
) {
394 case ISL_AUX_USAGE_MCS
:
395 case ISL_AUX_USAGE_CCS_E
:
396 dst_aux_usage
= dst_mt
->aux_usage
;
397 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
398 * we're going to re-interpret the format as an integer format possibly
399 * with a different number of components, we can't handle clear colors
402 dst_clear_supported
= brw
->gen
>= 9;
405 dst_aux_usage
= ISL_AUX_USAGE_NONE
;
406 dst_clear_supported
= false;
410 intel_miptree_prepare_access(brw
, src_mt
, src_level
, 1, src_layer
, 1,
411 src_aux_usage
, src_clear_supported
);
412 intel_miptree_prepare_access(brw
, dst_mt
, dst_level
, 1, dst_layer
, 1,
413 dst_aux_usage
, dst_clear_supported
);
415 struct isl_surf tmp_surfs
[2];
416 struct blorp_surf src_surf
, dst_surf
;
417 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, src_aux_usage
, false,
418 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
419 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, dst_aux_usage
, true,
420 &dst_level
, dst_layer
, 1, &tmp_surfs
[1]);
422 struct blorp_batch batch
;
423 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
424 blorp_copy(&batch
, &src_surf
, src_level
, src_layer
,
425 &dst_surf
, dst_level
, dst_layer
,
426 src_x
, src_y
, dst_x
, dst_y
, src_width
, src_height
);
427 blorp_batch_finish(&batch
);
429 intel_miptree_finish_write(brw
, dst_mt
, dst_level
, dst_layer
, 1,
433 static struct intel_mipmap_tree
*
434 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
436 struct intel_mipmap_tree
*mt
= irb
->mt
;
437 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
443 blorp_get_texture_swizzle(const struct intel_renderbuffer
*irb
)
445 return irb
->Base
.Base
._BaseFormat
== GL_RGB
?
446 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ONE
) :
451 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
452 struct intel_renderbuffer
*src_irb
, mesa_format src_format
,
453 struct intel_renderbuffer
*dst_irb
, mesa_format dst_format
,
454 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
455 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
456 GLenum filter
, bool mirror_x
, bool mirror_y
)
458 const struct gl_context
*ctx
= &brw
->ctx
;
460 /* Find source/dst miptrees */
461 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
462 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
464 const bool do_srgb
= ctx
->Color
.sRGBEnabled
;
467 brw_blorp_blit_miptrees(brw
,
468 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
469 src_format
, blorp_get_texture_swizzle(src_irb
),
470 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
472 srcX0
, srcY0
, srcX1
, srcY1
,
473 dstX0
, dstY0
, dstX1
, dstY1
,
474 filter
, mirror_x
, mirror_y
,
477 dst_irb
->need_downsample
= true;
481 try_blorp_blit(struct brw_context
*brw
,
482 const struct gl_framebuffer
*read_fb
,
483 const struct gl_framebuffer
*draw_fb
,
484 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
485 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
486 GLenum filter
, GLbitfield buffer_bit
)
488 struct gl_context
*ctx
= &brw
->ctx
;
490 /* Sync up the state of window system buffers. We need to do this before
491 * we go looking for the buffers.
493 intel_prepare_render(brw
);
495 bool mirror_x
, mirror_y
;
496 if (brw_meta_mirror_clip_and_scissor(ctx
, read_fb
, draw_fb
,
497 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
498 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
499 &mirror_x
, &mirror_y
))
503 struct intel_renderbuffer
*src_irb
;
504 struct intel_renderbuffer
*dst_irb
;
505 struct intel_mipmap_tree
*src_mt
;
506 struct intel_mipmap_tree
*dst_mt
;
507 switch (buffer_bit
) {
508 case GL_COLOR_BUFFER_BIT
:
509 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
510 for (unsigned i
= 0; i
< draw_fb
->_NumColorDrawBuffers
; ++i
) {
511 dst_irb
= intel_renderbuffer(draw_fb
->_ColorDrawBuffers
[i
]);
513 do_blorp_blit(brw
, buffer_bit
,
514 src_irb
, src_irb
->Base
.Base
.Format
,
515 dst_irb
, dst_irb
->Base
.Base
.Format
,
516 srcX0
, srcY0
, srcX1
, srcY1
,
517 dstX0
, dstY0
, dstX1
, dstY1
,
518 filter
, mirror_x
, mirror_y
);
521 case GL_DEPTH_BUFFER_BIT
:
523 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
525 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
526 src_mt
= find_miptree(buffer_bit
, src_irb
);
527 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
529 /* We can't handle format conversions between Z24 and other formats
530 * since we have to lie about the surface format. See the comments in
531 * brw_blorp_surface_info::set().
533 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
534 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
))
537 /* We also can't handle any combined depth-stencil formats because we
538 * have to reinterpret as a color format.
540 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
541 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
544 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
545 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
546 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
547 filter
, mirror_x
, mirror_y
);
549 case GL_STENCIL_BUFFER_BIT
:
550 /* Blorp doesn't support combined depth stencil which is all we have
557 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
559 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
560 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
561 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
562 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
563 filter
, mirror_x
, mirror_y
);
566 unreachable("not reached");
573 brw_blorp_copytexsubimage(struct brw_context
*brw
,
574 struct gl_renderbuffer
*src_rb
,
575 struct gl_texture_image
*dst_image
,
577 int srcX0
, int srcY0
,
578 int dstX0
, int dstY0
,
579 int width
, int height
)
581 struct gl_context
*ctx
= &brw
->ctx
;
582 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
583 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
585 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
586 if (brw
->ctx
._ImageTransferState
)
589 /* Sync up the state of window system buffers. We need to do this before
590 * we go looking at the src renderbuffer's miptree.
592 intel_prepare_render(brw
);
594 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
595 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
597 /* There is support for only up to eight samples. */
598 if (src_mt
->surf
.samples
> 8 || dst_mt
->surf
.samples
> 8)
601 if (_mesa_get_format_base_format(src_rb
->Format
) !=
602 _mesa_get_format_base_format(dst_image
->TexFormat
)) {
606 /* We can't handle format conversions between Z24 and other formats since
607 * we have to lie about the surface format. See the comments in
608 * brw_blorp_surface_info::set().
610 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
611 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
)) {
615 /* We also can't handle any combined depth-stencil formats because we
616 * have to reinterpret as a color format.
618 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
619 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
622 if (!brw
->mesa_format_supports_render
[dst_image
->TexFormat
])
625 /* Source clipping shouldn't be necessary, since copytexsubimage (in
626 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
629 * Destination clipping shouldn't be necessary since the restrictions on
630 * glCopyTexSubImage prevent the user from specifying a destination rectangle
631 * that falls outside the bounds of the destination texture.
632 * See error_check_subtexture_dimensions().
635 int srcY1
= srcY0
+ height
;
636 int srcX1
= srcX0
+ width
;
637 int dstX1
= dstX0
+ width
;
638 int dstY1
= dstY0
+ height
;
640 /* Account for the fact that in the system framebuffer, the origin is at
643 bool mirror_y
= false;
644 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
645 GLint tmp
= src_rb
->Height
- srcY0
;
646 srcY0
= src_rb
->Height
- srcY1
;
651 /* Account for face selection and texture view MinLayer */
652 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
653 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
655 brw_blorp_blit_miptrees(brw
,
656 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
657 src_rb
->Format
, blorp_get_texture_swizzle(src_irb
),
658 dst_mt
, dst_level
, dst_slice
,
659 dst_image
->TexFormat
,
660 srcX0
, srcY0
, srcX1
, srcY1
,
661 dstX0
, dstY0
, dstX1
, dstY1
,
662 GL_NEAREST
, false, mirror_y
,
665 /* If we're copying to a packed depth stencil texture and the source
666 * framebuffer has separate stencil, we need to also copy the stencil data
669 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
670 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
672 src_irb
= intel_renderbuffer(src_rb
);
673 src_mt
= src_irb
->mt
;
675 if (src_mt
->stencil_mt
)
676 src_mt
= src_mt
->stencil_mt
;
677 if (dst_mt
->stencil_mt
)
678 dst_mt
= dst_mt
->stencil_mt
;
680 if (src_mt
!= dst_mt
) {
681 brw_blorp_blit_miptrees(brw
,
682 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
684 blorp_get_texture_swizzle(src_irb
),
685 dst_mt
, dst_level
, dst_slice
,
687 srcX0
, srcY0
, srcX1
, srcY1
,
688 dstX0
, dstY0
, dstX1
, dstY1
,
689 GL_NEAREST
, false, mirror_y
,
699 brw_blorp_framebuffer(struct brw_context
*brw
,
700 struct gl_framebuffer
*readFb
,
701 struct gl_framebuffer
*drawFb
,
702 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
703 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
704 GLbitfield mask
, GLenum filter
)
706 static GLbitfield buffer_bits
[] = {
709 GL_STENCIL_BUFFER_BIT
,
712 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
713 if ((mask
& buffer_bits
[i
]) &&
714 try_blorp_blit(brw
, readFb
, drawFb
,
715 srcX0
, srcY0
, srcX1
, srcY1
,
716 dstX0
, dstY0
, dstX1
, dstY1
,
717 filter
, buffer_bits
[i
])) {
718 mask
&= ~buffer_bits
[i
];
726 set_write_disables(const struct intel_renderbuffer
*irb
,
727 const GLubyte
*color_mask
, bool *color_write_disable
)
729 /* Format information in the renderbuffer represents the requirements
730 * given by the client. There are cases where the backing miptree uses,
731 * for example, RGBA to represent RGBX. Since the client is only expecting
732 * RGB we can treat alpha as not used and write whatever we like into it.
734 const GLenum base_format
= irb
->Base
.Base
._BaseFormat
;
735 const int components
= _mesa_base_format_component_count(base_format
);
736 bool disables
= false;
738 assert(components
> 0);
740 for (int i
= 0; i
< components
; i
++) {
741 color_write_disable
[i
] = !color_mask
[i
];
742 disables
= disables
|| !color_mask
[i
];
749 do_single_blorp_clear(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
750 struct gl_renderbuffer
*rb
, unsigned buf
,
751 bool partial_clear
, bool encode_srgb
)
753 struct gl_context
*ctx
= &brw
->ctx
;
754 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
755 uint32_t x0
, x1
, y0
, y1
;
757 mesa_format format
= irb
->Base
.Base
.Format
;
758 if (!encode_srgb
&& _mesa_get_format_color_encoding(format
) == GL_SRGB
)
759 format
= _mesa_get_srgb_format_linear(format
);
767 y0
= rb
->Height
- fb
->_Ymax
;
768 y1
= rb
->Height
- fb
->_Ymin
;
771 /* If the clear region is empty, just return. */
772 if (x0
== x1
|| y0
== y1
)
775 bool can_fast_clear
= !partial_clear
;
777 bool color_write_disable
[4] = { false, false, false, false };
778 if (set_write_disables(irb
, ctx
->Color
.ColorMask
[buf
], color_write_disable
))
779 can_fast_clear
= false;
781 /* We store clear colors as floats or uints as needed. If there are
782 * texture views in play, the formats will not properly be respected
783 * during resolves because the resolve operations only know about the
784 * miptree and not the renderbuffer.
786 if (irb
->Base
.Base
.Format
!= irb
->mt
->format
)
787 can_fast_clear
= false;
789 if (!irb
->mt
->supports_fast_clear
||
790 !brw_is_color_fast_clear_compatible(brw
, irb
->mt
, &ctx
->Color
.ClearColor
))
791 can_fast_clear
= false;
793 /* Surface state can only record one fast clear color value. Therefore
794 * unless different levels/layers agree on the color it can be used to
795 * represent only single level/layer. Here it will be reserved for the
796 * first slice (level 0, layer 0).
798 if (irb
->layer_count
> 1 || irb
->mt_level
|| irb
->mt_layer
)
799 can_fast_clear
= false;
801 unsigned level
= irb
->mt_level
;
802 const unsigned num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
804 /* If the MCS buffer hasn't been allocated yet, we need to allocate it now.
806 if (can_fast_clear
&& !irb
->mt
->mcs_buf
) {
807 assert(irb
->mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
808 if (!intel_miptree_alloc_ccs(brw
, irb
->mt
)) {
809 /* There are a few reasons in addition to out-of-memory, that can
810 * cause intel_miptree_alloc_non_msrt_mcs to fail. Try to recover by
811 * falling back to non-fast clear.
813 can_fast_clear
= false;
817 if (can_fast_clear
) {
818 const enum isl_aux_state aux_state
=
819 intel_miptree_get_aux_state(irb
->mt
, irb
->mt_level
, irb
->mt_layer
);
820 union isl_color_value clear_color
=
821 brw_meta_convert_fast_clear_color(brw
, irb
->mt
,
822 &ctx
->Color
.ClearColor
);
824 /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
825 * is redundant and can be skipped.
827 if (aux_state
== ISL_AUX_STATE_CLEAR
&&
828 memcmp(&irb
->mt
->fast_clear_color
,
829 &clear_color
, sizeof(clear_color
)) == 0)
832 irb
->mt
->fast_clear_color
= clear_color
;
834 DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__
,
835 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
837 /* We can't setup the blorp_surf until we've allocated the MCS above */
838 struct isl_surf isl_tmp
[2];
839 struct blorp_surf surf
;
840 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, irb
->mt
->aux_usage
, true,
841 &level
, irb
->mt_layer
, num_layers
, isl_tmp
);
843 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
845 * "Any transition from any value in {Clear, Render, Resolve} to a
846 * different value in {Clear, Render, Resolve} requires end of pipe
849 * In other words, fast clear ops are not properly synchronized with
850 * other drawing. We need to use a PIPE_CONTROL to ensure that the
851 * contents of the previous draw hit the render target before we resolve
852 * and again afterwards to ensure that the resolve is complete before we
853 * do any more regular drawing.
855 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
857 struct blorp_batch batch
;
858 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
859 blorp_fast_clear(&batch
, &surf
,
860 brw
->mesa_to_isl_render_format
[format
],
861 level
, irb
->mt_layer
, num_layers
,
863 blorp_batch_finish(&batch
);
865 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
867 /* Now that the fast clear has occurred, put the buffer in
868 * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
871 intel_miptree_set_aux_state(brw
, irb
->mt
, irb
->mt_level
,
872 irb
->mt_layer
, num_layers
,
873 ISL_AUX_STATE_CLEAR
);
875 DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__
,
876 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
878 enum isl_aux_usage aux_usage
=
879 intel_miptree_render_aux_usage(brw
, irb
->mt
, encode_srgb
, false);
880 intel_miptree_prepare_render(brw
, irb
->mt
, level
, irb
->mt_layer
,
881 num_layers
, encode_srgb
, false);
883 struct isl_surf isl_tmp
[2];
884 struct blorp_surf surf
;
885 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, aux_usage
, true,
886 &level
, irb
->mt_layer
, num_layers
, isl_tmp
);
888 union isl_color_value clear_color
;
889 memcpy(clear_color
.f32
, ctx
->Color
.ClearColor
.f
, sizeof(float) * 4);
891 struct blorp_batch batch
;
892 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
893 blorp_clear(&batch
, &surf
,
894 brw
->mesa_to_isl_render_format
[format
],
895 ISL_SWIZZLE_IDENTITY
,
896 level
, irb
->mt_layer
, num_layers
,
898 clear_color
, color_write_disable
);
899 blorp_batch_finish(&batch
);
901 intel_miptree_finish_render(brw
, irb
->mt
, level
, irb
->mt_layer
,
902 num_layers
, encode_srgb
, false);
909 brw_blorp_clear_color(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
910 GLbitfield mask
, bool partial_clear
, bool encode_srgb
)
912 for (unsigned buf
= 0; buf
< fb
->_NumColorDrawBuffers
; buf
++) {
913 struct gl_renderbuffer
*rb
= fb
->_ColorDrawBuffers
[buf
];
914 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
916 /* Only clear the buffers present in the provided mask */
917 if (((1 << fb
->_ColorDrawBufferIndexes
[buf
]) & mask
) == 0)
920 /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
921 * the framebuffer can be complete with some attachments missing. In
922 * this case the _ColorDrawBuffers pointer will be NULL.
927 do_single_blorp_clear(brw
, fb
, rb
, buf
, partial_clear
, encode_srgb
);
928 irb
->need_downsample
= true;
935 brw_blorp_clear_depth_stencil(struct brw_context
*brw
,
936 struct gl_framebuffer
*fb
,
937 GLbitfield mask
, bool partial_clear
)
939 const struct gl_context
*ctx
= &brw
->ctx
;
940 struct gl_renderbuffer
*depth_rb
=
941 fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
;
942 struct gl_renderbuffer
*stencil_rb
=
943 fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
945 if (!depth_rb
|| ctx
->Depth
.Mask
== GL_FALSE
)
946 mask
&= ~BUFFER_BIT_DEPTH
;
948 if (!stencil_rb
|| (ctx
->Stencil
.WriteMask
[0] & 0xff) == 0)
949 mask
&= ~BUFFER_BIT_STENCIL
;
951 if (!(mask
& (BUFFER_BITS_DEPTH_STENCIL
)))
954 uint32_t x0
, x1
, y0
, y1
, rb_name
, rb_height
;
956 rb_name
= depth_rb
->Name
;
957 rb_height
= depth_rb
->Height
;
959 assert(depth_rb
->Width
== stencil_rb
->Width
);
960 assert(depth_rb
->Height
== stencil_rb
->Height
);
964 rb_name
= stencil_rb
->Name
;
965 rb_height
= stencil_rb
->Height
;
974 y0
= rb_height
- fb
->_Ymax
;
975 y1
= rb_height
- fb
->_Ymin
;
978 /* If the clear region is empty, just return. */
979 if (x0
== x1
|| y0
== y1
)
982 uint32_t level
, start_layer
, num_layers
;
983 struct isl_surf isl_tmp
[4];
984 struct blorp_surf depth_surf
, stencil_surf
;
986 struct intel_mipmap_tree
*depth_mt
= NULL
;
987 if (mask
& BUFFER_BIT_DEPTH
) {
988 struct intel_renderbuffer
*irb
= intel_renderbuffer(depth_rb
);
989 depth_mt
= find_miptree(GL_DEPTH_BUFFER_BIT
, irb
);
991 level
= irb
->mt_level
;
992 start_layer
= irb
->mt_layer
;
993 num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
995 intel_miptree_prepare_depth(brw
, depth_mt
, level
,
996 start_layer
, num_layers
);
998 unsigned depth_level
= level
;
999 blorp_surf_for_miptree(brw
, &depth_surf
, depth_mt
, depth_mt
->aux_usage
,
1000 true, &depth_level
, start_layer
, num_layers
,
1002 assert(depth_level
== level
);
1005 uint8_t stencil_mask
= 0;
1006 struct intel_mipmap_tree
*stencil_mt
= NULL
;
1007 if (mask
& BUFFER_BIT_STENCIL
) {
1008 struct intel_renderbuffer
*irb
= intel_renderbuffer(stencil_rb
);
1009 stencil_mt
= find_miptree(GL_STENCIL_BUFFER_BIT
, irb
);
1011 if (mask
& BUFFER_BIT_DEPTH
) {
1012 assert(level
== irb
->mt_level
);
1013 assert(start_layer
== irb
->mt_layer
);
1014 assert(num_layers
== fb
->MaxNumLayers
? irb
->layer_count
: 1);
1016 level
= irb
->mt_level
;
1017 start_layer
= irb
->mt_layer
;
1018 num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1021 stencil_mask
= ctx
->Stencil
.WriteMask
[0] & 0xff;
1023 intel_miptree_prepare_access(brw
, stencil_mt
, level
, 1,
1024 start_layer
, num_layers
,
1025 ISL_AUX_USAGE_NONE
, false);
1027 unsigned stencil_level
= level
;
1028 blorp_surf_for_miptree(brw
, &stencil_surf
, stencil_mt
,
1029 ISL_AUX_USAGE_NONE
, true,
1030 &stencil_level
, start_layer
, num_layers
,
1034 assert((mask
& BUFFER_BIT_DEPTH
) || stencil_mask
);
1036 struct blorp_batch batch
;
1037 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1038 blorp_clear_depth_stencil(&batch
, &depth_surf
, &stencil_surf
,
1039 level
, start_layer
, num_layers
,
1041 (mask
& BUFFER_BIT_DEPTH
), ctx
->Depth
.Clear
,
1042 stencil_mask
, ctx
->Stencil
.Clear
);
1043 blorp_batch_finish(&batch
);
1045 if (mask
& BUFFER_BIT_DEPTH
) {
1046 intel_miptree_finish_depth(brw
, depth_mt
, level
,
1047 start_layer
, num_layers
, true);
1051 intel_miptree_finish_write(brw
, stencil_mt
, level
,
1052 start_layer
, num_layers
,
1053 ISL_AUX_USAGE_NONE
);
1058 brw_blorp_resolve_color(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1059 unsigned level
, unsigned layer
,
1060 enum blorp_fast_clear_op resolve_op
)
1062 DBG("%s to mt %p level %u layer %u\n", __FUNCTION__
, mt
, level
, layer
);
1064 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
1066 struct isl_surf isl_tmp
[1];
1067 struct blorp_surf surf
;
1068 blorp_surf_for_miptree(brw
, &surf
, mt
, mt
->aux_usage
, true,
1069 &level
, layer
, 1 /* num_layers */,
1072 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1074 * "Any transition from any value in {Clear, Render, Resolve} to a
1075 * different value in {Clear, Render, Resolve} requires end of pipe
1078 * In other words, fast clear ops are not properly synchronized with
1079 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1080 * contents of the previous draw hit the render target before we resolve
1081 * and again afterwards to ensure that the resolve is complete before we
1082 * do any more regular drawing.
1084 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1087 struct blorp_batch batch
;
1088 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1089 blorp_ccs_resolve(&batch
, &surf
, level
, layer
,
1090 brw_blorp_to_isl_format(brw
, format
, true),
1092 blorp_batch_finish(&batch
);
1094 /* See comment above */
1095 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1099 brw_blorp_mcs_partial_resolve(struct brw_context
*brw
,
1100 struct intel_mipmap_tree
*mt
,
1101 uint32_t start_layer
, uint32_t num_layers
)
1103 DBG("%s to mt %p layers %u-%u\n", __FUNCTION__
, mt
,
1104 start_layer
, start_layer
+ num_layers
- 1);
1106 assert(mt
->aux_usage
= ISL_AUX_USAGE_MCS
);
1108 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
1109 enum isl_format isl_format
= brw_blorp_to_isl_format(brw
, format
, true);
1111 struct isl_surf isl_tmp
[1];
1112 struct blorp_surf surf
;
1114 blorp_surf_for_miptree(brw
, &surf
, mt
, ISL_AUX_USAGE_MCS
, true,
1115 &level
, start_layer
, num_layers
, isl_tmp
);
1117 struct blorp_batch batch
;
1118 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1119 blorp_mcs_partial_resolve(&batch
, &surf
, isl_format
,
1120 start_layer
, num_layers
);
1121 blorp_batch_finish(&batch
);
1125 * Perform a HiZ or depth resolve operation.
1127 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
1128 * PRM, Volume 1, Part 2:
1129 * - 7.5.3.1 Depth Buffer Clear
1130 * - 7.5.3.2 Depth Buffer Resolve
1131 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1134 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1135 unsigned int level
, unsigned int start_layer
,
1136 unsigned int num_layers
, enum blorp_hiz_op op
)
1138 assert(intel_miptree_level_has_hiz(mt
, level
));
1139 assert(op
!= BLORP_HIZ_OP_NONE
);
1140 const char *opname
= NULL
;
1143 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
1144 opname
= "depth resolve";
1146 case BLORP_HIZ_OP_HIZ_RESOLVE
:
1147 opname
= "hiz ambiguate";
1149 case BLORP_HIZ_OP_DEPTH_CLEAR
:
1150 opname
= "depth clear";
1152 case BLORP_HIZ_OP_NONE
:
1157 DBG("%s %s to mt %p level %d layers %d-%d\n",
1158 __func__
, opname
, mt
, level
, start_layer
, start_layer
+ num_layers
- 1);
1160 /* The following stalls and flushes are only documented to be required for
1161 * HiZ clear operations. However, they also seem to be required for
1162 * resolve operations.
1164 if (brw
->gen
== 6) {
1165 /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
1167 * "If other rendering operations have preceded this clear, a
1168 * PIPE_CONTROL with write cache flush enabled and Z-inhibit
1169 * disabled must be issued before the rectangle primitive used for
1170 * the depth buffer clear operation.
1172 brw_emit_pipe_control_flush(brw
,
1173 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1174 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1175 PIPE_CONTROL_CS_STALL
);
1176 } else if (brw
->gen
>= 7) {
1178 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
1180 * If other rendering operations have preceded this clear, a
1181 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
1182 * enabled must be issued before the rectangle primitive used for
1183 * the depth buffer clear operation.
1185 * Same applies for Gen8 and Gen9.
1187 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
1188 * PIPE_CONTROL, Depth Cache Flush Enable:
1190 * This bit must not be set when Depth Stall Enable bit is set in
1193 * This is confirmed to hold for real, HSW gets immediate gpu hangs.
1195 * Therefore issue two pipe control flushes, one for cache flush and
1196 * another for depth stall.
1198 brw_emit_pipe_control_flush(brw
,
1199 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1200 PIPE_CONTROL_CS_STALL
);
1202 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
1205 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
&& mt
->hiz_buf
);
1207 struct isl_surf isl_tmp
[2];
1208 struct blorp_surf surf
;
1209 blorp_surf_for_miptree(brw
, &surf
, mt
, ISL_AUX_USAGE_HIZ
, true,
1210 &level
, start_layer
, num_layers
, isl_tmp
);
1212 struct blorp_batch batch
;
1213 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1214 blorp_hiz_op(&batch
, &surf
, level
, start_layer
, num_layers
, op
);
1215 blorp_batch_finish(&batch
);
1217 /* The following stalls and flushes are only documented to be required for
1218 * HiZ clear operations. However, they also seem to be required for
1219 * resolve operations.
1221 if (brw
->gen
== 6) {
1222 /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
1224 * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be
1225 * followed by a PIPE_CONTROL command with DEPTH_STALL bit set
1226 * and Then followed by Depth FLUSH'
1228 brw_emit_pipe_control_flush(brw
,
1229 PIPE_CONTROL_DEPTH_STALL
);
1231 brw_emit_pipe_control_flush(brw
,
1232 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1233 PIPE_CONTROL_CS_STALL
);
1234 } else if (brw
->gen
>= 8) {
1236 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
1238 * "Depth buffer clear pass using any of the methods (WM_STATE,
1239 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
1240 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
1241 * "set" before starting to render. DepthStall and DepthFlush are
1242 * not needed between consecutive depth clear passes nor is it
1243 * required if the depth clear pass was done with
1244 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
1246 * TODO: Such as the spec says, this could be conditional.
1248 brw_emit_pipe_control_flush(brw
,
1249 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1250 PIPE_CONTROL_DEPTH_STALL
);