2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/blend.h"
27 #include "main/bufferobj.h"
28 #include "main/enums.h"
29 #include "main/fbobject.h"
30 #include "main/image.h"
31 #include "main/renderbuffer.h"
32 #include "main/glformats.h"
34 #include "brw_blorp.h"
35 #include "brw_context.h"
36 #include "brw_defines.h"
37 #include "brw_meta_util.h"
38 #include "brw_state.h"
39 #include "intel_buffer_objects.h"
40 #include "intel_fbo.h"
41 #include "common/gen_debug.h"
43 #define FILE_DEBUG_FLAG DEBUG_BLORP
46 brw_blorp_lookup_shader(struct blorp_context
*blorp
,
47 const void *key
, uint32_t key_size
,
48 uint32_t *kernel_out
, void *prog_data_out
)
50 struct brw_context
*brw
= blorp
->driver_ctx
;
51 return brw_search_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
,
52 key
, key_size
, kernel_out
, prog_data_out
);
56 brw_blorp_upload_shader(struct blorp_context
*blorp
,
57 const void *key
, uint32_t key_size
,
58 const void *kernel
, uint32_t kernel_size
,
59 const struct brw_stage_prog_data
*prog_data
,
60 uint32_t prog_data_size
,
61 uint32_t *kernel_out
, void *prog_data_out
)
63 struct brw_context
*brw
= blorp
->driver_ctx
;
64 brw_upload_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
, key
, key_size
,
65 kernel
, kernel_size
, prog_data
, prog_data_size
,
66 kernel_out
, prog_data_out
);
71 brw_blorp_init(struct brw_context
*brw
)
73 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
75 blorp_init(&brw
->blorp
, brw
, &brw
->isl_dev
);
77 brw
->blorp
.compiler
= brw
->screen
->compiler
;
79 switch (devinfo
->gen
) {
81 if (devinfo
->is_g4x
) {
82 brw
->blorp
.exec
= gen45_blorp_exec
;
84 brw
->blorp
.exec
= gen4_blorp_exec
;
88 brw
->blorp
.exec
= gen5_blorp_exec
;
91 brw
->blorp
.exec
= gen6_blorp_exec
;
94 if (devinfo
->is_haswell
) {
95 brw
->blorp
.exec
= gen75_blorp_exec
;
97 brw
->blorp
.exec
= gen7_blorp_exec
;
101 brw
->blorp
.exec
= gen8_blorp_exec
;
104 brw
->blorp
.exec
= gen9_blorp_exec
;
107 brw
->blorp
.exec
= gen10_blorp_exec
;
110 brw
->blorp
.exec
= gen11_blorp_exec
;
114 unreachable("Invalid gen");
117 brw
->blorp
.lookup_shader
= brw_blorp_lookup_shader
;
118 brw
->blorp
.upload_shader
= brw_blorp_upload_shader
;
122 blorp_surf_for_miptree(struct brw_context
*brw
,
123 struct blorp_surf
*surf
,
124 struct intel_mipmap_tree
*mt
,
125 enum isl_aux_usage aux_usage
,
126 bool is_render_target
,
128 unsigned start_layer
, unsigned num_layers
,
129 struct isl_surf tmp_surfs
[1])
131 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
133 if (mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
) {
134 const unsigned num_samples
= mt
->surf
.samples
;
135 for (unsigned i
= 0; i
< num_layers
; i
++) {
136 for (unsigned s
= 0; s
< num_samples
; s
++) {
137 const unsigned phys_layer
= (start_layer
+ i
) * num_samples
+ s
;
138 intel_miptree_check_level_layer(mt
, *level
, phys_layer
);
142 for (unsigned i
= 0; i
< num_layers
; i
++)
143 intel_miptree_check_level_layer(mt
, *level
, start_layer
+ i
);
146 *surf
= (struct blorp_surf
) {
148 .addr
= (struct blorp_address
) {
150 .offset
= mt
->offset
,
151 .reloc_flags
= is_render_target
? EXEC_OBJECT_WRITE
: 0,
152 .mocs
= brw_get_bo_mocs(devinfo
, mt
->bo
),
154 .aux_usage
= aux_usage
,
155 .tile_x_sa
= mt
->level
[*level
].level_x
,
156 .tile_y_sa
= mt
->level
[*level
].level_y
,
159 if (mt
->format
== MESA_FORMAT_S_UINT8
&& is_render_target
&&
161 mt
->r8stencil_needs_update
= true;
163 if (surf
->aux_usage
== ISL_AUX_USAGE_HIZ
&&
164 !intel_miptree_level_has_hiz(mt
, *level
))
165 surf
->aux_usage
= ISL_AUX_USAGE_NONE
;
167 if (surf
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
168 /* We only really need a clear color if we also have an auxiliary
169 * surface. Without one, it does nothing.
172 intel_miptree_get_clear_color(devinfo
, mt
, mt
->surf
.format
,
173 !is_render_target
, (struct brw_bo
**)
174 &surf
->clear_color_addr
.buffer
,
175 &surf
->clear_color_addr
.offset
);
177 surf
->aux_surf
= &mt
->aux_buf
->surf
;
178 surf
->aux_addr
= (struct blorp_address
) {
179 .reloc_flags
= is_render_target
? EXEC_OBJECT_WRITE
: 0,
180 .mocs
= surf
->addr
.mocs
,
183 surf
->aux_addr
.buffer
= mt
->aux_buf
->bo
;
184 surf
->aux_addr
.offset
= mt
->aux_buf
->offset
;
186 surf
->aux_addr
= (struct blorp_address
) {
189 memset(&surf
->clear_color
, 0, sizeof(surf
->clear_color
));
191 assert((surf
->aux_usage
== ISL_AUX_USAGE_NONE
) ==
192 (surf
->aux_addr
.buffer
== NULL
));
194 /* ISL wants real levels, not offset ones. */
195 *level
-= mt
->first_level
;
199 brw_blorp_supports_dst_format(struct brw_context
*brw
, mesa_format format
)
201 /* If it's renderable, it's definitely supported. */
202 if (brw
->mesa_format_supports_render
[format
])
205 /* BLORP can't compress anything */
206 if (_mesa_is_format_compressed(format
))
209 /* No exotic formats such as GL_LUMINANCE_ALPHA */
210 if (_mesa_get_format_bits(format
, GL_RED_BITS
) == 0 &&
211 _mesa_get_format_bits(format
, GL_DEPTH_BITS
) == 0 &&
212 _mesa_get_format_bits(format
, GL_STENCIL_BITS
) == 0)
218 static enum isl_format
219 brw_blorp_to_isl_format(struct brw_context
*brw
, mesa_format format
,
220 bool is_render_target
)
223 case MESA_FORMAT_NONE
:
224 return ISL_FORMAT_UNSUPPORTED
;
225 case MESA_FORMAT_S_UINT8
:
226 return ISL_FORMAT_R8_UINT
;
227 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
228 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
229 return ISL_FORMAT_R24_UNORM_X8_TYPELESS
;
230 case MESA_FORMAT_Z_FLOAT32
:
231 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
232 return ISL_FORMAT_R32_FLOAT
;
233 case MESA_FORMAT_Z_UNORM16
:
234 return ISL_FORMAT_R16_UNORM
;
236 if (is_render_target
) {
237 assert(brw_blorp_supports_dst_format(brw
, format
));
238 if (brw
->mesa_format_supports_render
[format
]) {
239 return brw
->mesa_to_isl_render_format
[format
];
241 return brw_isl_format_for_mesa_format(format
);
244 /* Some destinations (is_render_target == true) are supported by
245 * blorp even though we technically can't render to them.
247 return brw_isl_format_for_mesa_format(format
);
253 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
254 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
256 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
259 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
261 * which is simply adding 4 then modding by 8 (or anding with 7).
263 * We then may need to apply workarounds for textureGather hardware bugs.
265 static enum isl_channel_select
266 swizzle_to_scs(GLenum swizzle
)
268 return (enum isl_channel_select
)((swizzle
+ 4) & 7);
272 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
273 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
274 * the physical layer holding sample 0. So, for example, if
275 * src_mt->surf.samples == 4, then logical layer n corresponds to src_layer ==
279 brw_blorp_blit_miptrees(struct brw_context
*brw
,
280 struct intel_mipmap_tree
*src_mt
,
281 unsigned src_level
, unsigned src_layer
,
282 mesa_format src_format
, int src_swizzle
,
283 struct intel_mipmap_tree
*dst_mt
,
284 unsigned dst_level
, unsigned dst_layer
,
285 mesa_format dst_format
,
286 float src_x0
, float src_y0
,
287 float src_x1
, float src_y1
,
288 float dst_x0
, float dst_y0
,
289 float dst_x1
, float dst_y1
,
290 GLenum filter
, bool mirror_x
, bool mirror_y
,
291 bool decode_srgb
, bool encode_srgb
)
293 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
295 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f) "
296 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
298 src_mt
->surf
.samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
299 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
300 dst_mt
->surf
.samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
301 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
304 if (!decode_srgb
&& _mesa_get_format_color_encoding(src_format
) == GL_SRGB
)
305 src_format
= _mesa_get_srgb_format_linear(src_format
);
307 if (!encode_srgb
&& _mesa_get_format_color_encoding(dst_format
) == GL_SRGB
)
308 dst_format
= _mesa_get_srgb_format_linear(dst_format
);
310 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
311 * texture, the above code configures the source format for L32_FLOAT or
312 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
313 * the SAMPLE message appears to handle multisampled L32_FLOAT and
314 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
315 * around the problem by using a source format of R32_FLOAT. This
316 * shouldn't affect rendering correctness, since the destination format is
317 * R32_FLOAT, so only the contents of the red channel matters.
319 if (devinfo
->gen
== 6 &&
320 src_mt
->surf
.samples
> 1 && dst_mt
->surf
.samples
<= 1 &&
321 src_mt
->format
== dst_mt
->format
&&
322 (dst_format
== MESA_FORMAT_L_FLOAT32
||
323 dst_format
== MESA_FORMAT_I_FLOAT32
)) {
324 src_format
= dst_format
= MESA_FORMAT_R_FLOAT32
;
327 enum isl_format src_isl_format
=
328 brw_blorp_to_isl_format(brw
, src_format
, false);
329 enum isl_aux_usage src_aux_usage
=
330 intel_miptree_texture_aux_usage(brw
, src_mt
, src_isl_format
);
331 /* We do format workarounds for some depth formats so we can't reliably
332 * sample with HiZ. One of these days, we should fix that.
334 if (src_aux_usage
== ISL_AUX_USAGE_HIZ
)
335 src_aux_usage
= ISL_AUX_USAGE_NONE
;
336 const bool src_clear_supported
=
337 src_aux_usage
!= ISL_AUX_USAGE_NONE
&& src_mt
->format
== src_format
;
338 intel_miptree_prepare_access(brw
, src_mt
, src_level
, 1, src_layer
, 1,
339 src_aux_usage
, src_clear_supported
);
341 enum isl_format dst_isl_format
=
342 brw_blorp_to_isl_format(brw
, dst_format
, true);
343 enum isl_aux_usage dst_aux_usage
=
344 intel_miptree_render_aux_usage(brw
, dst_mt
, dst_isl_format
,
346 const bool dst_clear_supported
= dst_aux_usage
!= ISL_AUX_USAGE_NONE
;
347 intel_miptree_prepare_access(brw
, dst_mt
, dst_level
, 1, dst_layer
, 1,
348 dst_aux_usage
, dst_clear_supported
);
350 struct isl_surf tmp_surfs
[2];
351 struct blorp_surf src_surf
, dst_surf
;
352 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, src_aux_usage
, false,
353 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
354 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, dst_aux_usage
, true,
355 &dst_level
, dst_layer
, 1, &tmp_surfs
[1]);
357 struct isl_swizzle src_isl_swizzle
= {
358 .r
= swizzle_to_scs(GET_SWZ(src_swizzle
, 0)),
359 .g
= swizzle_to_scs(GET_SWZ(src_swizzle
, 1)),
360 .b
= swizzle_to_scs(GET_SWZ(src_swizzle
, 2)),
361 .a
= swizzle_to_scs(GET_SWZ(src_swizzle
, 3)),
364 struct blorp_batch batch
;
365 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
366 blorp_blit(&batch
, &src_surf
, src_level
, src_layer
,
367 src_isl_format
, src_isl_swizzle
,
368 &dst_surf
, dst_level
, dst_layer
,
369 dst_isl_format
, ISL_SWIZZLE_IDENTITY
,
370 src_x0
, src_y0
, src_x1
, src_y1
,
371 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
372 filter
, mirror_x
, mirror_y
);
373 blorp_batch_finish(&batch
);
375 intel_miptree_finish_write(brw
, dst_mt
, dst_level
, dst_layer
, 1,
380 brw_blorp_copy_miptrees(struct brw_context
*brw
,
381 struct intel_mipmap_tree
*src_mt
,
382 unsigned src_level
, unsigned src_layer
,
383 struct intel_mipmap_tree
*dst_mt
,
384 unsigned dst_level
, unsigned dst_layer
,
385 unsigned src_x
, unsigned src_y
,
386 unsigned dst_x
, unsigned dst_y
,
387 unsigned src_width
, unsigned src_height
)
389 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
391 DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
392 "to %dx %s mt %p %d %d (%d,%d)\n",
394 src_mt
->surf
.samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
395 src_level
, src_layer
, src_x
, src_y
, src_width
, src_height
,
396 dst_mt
->surf
.samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
397 dst_level
, dst_layer
, dst_x
, dst_y
);
399 enum isl_aux_usage src_aux_usage
, dst_aux_usage
;
400 bool src_clear_supported
, dst_clear_supported
;
402 switch (src_mt
->aux_usage
) {
403 case ISL_AUX_USAGE_MCS
:
404 case ISL_AUX_USAGE_CCS_E
:
405 src_aux_usage
= src_mt
->aux_usage
;
406 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
407 * we're going to re-interpret the format as an integer format possibly
408 * with a different number of components, we can't handle clear colors
411 src_clear_supported
= devinfo
->gen
>= 9;
414 src_aux_usage
= ISL_AUX_USAGE_NONE
;
415 src_clear_supported
= false;
419 switch (dst_mt
->aux_usage
) {
420 case ISL_AUX_USAGE_MCS
:
421 case ISL_AUX_USAGE_CCS_E
:
422 dst_aux_usage
= dst_mt
->aux_usage
;
423 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
424 * we're going to re-interpret the format as an integer format possibly
425 * with a different number of components, we can't handle clear colors
428 dst_clear_supported
= devinfo
->gen
>= 9;
431 dst_aux_usage
= ISL_AUX_USAGE_NONE
;
432 dst_clear_supported
= false;
436 intel_miptree_prepare_access(brw
, src_mt
, src_level
, 1, src_layer
, 1,
437 src_aux_usage
, src_clear_supported
);
438 intel_miptree_prepare_access(brw
, dst_mt
, dst_level
, 1, dst_layer
, 1,
439 dst_aux_usage
, dst_clear_supported
);
441 struct isl_surf tmp_surfs
[2];
442 struct blorp_surf src_surf
, dst_surf
;
443 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, src_aux_usage
, false,
444 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
445 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, dst_aux_usage
, true,
446 &dst_level
, dst_layer
, 1, &tmp_surfs
[1]);
448 /* The hardware seems to have issues with having a two different format
449 * views of the same texture in the sampler cache at the same time. It's
450 * unclear exactly what the issue is but it hurts glCopyImageSubData
451 * particularly badly because it does a lot of format reinterprets. We
452 * badly need better understanding of the issue and a better fix but this
453 * works for now and fixes CTS tests.
455 * TODO: Remove this hack!
457 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
|
458 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
460 struct blorp_batch batch
;
461 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
462 blorp_copy(&batch
, &src_surf
, src_level
, src_layer
,
463 &dst_surf
, dst_level
, dst_layer
,
464 src_x
, src_y
, dst_x
, dst_y
, src_width
, src_height
);
465 blorp_batch_finish(&batch
);
467 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
|
468 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
470 intel_miptree_finish_write(brw
, dst_mt
, dst_level
, dst_layer
, 1,
475 brw_blorp_copy_buffers(struct brw_context
*brw
,
476 struct brw_bo
*src_bo
,
478 struct brw_bo
*dst_bo
,
482 DBG("%s %d bytes from %p[%d] to %p[%d]",
483 __func__
, size
, src_bo
, src_offset
, dst_bo
, dst_offset
);
485 struct blorp_batch batch
;
486 struct blorp_address src
= { .buffer
= src_bo
, .offset
= src_offset
};
487 struct blorp_address dst
= { .buffer
= dst_bo
, .offset
= dst_offset
};
489 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
490 blorp_buffer_copy(&batch
, src
, dst
, size
);
491 blorp_batch_finish(&batch
);
495 static struct intel_mipmap_tree
*
496 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
498 struct intel_mipmap_tree
*mt
= irb
->mt
;
499 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
505 blorp_get_texture_swizzle(const struct intel_renderbuffer
*irb
)
507 return irb
->Base
.Base
._BaseFormat
== GL_RGB
?
508 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ONE
) :
513 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
514 struct intel_renderbuffer
*src_irb
, mesa_format src_format
,
515 struct intel_renderbuffer
*dst_irb
, mesa_format dst_format
,
516 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
517 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
518 GLenum filter
, bool mirror_x
, bool mirror_y
)
520 const struct gl_context
*ctx
= &brw
->ctx
;
522 /* Find source/dst miptrees */
523 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
524 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
526 const bool do_srgb
= ctx
->Color
.sRGBEnabled
;
529 brw_blorp_blit_miptrees(brw
,
530 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
531 src_format
, blorp_get_texture_swizzle(src_irb
),
532 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
534 srcX0
, srcY0
, srcX1
, srcY1
,
535 dstX0
, dstY0
, dstX1
, dstY1
,
536 filter
, mirror_x
, mirror_y
,
539 dst_irb
->need_downsample
= true;
543 try_blorp_blit(struct brw_context
*brw
,
544 const struct gl_framebuffer
*read_fb
,
545 const struct gl_framebuffer
*draw_fb
,
546 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
547 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
548 GLenum filter
, GLbitfield buffer_bit
)
550 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
551 struct gl_context
*ctx
= &brw
->ctx
;
553 /* Sync up the state of window system buffers. We need to do this before
554 * we go looking for the buffers.
556 intel_prepare_render(brw
);
558 bool mirror_x
, mirror_y
;
559 if (brw_meta_mirror_clip_and_scissor(ctx
, read_fb
, draw_fb
,
560 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
561 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
562 &mirror_x
, &mirror_y
))
566 struct intel_renderbuffer
*src_irb
;
567 struct intel_renderbuffer
*dst_irb
;
568 struct intel_mipmap_tree
*src_mt
;
569 struct intel_mipmap_tree
*dst_mt
;
570 switch (buffer_bit
) {
571 case GL_COLOR_BUFFER_BIT
:
572 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
573 for (unsigned i
= 0; i
< draw_fb
->_NumColorDrawBuffers
; ++i
) {
574 dst_irb
= intel_renderbuffer(draw_fb
->_ColorDrawBuffers
[i
]);
576 do_blorp_blit(brw
, buffer_bit
,
577 src_irb
, src_irb
->Base
.Base
.Format
,
578 dst_irb
, dst_irb
->Base
.Base
.Format
,
579 srcX0
, srcY0
, srcX1
, srcY1
,
580 dstX0
, dstY0
, dstX1
, dstY1
,
581 filter
, mirror_x
, mirror_y
);
584 case GL_DEPTH_BUFFER_BIT
:
586 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
588 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
589 src_mt
= find_miptree(buffer_bit
, src_irb
);
590 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
592 /* We also can't handle any combined depth-stencil formats because we
593 * have to reinterpret as a color format.
595 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
596 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
599 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
600 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
601 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
602 filter
, mirror_x
, mirror_y
);
604 case GL_STENCIL_BUFFER_BIT
:
605 /* Blorp doesn't support combined depth stencil which is all we have
608 if (devinfo
->gen
< 6)
612 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
614 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
615 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
616 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
617 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
618 filter
, mirror_x
, mirror_y
);
621 unreachable("not reached");
628 apply_y_flip(int *y0
, int *y1
, int height
)
630 int tmp
= height
- *y0
;
636 brw_blorp_copytexsubimage(struct brw_context
*brw
,
637 struct gl_renderbuffer
*src_rb
,
638 struct gl_texture_image
*dst_image
,
640 int srcX0
, int srcY0
,
641 int dstX0
, int dstY0
,
642 int width
, int height
)
644 struct gl_context
*ctx
= &brw
->ctx
;
645 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
646 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
648 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
649 if (brw
->ctx
._ImageTransferState
)
652 /* Sync up the state of window system buffers. We need to do this before
653 * we go looking at the src renderbuffer's miptree.
655 intel_prepare_render(brw
);
657 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
658 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
660 /* We can't handle any combined depth-stencil formats because we have to
661 * reinterpret as a color format.
663 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
664 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
667 if (!brw_blorp_supports_dst_format(brw
, dst_image
->TexFormat
))
670 /* Source clipping shouldn't be necessary, since copytexsubimage (in
671 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
674 * Destination clipping shouldn't be necessary since the restrictions on
675 * glCopyTexSubImage prevent the user from specifying a destination rectangle
676 * that falls outside the bounds of the destination texture.
677 * See error_check_subtexture_dimensions().
680 int srcY1
= srcY0
+ height
;
681 int srcX1
= srcX0
+ width
;
682 int dstX1
= dstX0
+ width
;
683 int dstY1
= dstY0
+ height
;
685 /* Account for the fact that in the system framebuffer, the origin is at
688 bool mirror_y
= _mesa_is_winsys_fbo(ctx
->ReadBuffer
);
690 apply_y_flip(&srcY0
, &srcY1
, src_rb
->Height
);
692 /* Account for face selection and texture view MinLayer */
693 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
694 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
696 brw_blorp_blit_miptrees(brw
,
697 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
698 src_rb
->Format
, blorp_get_texture_swizzle(src_irb
),
699 dst_mt
, dst_level
, dst_slice
,
700 dst_image
->TexFormat
,
701 srcX0
, srcY0
, srcX1
, srcY1
,
702 dstX0
, dstY0
, dstX1
, dstY1
,
703 GL_NEAREST
, false, mirror_y
,
706 /* If we're copying to a packed depth stencil texture and the source
707 * framebuffer has separate stencil, we need to also copy the stencil data
710 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
711 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
713 src_irb
= intel_renderbuffer(src_rb
);
714 src_mt
= src_irb
->mt
;
716 if (src_mt
->stencil_mt
)
717 src_mt
= src_mt
->stencil_mt
;
718 if (dst_mt
->stencil_mt
)
719 dst_mt
= dst_mt
->stencil_mt
;
721 if (src_mt
!= dst_mt
) {
722 brw_blorp_blit_miptrees(brw
,
723 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
725 blorp_get_texture_swizzle(src_irb
),
726 dst_mt
, dst_level
, dst_slice
,
728 srcX0
, srcY0
, srcX1
, srcY1
,
729 dstX0
, dstY0
, dstX1
, dstY1
,
730 GL_NEAREST
, false, mirror_y
,
740 brw_blorp_framebuffer(struct brw_context
*brw
,
741 struct gl_framebuffer
*readFb
,
742 struct gl_framebuffer
*drawFb
,
743 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
744 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
745 GLbitfield mask
, GLenum filter
)
747 static GLbitfield buffer_bits
[] = {
750 GL_STENCIL_BUFFER_BIT
,
753 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
754 if ((mask
& buffer_bits
[i
]) &&
755 try_blorp_blit(brw
, readFb
, drawFb
,
756 srcX0
, srcY0
, srcX1
, srcY1
,
757 dstX0
, dstY0
, dstX1
, dstY1
,
758 filter
, buffer_bits
[i
])) {
759 mask
&= ~buffer_bits
[i
];
766 static struct brw_bo
*
767 blorp_get_client_bo(struct brw_context
*brw
,
768 unsigned w
, unsigned h
, unsigned d
,
769 GLenum target
, GLenum format
, GLenum type
,
771 const struct gl_pixelstore_attrib
*packing
,
772 uint32_t *offset_out
, uint32_t *row_stride_out
,
773 uint32_t *image_stride_out
, bool read_only
)
775 /* Account for SKIP_PIXELS, SKIP_ROWS, ALIGNMENT, and SKIP_IMAGES */
776 const GLuint dims
= _mesa_get_texture_dimensions(target
);
777 const uint32_t first_pixel
= _mesa_image_offset(dims
, packing
, w
, h
,
778 format
, type
, 0, 0, 0);
779 const uint32_t last_pixel
= _mesa_image_offset(dims
, packing
, w
, h
,
782 const uint32_t stride
= _mesa_image_row_stride(packing
, w
, format
, type
);
783 const uint32_t cpp
= _mesa_bytes_per_pixel(format
, type
);
784 const uint32_t size
= last_pixel
- first_pixel
;
786 *row_stride_out
= stride
;
787 *image_stride_out
= _mesa_image_image_stride(packing
, w
, h
, format
, type
);
789 if (_mesa_is_bufferobj(packing
->BufferObj
)) {
790 const uint32_t offset
= first_pixel
+ (intptr_t)pixels
;
791 if (!read_only
&& ((offset
% cpp
) || (stride
% cpp
))) {
792 perf_debug("Bad PBO alignment; fallback to CPU mapping\n");
796 /* This is a user-provided PBO. We just need to get the BO out */
797 struct intel_buffer_object
*intel_pbo
=
798 intel_buffer_object(packing
->BufferObj
);
800 intel_bufferobj_buffer(brw
, intel_pbo
, offset
, size
, !read_only
);
802 /* We take a reference to the BO so that the caller can just always
803 * unref without having to worry about whether it's a user PBO or one
806 brw_bo_reference(bo
);
808 *offset_out
= offset
;
811 /* Someone should have already checked that there is data to upload. */
814 /* Creating a temp buffer currently only works for upload */
817 /* This is not a user-provided PBO. Instead, pixels is a pointer to CPU
818 * data which we need to copy into a BO.
821 brw_bo_alloc(brw
->bufmgr
, "tmp_tex_subimage_src", size
,
824 perf_debug("intel_texsubimage: temp bo creation failed: size = %u\n",
829 if (brw_bo_subdata(bo
, 0, size
, pixels
+ first_pixel
)) {
830 perf_debug("intel_texsubimage: temp bo upload failed\n");
831 brw_bo_unreference(bo
);
840 /* Consider all the restrictions and determine the format of the source. */
842 blorp_get_client_format(struct brw_context
*brw
,
843 GLenum format
, GLenum type
,
844 const struct gl_pixelstore_attrib
*packing
)
846 if (brw
->ctx
._ImageTransferState
)
847 return MESA_FORMAT_NONE
;
849 if (packing
->SwapBytes
|| packing
->LsbFirst
|| packing
->Invert
) {
850 perf_debug("intel_texsubimage_blorp: unsupported gl_pixelstore_attrib\n");
851 return MESA_FORMAT_NONE
;
854 if (format
!= GL_RED
&&
860 format
!= GL_ALPHA
&&
861 format
!= GL_RED_INTEGER
&&
862 format
!= GL_RG_INTEGER
&&
863 format
!= GL_RGB_INTEGER
&&
864 format
!= GL_BGR_INTEGER
&&
865 format
!= GL_RGBA_INTEGER
&&
866 format
!= GL_BGRA_INTEGER
) {
867 perf_debug("intel_texsubimage_blorp: %s not supported",
868 _mesa_enum_to_string(format
));
869 return MESA_FORMAT_NONE
;
872 return _mesa_tex_format_from_format_and_type(&brw
->ctx
, format
, type
);
876 need_signed_unsigned_int_conversion(mesa_format src_format
,
877 mesa_format dst_format
)
879 const GLenum src_type
= _mesa_get_format_datatype(src_format
);
880 const GLenum dst_type
= _mesa_get_format_datatype(dst_format
);
881 return (src_type
== GL_INT
&& dst_type
== GL_UNSIGNED_INT
) ||
882 (src_type
== GL_UNSIGNED_INT
&& dst_type
== GL_INT
);
886 brw_blorp_upload_miptree(struct brw_context
*brw
,
887 struct intel_mipmap_tree
*dst_mt
,
888 mesa_format dst_format
,
889 uint32_t level
, uint32_t x
, uint32_t y
, uint32_t z
,
890 uint32_t width
, uint32_t height
, uint32_t depth
,
891 GLenum target
, GLenum format
, GLenum type
,
893 const struct gl_pixelstore_attrib
*packing
)
895 const mesa_format src_format
=
896 blorp_get_client_format(brw
, format
, type
, packing
);
897 if (src_format
== MESA_FORMAT_NONE
)
900 if (!brw
->mesa_format_supports_render
[dst_format
]) {
901 perf_debug("intel_texsubimage: can't use %s as render target\n",
902 _mesa_get_format_name(dst_format
));
906 /* This function relies on blorp_blit to upload the pixel data to the
907 * miptree. But, blorp_blit doesn't support signed to unsigned or
908 * unsigned to signed integer conversions.
910 if (need_signed_unsigned_int_conversion(src_format
, dst_format
))
913 uint32_t src_offset
, src_row_stride
, src_image_stride
;
914 struct brw_bo
*src_bo
=
915 blorp_get_client_bo(brw
, width
, height
, depth
,
916 target
, format
, type
, pixels
, packing
,
917 &src_offset
, &src_row_stride
,
918 &src_image_stride
, true);
922 /* Now that source is offset to correct starting point, adjust the
923 * given dimensions to treat 1D arrays as 2D.
925 if (target
== GL_TEXTURE_1D_ARRAY
) {
932 src_image_stride
= src_row_stride
;
935 intel_miptree_check_level_layer(dst_mt
, level
, z
+ depth
- 1);
939 /* Blit slice-by-slice creating a single-slice miptree for each layer. Even
940 * in case of linear buffers hardware wants image arrays to be aligned by
941 * four rows. This way hardware only gets one image at a time and any
942 * source alignment will do.
944 for (unsigned i
= 0; i
< depth
; ++i
) {
945 struct intel_mipmap_tree
*src_mt
= intel_miptree_create_for_bo(
946 brw
, src_bo
, src_format
,
947 src_offset
+ i
* src_image_stride
,
950 ISL_TILING_LINEAR
, 0);
953 perf_debug("intel_texsubimage: miptree creation for src failed\n");
957 /* In case exact match is needed, copy using equivalent UINT formats
958 * preventing hardware from changing presentation for SNORM -1.
960 if (src_mt
->format
== dst_format
) {
961 brw_blorp_copy_miptrees(brw
, src_mt
, 0, 0,
962 dst_mt
, level
, z
+ i
,
963 0, 0, x
, y
, width
, height
);
965 brw_blorp_blit_miptrees(brw
, src_mt
, 0, 0,
966 src_format
, SWIZZLE_XYZW
,
967 dst_mt
, level
, z
+ i
,
970 x
, y
, x
+ width
, y
+ height
,
971 GL_NEAREST
, false, false, false, false);
974 intel_miptree_release(&src_mt
);
980 brw_bo_unreference(src_bo
);
986 brw_blorp_download_miptree(struct brw_context
*brw
,
987 struct intel_mipmap_tree
*src_mt
,
988 mesa_format src_format
, uint32_t src_swizzle
,
989 uint32_t level
, uint32_t x
, uint32_t y
, uint32_t z
,
990 uint32_t width
, uint32_t height
, uint32_t depth
,
991 GLenum target
, GLenum format
, GLenum type
,
992 bool y_flip
, const void *pixels
,
993 const struct gl_pixelstore_attrib
*packing
)
995 const mesa_format dst_format
=
996 blorp_get_client_format(brw
, format
, type
, packing
);
997 if (dst_format
== MESA_FORMAT_NONE
)
1000 if (!brw
->mesa_format_supports_render
[dst_format
]) {
1001 perf_debug("intel_texsubimage: can't use %s as render target\n",
1002 _mesa_get_format_name(dst_format
));
1006 /* This function relies on blorp_blit to download the pixel data from the
1007 * miptree. But, blorp_blit doesn't support signed to unsigned or unsigned
1008 * to signed integer conversions.
1010 if (need_signed_unsigned_int_conversion(src_format
, dst_format
))
1013 /* We can't fetch from LUMINANCE or intensity as that would require a
1014 * non-trivial swizzle.
1016 switch (_mesa_get_format_base_format(src_format
)) {
1018 case GL_LUMINANCE_ALPHA
:
1025 /* This pass only works for PBOs */
1026 assert(_mesa_is_bufferobj(packing
->BufferObj
));
1028 uint32_t dst_offset
, dst_row_stride
, dst_image_stride
;
1029 struct brw_bo
*dst_bo
=
1030 blorp_get_client_bo(brw
, width
, height
, depth
,
1031 target
, format
, type
, pixels
, packing
,
1032 &dst_offset
, &dst_row_stride
,
1033 &dst_image_stride
, false);
1037 /* Now that source is offset to correct starting point, adjust the
1038 * given dimensions to treat 1D arrays as 2D.
1040 if (target
== GL_TEXTURE_1D_ARRAY
) {
1047 dst_image_stride
= dst_row_stride
;
1050 intel_miptree_check_level_layer(src_mt
, level
, z
+ depth
- 1);
1053 int y1
= y
+ height
;
1055 apply_y_flip(&y0
, &y1
, minify(src_mt
->surf
.phys_level0_sa
.height
,
1056 level
- src_mt
->first_level
));
1059 bool result
= false;
1061 /* Blit slice-by-slice creating a single-slice miptree for each layer. Even
1062 * in case of linear buffers hardware wants image arrays to be aligned by
1063 * four rows. This way hardware only gets one image at a time and any
1064 * source alignment will do.
1066 for (unsigned i
= 0; i
< depth
; ++i
) {
1067 struct intel_mipmap_tree
*dst_mt
= intel_miptree_create_for_bo(
1068 brw
, dst_bo
, dst_format
,
1069 dst_offset
+ i
* dst_image_stride
,
1072 ISL_TILING_LINEAR
, 0);
1075 perf_debug("intel_texsubimage: miptree creation for src failed\n");
1079 /* In case exact match is needed, copy using equivalent UINT formats
1080 * preventing hardware from changing presentation for SNORM -1.
1082 if (dst_mt
->format
== src_format
&& !y_flip
&&
1083 src_swizzle
== SWIZZLE_XYZW
) {
1084 brw_blorp_copy_miptrees(brw
, src_mt
, level
, z
+ i
,
1086 x
, y
, 0, 0, width
, height
);
1088 brw_blorp_blit_miptrees(brw
, src_mt
, level
, z
+ i
,
1089 src_format
, src_swizzle
,
1090 dst_mt
, 0, 0, dst_format
,
1091 x
, y0
, x
+ width
, y1
,
1092 0, 0, width
, height
,
1093 GL_NEAREST
, false, y_flip
, false, false);
1096 intel_miptree_release(&dst_mt
);
1101 /* As we implement PBO transfers by binding the user-provided BO as a
1102 * fake framebuffer and rendering to it. This breaks the invariant of the
1103 * GL that nothing is able to render to a BO, causing nondeterministic
1104 * corruption issues because the render cache is not coherent with a
1105 * number of other caches that the BO could potentially be bound to
1108 * This could be solved in the same way that we guarantee texture
1109 * coherency after a texture is attached to a framebuffer and
1110 * rendered to, but that would involve checking *all* BOs bound to
1111 * the pipeline for the case we need to emit a cache flush due to
1112 * previous rendering to any of them -- Including vertex, index,
1113 * uniform, atomic counter, shader image, transform feedback,
1114 * indirect draw buffers, etc.
1116 * That would increase the per-draw call overhead even though it's
1117 * very unlikely that any of the BOs bound to the pipeline has been
1118 * rendered to via a PBO at any point, so it seems better to just
1119 * flush here unconditionally.
1121 brw_emit_mi_flush(brw
);
1124 brw_bo_unreference(dst_bo
);
1130 set_write_disables(const struct intel_renderbuffer
*irb
,
1131 const unsigned color_mask
, bool *color_write_disable
)
1133 /* Format information in the renderbuffer represents the requirements
1134 * given by the client. There are cases where the backing miptree uses,
1135 * for example, RGBA to represent RGBX. Since the client is only expecting
1136 * RGB we can treat alpha as not used and write whatever we like into it.
1138 const GLenum base_format
= irb
->Base
.Base
._BaseFormat
;
1139 const int components
= _mesa_base_format_component_count(base_format
);
1140 bool disables
= false;
1142 assert(components
> 0);
1144 for (int i
= 0; i
< components
; i
++) {
1145 color_write_disable
[i
] = !(color_mask
& (1 << i
));
1146 disables
= disables
|| color_write_disable
[i
];
1153 do_single_blorp_clear(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
1154 struct gl_renderbuffer
*rb
, unsigned buf
,
1155 bool partial_clear
, bool encode_srgb
)
1157 struct gl_context
*ctx
= &brw
->ctx
;
1158 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
1159 uint32_t x0
, x1
, y0
, y1
;
1161 mesa_format format
= irb
->Base
.Base
.Format
;
1162 if (!encode_srgb
&& _mesa_get_format_color_encoding(format
) == GL_SRGB
)
1163 format
= _mesa_get_srgb_format_linear(format
);
1164 enum isl_format isl_format
= brw
->mesa_to_isl_render_format
[format
];
1168 if (rb
->Name
!= 0) {
1172 y0
= rb
->Height
- fb
->_Ymax
;
1173 y1
= rb
->Height
- fb
->_Ymin
;
1176 /* If the clear region is empty, just return. */
1177 if (x0
== x1
|| y0
== y1
)
1180 bool can_fast_clear
= !partial_clear
;
1182 bool color_write_disable
[4] = { false, false, false, false };
1183 if (set_write_disables(irb
, GET_COLORMASK(ctx
->Color
.ColorMask
, buf
),
1184 color_write_disable
))
1185 can_fast_clear
= false;
1187 /* We store clear colors as floats or uints as needed. If there are
1188 * texture views in play, the formats will not properly be respected
1189 * during resolves because the resolve operations only know about the
1190 * miptree and not the renderbuffer.
1192 if (irb
->Base
.Base
.Format
!= irb
->mt
->format
)
1193 can_fast_clear
= false;
1195 if (!irb
->mt
->supports_fast_clear
||
1196 !brw_is_color_fast_clear_compatible(brw
, irb
->mt
, &ctx
->Color
.ClearColor
))
1197 can_fast_clear
= false;
1199 /* Surface state can only record one fast clear color value. Therefore
1200 * unless different levels/layers agree on the color it can be used to
1201 * represent only single level/layer. Here it will be reserved for the
1202 * first slice (level 0, layer 0).
1204 if (irb
->layer_count
> 1 || irb
->mt_level
|| irb
->mt_layer
)
1205 can_fast_clear
= false;
1207 unsigned level
= irb
->mt_level
;
1208 const unsigned num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1210 /* If the MCS buffer hasn't been allocated yet, we need to allocate it now.
1212 if (can_fast_clear
&& !irb
->mt
->aux_buf
) {
1213 assert(irb
->mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1214 if (!intel_miptree_alloc_aux(brw
, irb
->mt
)) {
1215 /* We're out of memory. Fall back to a non-fast clear. */
1216 can_fast_clear
= false;
1220 /* FINISHME: Debug and enable fast clears */
1221 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1222 if (devinfo
->gen
>= 11)
1223 can_fast_clear
= false;
1225 if (can_fast_clear
) {
1226 const enum isl_aux_state aux_state
=
1227 intel_miptree_get_aux_state(irb
->mt
, irb
->mt_level
, irb
->mt_layer
);
1228 union isl_color_value clear_color
=
1229 brw_meta_convert_fast_clear_color(brw
, irb
->mt
,
1230 &ctx
->Color
.ClearColor
);
1232 intel_miptree_set_clear_color(brw
, irb
->mt
, clear_color
);
1234 /* If the buffer is already in ISL_AUX_STATE_CLEAR, the clear
1235 * is redundant and can be skipped.
1237 if (aux_state
== ISL_AUX_STATE_CLEAR
)
1240 DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__
,
1241 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
1243 /* We can't setup the blorp_surf until we've allocated the MCS above */
1244 struct isl_surf isl_tmp
[2];
1245 struct blorp_surf surf
;
1246 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, irb
->mt
->aux_usage
, true,
1247 &level
, irb
->mt_layer
, num_layers
, isl_tmp
);
1249 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1251 * "Any transition from any value in {Clear, Render, Resolve} to a
1252 * different value in {Clear, Render, Resolve} requires end of pipe
1255 * In other words, fast clear ops are not properly synchronized with
1256 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1257 * contents of the previous draw hit the render target before we resolve
1258 * and again afterwards to ensure that the resolve is complete before we
1259 * do any more regular drawing.
1261 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1263 struct blorp_batch batch
;
1264 blorp_batch_init(&brw
->blorp
, &batch
, brw
,
1265 BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
);
1266 blorp_fast_clear(&batch
, &surf
, isl_format
,
1267 level
, irb
->mt_layer
, num_layers
,
1269 blorp_batch_finish(&batch
);
1271 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1273 /* Now that the fast clear has occurred, put the buffer in
1274 * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
1277 intel_miptree_set_aux_state(brw
, irb
->mt
, irb
->mt_level
,
1278 irb
->mt_layer
, num_layers
,
1279 ISL_AUX_STATE_CLEAR
);
1281 DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__
,
1282 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
1284 enum isl_aux_usage aux_usage
=
1285 intel_miptree_render_aux_usage(brw
, irb
->mt
, isl_format
,
1287 intel_miptree_prepare_render(brw
, irb
->mt
, level
, irb
->mt_layer
,
1288 num_layers
, aux_usage
);
1290 struct isl_surf isl_tmp
[2];
1291 struct blorp_surf surf
;
1292 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, aux_usage
, true,
1293 &level
, irb
->mt_layer
, num_layers
, isl_tmp
);
1295 union isl_color_value clear_color
;
1296 memcpy(clear_color
.f32
, ctx
->Color
.ClearColor
.f
, sizeof(float) * 4);
1298 struct blorp_batch batch
;
1299 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1300 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
1301 level
, irb
->mt_layer
, num_layers
,
1303 clear_color
, color_write_disable
);
1304 blorp_batch_finish(&batch
);
1306 intel_miptree_finish_render(brw
, irb
->mt
, level
, irb
->mt_layer
,
1307 num_layers
, aux_usage
);
1314 brw_blorp_clear_color(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
1315 GLbitfield mask
, bool partial_clear
, bool encode_srgb
)
1317 for (unsigned buf
= 0; buf
< fb
->_NumColorDrawBuffers
; buf
++) {
1318 struct gl_renderbuffer
*rb
= fb
->_ColorDrawBuffers
[buf
];
1319 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
1321 /* Only clear the buffers present in the provided mask */
1322 if (((1 << fb
->_ColorDrawBufferIndexes
[buf
]) & mask
) == 0)
1325 /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
1326 * the framebuffer can be complete with some attachments missing. In
1327 * this case the _ColorDrawBuffers pointer will be NULL.
1332 do_single_blorp_clear(brw
, fb
, rb
, buf
, partial_clear
, encode_srgb
);
1333 irb
->need_downsample
= true;
1340 brw_blorp_clear_depth_stencil(struct brw_context
*brw
,
1341 struct gl_framebuffer
*fb
,
1342 GLbitfield mask
, bool partial_clear
)
1344 const struct gl_context
*ctx
= &brw
->ctx
;
1345 struct gl_renderbuffer
*depth_rb
=
1346 fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
;
1347 struct gl_renderbuffer
*stencil_rb
=
1348 fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
1350 if (!depth_rb
|| ctx
->Depth
.Mask
== GL_FALSE
)
1351 mask
&= ~BUFFER_BIT_DEPTH
;
1353 if (!stencil_rb
|| (ctx
->Stencil
.WriteMask
[0] & 0xff) == 0)
1354 mask
&= ~BUFFER_BIT_STENCIL
;
1356 if (!(mask
& (BUFFER_BITS_DEPTH_STENCIL
)))
1359 uint32_t x0
, x1
, y0
, y1
, rb_name
, rb_height
;
1361 rb_name
= depth_rb
->Name
;
1362 rb_height
= depth_rb
->Height
;
1364 assert(depth_rb
->Width
== stencil_rb
->Width
);
1365 assert(depth_rb
->Height
== stencil_rb
->Height
);
1369 rb_name
= stencil_rb
->Name
;
1370 rb_height
= stencil_rb
->Height
;
1379 y0
= rb_height
- fb
->_Ymax
;
1380 y1
= rb_height
- fb
->_Ymin
;
1383 /* If the clear region is empty, just return. */
1384 if (x0
== x1
|| y0
== y1
)
1387 uint32_t level
, start_layer
, num_layers
;
1388 struct isl_surf isl_tmp
[4];
1389 struct blorp_surf depth_surf
, stencil_surf
;
1391 struct intel_mipmap_tree
*depth_mt
= NULL
;
1392 if (mask
& BUFFER_BIT_DEPTH
) {
1393 struct intel_renderbuffer
*irb
= intel_renderbuffer(depth_rb
);
1394 depth_mt
= find_miptree(GL_DEPTH_BUFFER_BIT
, irb
);
1396 level
= irb
->mt_level
;
1397 start_layer
= irb
->mt_layer
;
1398 num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1400 intel_miptree_prepare_depth(brw
, depth_mt
, level
,
1401 start_layer
, num_layers
);
1403 unsigned depth_level
= level
;
1404 blorp_surf_for_miptree(brw
, &depth_surf
, depth_mt
, depth_mt
->aux_usage
,
1405 true, &depth_level
, start_layer
, num_layers
,
1407 assert(depth_level
== level
);
1410 uint8_t stencil_mask
= 0;
1411 struct intel_mipmap_tree
*stencil_mt
= NULL
;
1412 if (mask
& BUFFER_BIT_STENCIL
) {
1413 struct intel_renderbuffer
*irb
= intel_renderbuffer(stencil_rb
);
1414 stencil_mt
= find_miptree(GL_STENCIL_BUFFER_BIT
, irb
);
1416 if (mask
& BUFFER_BIT_DEPTH
) {
1417 assert(level
== irb
->mt_level
);
1418 assert(start_layer
== irb
->mt_layer
);
1419 assert(num_layers
== fb
->MaxNumLayers
? irb
->layer_count
: 1);
1421 level
= irb
->mt_level
;
1422 start_layer
= irb
->mt_layer
;
1424 num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1426 stencil_mask
= ctx
->Stencil
.WriteMask
[0] & 0xff;
1428 intel_miptree_prepare_access(brw
, stencil_mt
, level
, 1,
1429 start_layer
, num_layers
,
1430 ISL_AUX_USAGE_NONE
, false);
1432 unsigned stencil_level
= level
;
1433 blorp_surf_for_miptree(brw
, &stencil_surf
, stencil_mt
,
1434 ISL_AUX_USAGE_NONE
, true,
1435 &stencil_level
, start_layer
, num_layers
,
1439 assert((mask
& BUFFER_BIT_DEPTH
) || stencil_mask
);
1441 struct blorp_batch batch
;
1442 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1443 blorp_clear_depth_stencil(&batch
, &depth_surf
, &stencil_surf
,
1444 level
, start_layer
, num_layers
,
1446 (mask
& BUFFER_BIT_DEPTH
), ctx
->Depth
.Clear
,
1447 stencil_mask
, ctx
->Stencil
.Clear
);
1448 blorp_batch_finish(&batch
);
1450 if (mask
& BUFFER_BIT_DEPTH
) {
1451 intel_miptree_finish_depth(brw
, depth_mt
, level
,
1452 start_layer
, num_layers
, true);
1456 intel_miptree_finish_write(brw
, stencil_mt
, level
,
1457 start_layer
, num_layers
,
1458 ISL_AUX_USAGE_NONE
);
1463 brw_blorp_resolve_color(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1464 unsigned level
, unsigned layer
,
1465 enum isl_aux_op resolve_op
)
1467 DBG("%s to mt %p level %u layer %u\n", __FUNCTION__
, mt
, level
, layer
);
1469 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
1471 struct isl_surf isl_tmp
[1];
1472 struct blorp_surf surf
;
1473 blorp_surf_for_miptree(brw
, &surf
, mt
, mt
->aux_usage
, true,
1474 &level
, layer
, 1 /* num_layers */,
1477 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1479 * "Any transition from any value in {Clear, Render, Resolve} to a
1480 * different value in {Clear, Render, Resolve} requires end of pipe
1483 * In other words, fast clear ops are not properly synchronized with
1484 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1485 * contents of the previous draw hit the render target before we resolve
1486 * and again afterwards to ensure that the resolve is complete before we
1487 * do any more regular drawing.
1489 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1492 struct blorp_batch batch
;
1493 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1494 blorp_ccs_resolve(&batch
, &surf
, level
, layer
, 1,
1495 brw_blorp_to_isl_format(brw
, format
, true),
1497 blorp_batch_finish(&batch
);
1499 /* See comment above */
1500 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1504 brw_blorp_mcs_partial_resolve(struct brw_context
*brw
,
1505 struct intel_mipmap_tree
*mt
,
1506 uint32_t start_layer
, uint32_t num_layers
)
1508 DBG("%s to mt %p layers %u-%u\n", __FUNCTION__
, mt
,
1509 start_layer
, start_layer
+ num_layers
- 1);
1511 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1513 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
1514 enum isl_format isl_format
= brw_blorp_to_isl_format(brw
, format
, true);
1516 struct isl_surf isl_tmp
[1];
1517 struct blorp_surf surf
;
1519 blorp_surf_for_miptree(brw
, &surf
, mt
, ISL_AUX_USAGE_MCS
, true,
1520 &level
, start_layer
, num_layers
, isl_tmp
);
1522 struct blorp_batch batch
;
1523 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1524 blorp_mcs_partial_resolve(&batch
, &surf
, isl_format
,
1525 start_layer
, num_layers
);
1526 blorp_batch_finish(&batch
);
1530 * Perform a HiZ or depth resolve operation.
1532 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
1533 * PRM, Volume 1, Part 2:
1534 * - 7.5.3.1 Depth Buffer Clear
1535 * - 7.5.3.2 Depth Buffer Resolve
1536 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1539 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1540 unsigned int level
, unsigned int start_layer
,
1541 unsigned int num_layers
, enum isl_aux_op op
)
1543 assert(intel_miptree_level_has_hiz(mt
, level
));
1544 assert(op
!= ISL_AUX_OP_NONE
);
1545 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1546 const char *opname
= NULL
;
1549 case ISL_AUX_OP_FULL_RESOLVE
:
1550 opname
= "depth resolve";
1552 case ISL_AUX_OP_AMBIGUATE
:
1553 opname
= "hiz ambiguate";
1555 case ISL_AUX_OP_FAST_CLEAR
:
1556 opname
= "depth clear";
1558 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1559 case ISL_AUX_OP_NONE
:
1560 unreachable("Invalid HiZ op");
1563 DBG("%s %s to mt %p level %d layers %d-%d\n",
1564 __func__
, opname
, mt
, level
, start_layer
, start_layer
+ num_layers
- 1);
1566 /* The following stalls and flushes are only documented to be required for
1567 * HiZ clear operations. However, they also seem to be required for
1568 * resolve operations.
1570 if (devinfo
->gen
== 6) {
1571 /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
1573 * "If other rendering operations have preceded this clear, a
1574 * PIPE_CONTROL with write cache flush enabled and Z-inhibit
1575 * disabled must be issued before the rectangle primitive used for
1576 * the depth buffer clear operation.
1578 brw_emit_pipe_control_flush(brw
,
1579 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1580 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1581 PIPE_CONTROL_CS_STALL
);
1582 } else if (devinfo
->gen
>= 7) {
1584 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
1586 * If other rendering operations have preceded this clear, a
1587 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
1588 * enabled must be issued before the rectangle primitive used for
1589 * the depth buffer clear operation.
1591 * Same applies for Gen8 and Gen9.
1593 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
1594 * PIPE_CONTROL, Depth Cache Flush Enable:
1596 * This bit must not be set when Depth Stall Enable bit is set in
1599 * This is confirmed to hold for real, HSW gets immediate gpu hangs.
1601 * Therefore issue two pipe control flushes, one for cache flush and
1602 * another for depth stall.
1604 brw_emit_pipe_control_flush(brw
,
1605 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1606 PIPE_CONTROL_CS_STALL
);
1608 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
1611 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
&& mt
->aux_buf
);
1613 struct isl_surf isl_tmp
[2];
1614 struct blorp_surf surf
;
1615 blorp_surf_for_miptree(brw
, &surf
, mt
, ISL_AUX_USAGE_HIZ
, true,
1616 &level
, start_layer
, num_layers
, isl_tmp
);
1618 struct blorp_batch batch
;
1619 blorp_batch_init(&brw
->blorp
, &batch
, brw
,
1620 BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
);
1621 blorp_hiz_op(&batch
, &surf
, level
, start_layer
, num_layers
, op
);
1622 blorp_batch_finish(&batch
);
1624 /* The following stalls and flushes are only documented to be required for
1625 * HiZ clear operations. However, they also seem to be required for
1626 * resolve operations.
1628 if (devinfo
->gen
== 6) {
1629 /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
1631 * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be
1632 * followed by a PIPE_CONTROL command with DEPTH_STALL bit set
1633 * and Then followed by Depth FLUSH'
1635 brw_emit_pipe_control_flush(brw
,
1636 PIPE_CONTROL_DEPTH_STALL
);
1638 brw_emit_pipe_control_flush(brw
,
1639 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1640 PIPE_CONTROL_CS_STALL
);
1641 } else if (devinfo
->gen
>= 8) {
1643 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
1645 * "Depth buffer clear pass using any of the methods (WM_STATE,
1646 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
1647 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
1648 * "set" before starting to render. DepthStall and DepthFlush are
1649 * not needed between consecutive depth clear passes nor is it
1650 * required if the depth clear pass was done with
1651 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
1653 * TODO: Such as the spec says, this could be conditional.
1655 brw_emit_pipe_control_flush(brw
,
1656 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1657 PIPE_CONTROL_DEPTH_STALL
);