2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/blend.h"
27 #include "main/bufferobj.h"
28 #include "main/enums.h"
29 #include "main/fbobject.h"
30 #include "main/image.h"
31 #include "main/renderbuffer.h"
32 #include "main/glformats.h"
34 #include "brw_blorp.h"
35 #include "brw_context.h"
36 #include "brw_defines.h"
37 #include "brw_meta_util.h"
38 #include "brw_state.h"
39 #include "intel_buffer_objects.h"
40 #include "intel_fbo.h"
41 #include "common/gen_debug.h"
43 #define FILE_DEBUG_FLAG DEBUG_BLORP
46 brw_blorp_lookup_shader(struct blorp_context
*blorp
,
47 const void *key
, uint32_t key_size
,
48 uint32_t *kernel_out
, void *prog_data_out
)
50 struct brw_context
*brw
= blorp
->driver_ctx
;
51 return brw_search_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
,
52 key
, key_size
, kernel_out
, prog_data_out
);
56 brw_blorp_upload_shader(struct blorp_context
*blorp
,
57 const void *key
, uint32_t key_size
,
58 const void *kernel
, uint32_t kernel_size
,
59 const struct brw_stage_prog_data
*prog_data
,
60 uint32_t prog_data_size
,
61 uint32_t *kernel_out
, void *prog_data_out
)
63 struct brw_context
*brw
= blorp
->driver_ctx
;
64 brw_upload_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
, key
, key_size
,
65 kernel
, kernel_size
, prog_data
, prog_data_size
,
66 kernel_out
, prog_data_out
);
71 brw_blorp_init(struct brw_context
*brw
)
73 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
75 blorp_init(&brw
->blorp
, brw
, &brw
->isl_dev
);
77 brw
->blorp
.compiler
= brw
->screen
->compiler
;
79 switch (devinfo
->gen
) {
81 if (devinfo
->is_g4x
) {
82 brw
->blorp
.exec
= gen45_blorp_exec
;
84 brw
->blorp
.exec
= gen4_blorp_exec
;
88 brw
->blorp
.exec
= gen5_blorp_exec
;
91 brw
->blorp
.exec
= gen6_blorp_exec
;
94 if (devinfo
->is_haswell
) {
95 brw
->blorp
.exec
= gen75_blorp_exec
;
97 brw
->blorp
.exec
= gen7_blorp_exec
;
101 brw
->blorp
.exec
= gen8_blorp_exec
;
104 brw
->blorp
.exec
= gen9_blorp_exec
;
107 brw
->blorp
.exec
= gen10_blorp_exec
;
110 unreachable("Invalid gen");
113 brw
->blorp
.lookup_shader
= brw_blorp_lookup_shader
;
114 brw
->blorp
.upload_shader
= brw_blorp_upload_shader
;
117 static uint32_t wb_mocs
[] = {
124 static uint32_t pte_mocs
[] = {
132 blorp_surf_for_miptree(struct brw_context
*brw
,
133 struct blorp_surf
*surf
,
134 struct intel_mipmap_tree
*mt
,
135 enum isl_aux_usage aux_usage
,
136 bool is_render_target
,
138 unsigned start_layer
, unsigned num_layers
,
139 struct isl_surf tmp_surfs
[1])
141 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
143 if (mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
) {
144 const unsigned num_samples
= mt
->surf
.samples
;
145 for (unsigned i
= 0; i
< num_layers
; i
++) {
146 for (unsigned s
= 0; s
< num_samples
; s
++) {
147 const unsigned phys_layer
= (start_layer
+ i
) * num_samples
+ s
;
148 intel_miptree_check_level_layer(mt
, *level
, phys_layer
);
152 for (unsigned i
= 0; i
< num_layers
; i
++)
153 intel_miptree_check_level_layer(mt
, *level
, start_layer
+ i
);
156 surf
->surf
= &mt
->surf
;
157 surf
->addr
= (struct blorp_address
) {
159 .offset
= mt
->offset
,
160 .reloc_flags
= is_render_target
? EXEC_OBJECT_WRITE
: 0,
161 .mocs
= (is_render_target
|| mt
->bo
->external
) ? pte_mocs
[devinfo
->gen
] :
162 wb_mocs
[devinfo
->gen
],
165 surf
->aux_usage
= aux_usage
;
167 struct isl_surf
*aux_surf
= NULL
;
169 aux_surf
= &mt
->mcs_buf
->surf
;
170 else if (mt
->hiz_buf
)
171 aux_surf
= &mt
->hiz_buf
->surf
;
173 if (mt
->format
== MESA_FORMAT_S_UINT8
&& is_render_target
&&
175 mt
->r8stencil_needs_update
= true;
177 if (surf
->aux_usage
== ISL_AUX_USAGE_HIZ
&&
178 !intel_miptree_level_has_hiz(mt
, *level
))
179 surf
->aux_usage
= ISL_AUX_USAGE_NONE
;
181 if (surf
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
182 /* We only really need a clear color if we also have an auxiliary
183 * surface. Without one, it does nothing.
185 surf
->clear_color
= mt
->fast_clear_color
;
187 surf
->aux_surf
= aux_surf
;
188 surf
->aux_addr
= (struct blorp_address
) {
189 .reloc_flags
= is_render_target
? EXEC_OBJECT_WRITE
: 0,
190 .mocs
= surf
->addr
.mocs
,
194 surf
->aux_addr
.buffer
= mt
->mcs_buf
->bo
;
195 surf
->aux_addr
.offset
= mt
->mcs_buf
->offset
;
198 assert(surf
->aux_usage
== ISL_AUX_USAGE_HIZ
);
200 surf
->aux_addr
.buffer
= mt
->hiz_buf
->bo
;
201 surf
->aux_addr
.offset
= mt
->hiz_buf
->offset
;
204 surf
->aux_addr
= (struct blorp_address
) {
207 memset(&surf
->clear_color
, 0, sizeof(surf
->clear_color
));
209 assert((surf
->aux_usage
== ISL_AUX_USAGE_NONE
) ==
210 (surf
->aux_addr
.buffer
== NULL
));
212 /* ISL wants real levels, not offset ones. */
213 *level
-= mt
->first_level
;
216 static enum isl_format
217 brw_blorp_to_isl_format(struct brw_context
*brw
, mesa_format format
,
218 bool is_render_target
)
221 case MESA_FORMAT_NONE
:
222 return ISL_FORMAT_UNSUPPORTED
;
223 case MESA_FORMAT_S_UINT8
:
224 return ISL_FORMAT_R8_UINT
;
225 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
226 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
227 return ISL_FORMAT_R24_UNORM_X8_TYPELESS
;
228 case MESA_FORMAT_Z_FLOAT32
:
229 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
230 return ISL_FORMAT_R32_FLOAT
;
231 case MESA_FORMAT_Z_UNORM16
:
232 return ISL_FORMAT_R16_UNORM
;
234 if (is_render_target
) {
235 assert(brw
->mesa_format_supports_render
[format
]);
236 return brw
->mesa_to_isl_render_format
[format
];
238 return brw_isl_format_for_mesa_format(format
);
246 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
247 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
249 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
252 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
254 * which is simply adding 4 then modding by 8 (or anding with 7).
256 * We then may need to apply workarounds for textureGather hardware bugs.
258 static enum isl_channel_select
259 swizzle_to_scs(GLenum swizzle
)
261 return (enum isl_channel_select
)((swizzle
+ 4) & 7);
265 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
266 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
267 * the physical layer holding sample 0. So, for example, if
268 * src_mt->surf.samples == 4, then logical layer n corresponds to src_layer ==
272 brw_blorp_blit_miptrees(struct brw_context
*brw
,
273 struct intel_mipmap_tree
*src_mt
,
274 unsigned src_level
, unsigned src_layer
,
275 mesa_format src_format
, int src_swizzle
,
276 struct intel_mipmap_tree
*dst_mt
,
277 unsigned dst_level
, unsigned dst_layer
,
278 mesa_format dst_format
,
279 float src_x0
, float src_y0
,
280 float src_x1
, float src_y1
,
281 float dst_x0
, float dst_y0
,
282 float dst_x1
, float dst_y1
,
283 GLenum filter
, bool mirror_x
, bool mirror_y
,
284 bool decode_srgb
, bool encode_srgb
)
286 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
288 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
289 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
291 src_mt
->surf
.samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
292 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
293 dst_mt
->surf
.samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
294 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
297 if (!decode_srgb
&& _mesa_get_format_color_encoding(src_format
) == GL_SRGB
)
298 src_format
= _mesa_get_srgb_format_linear(src_format
);
300 if (!encode_srgb
&& _mesa_get_format_color_encoding(dst_format
) == GL_SRGB
)
301 dst_format
= _mesa_get_srgb_format_linear(dst_format
);
303 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
304 * texture, the above code configures the source format for L32_FLOAT or
305 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
306 * the SAMPLE message appears to handle multisampled L32_FLOAT and
307 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
308 * around the problem by using a source format of R32_FLOAT. This
309 * shouldn't affect rendering correctness, since the destination format is
310 * R32_FLOAT, so only the contents of the red channel matters.
312 if (devinfo
->gen
== 6 &&
313 src_mt
->surf
.samples
> 1 && dst_mt
->surf
.samples
<= 1 &&
314 src_mt
->format
== dst_mt
->format
&&
315 (dst_format
== MESA_FORMAT_L_FLOAT32
||
316 dst_format
== MESA_FORMAT_I_FLOAT32
)) {
317 src_format
= dst_format
= MESA_FORMAT_R_FLOAT32
;
320 enum isl_format src_isl_format
=
321 brw_blorp_to_isl_format(brw
, src_format
, false);
322 enum isl_aux_usage src_aux_usage
=
323 intel_miptree_texture_aux_usage(brw
, src_mt
, src_isl_format
);
324 /* We do format workarounds for some depth formats so we can't reliably
325 * sample with HiZ. One of these days, we should fix that.
327 if (src_aux_usage
== ISL_AUX_USAGE_HIZ
)
328 src_aux_usage
= ISL_AUX_USAGE_NONE
;
329 const bool src_clear_supported
=
330 src_aux_usage
!= ISL_AUX_USAGE_NONE
&& src_mt
->format
== src_format
;
331 intel_miptree_prepare_access(brw
, src_mt
, src_level
, 1, src_layer
, 1,
332 src_aux_usage
, src_clear_supported
);
334 enum isl_format dst_isl_format
=
335 brw_blorp_to_isl_format(brw
, dst_format
, true);
336 enum isl_aux_usage dst_aux_usage
=
337 intel_miptree_render_aux_usage(brw
, dst_mt
, dst_isl_format
, false);
338 const bool dst_clear_supported
= dst_aux_usage
!= ISL_AUX_USAGE_NONE
;
339 intel_miptree_prepare_access(brw
, dst_mt
, dst_level
, 1, dst_layer
, 1,
340 dst_aux_usage
, dst_clear_supported
);
342 struct isl_surf tmp_surfs
[2];
343 struct blorp_surf src_surf
, dst_surf
;
344 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, src_aux_usage
, false,
345 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
346 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, dst_aux_usage
, true,
347 &dst_level
, dst_layer
, 1, &tmp_surfs
[1]);
349 struct isl_swizzle src_isl_swizzle
= {
350 .r
= swizzle_to_scs(GET_SWZ(src_swizzle
, 0)),
351 .g
= swizzle_to_scs(GET_SWZ(src_swizzle
, 1)),
352 .b
= swizzle_to_scs(GET_SWZ(src_swizzle
, 2)),
353 .a
= swizzle_to_scs(GET_SWZ(src_swizzle
, 3)),
356 struct blorp_batch batch
;
357 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
358 blorp_blit(&batch
, &src_surf
, src_level
, src_layer
,
359 src_isl_format
, src_isl_swizzle
,
360 &dst_surf
, dst_level
, dst_layer
,
361 dst_isl_format
, ISL_SWIZZLE_IDENTITY
,
362 src_x0
, src_y0
, src_x1
, src_y1
,
363 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
364 filter
, mirror_x
, mirror_y
);
365 blorp_batch_finish(&batch
);
367 intel_miptree_finish_write(brw
, dst_mt
, dst_level
, dst_layer
, 1,
372 brw_blorp_copy_miptrees(struct brw_context
*brw
,
373 struct intel_mipmap_tree
*src_mt
,
374 unsigned src_level
, unsigned src_layer
,
375 struct intel_mipmap_tree
*dst_mt
,
376 unsigned dst_level
, unsigned dst_layer
,
377 unsigned src_x
, unsigned src_y
,
378 unsigned dst_x
, unsigned dst_y
,
379 unsigned src_width
, unsigned src_height
)
381 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
383 DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
384 "to %dx %s mt %p %d %d (%d,%d)\n",
386 src_mt
->surf
.samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
387 src_level
, src_layer
, src_x
, src_y
, src_width
, src_height
,
388 dst_mt
->surf
.samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
389 dst_level
, dst_layer
, dst_x
, dst_y
);
391 enum isl_aux_usage src_aux_usage
, dst_aux_usage
;
392 bool src_clear_supported
, dst_clear_supported
;
394 switch (src_mt
->aux_usage
) {
395 case ISL_AUX_USAGE_MCS
:
396 case ISL_AUX_USAGE_CCS_E
:
397 src_aux_usage
= src_mt
->aux_usage
;
398 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
399 * we're going to re-interpret the format as an integer format possibly
400 * with a different number of components, we can't handle clear colors
403 src_clear_supported
= devinfo
->gen
>= 9;
406 src_aux_usage
= ISL_AUX_USAGE_NONE
;
407 src_clear_supported
= false;
411 switch (dst_mt
->aux_usage
) {
412 case ISL_AUX_USAGE_MCS
:
413 case ISL_AUX_USAGE_CCS_E
:
414 dst_aux_usage
= dst_mt
->aux_usage
;
415 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
416 * we're going to re-interpret the format as an integer format possibly
417 * with a different number of components, we can't handle clear colors
420 dst_clear_supported
= devinfo
->gen
>= 9;
423 dst_aux_usage
= ISL_AUX_USAGE_NONE
;
424 dst_clear_supported
= false;
428 intel_miptree_prepare_access(brw
, src_mt
, src_level
, 1, src_layer
, 1,
429 src_aux_usage
, src_clear_supported
);
430 intel_miptree_prepare_access(brw
, dst_mt
, dst_level
, 1, dst_layer
, 1,
431 dst_aux_usage
, dst_clear_supported
);
433 struct isl_surf tmp_surfs
[2];
434 struct blorp_surf src_surf
, dst_surf
;
435 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, src_aux_usage
, false,
436 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
437 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, dst_aux_usage
, true,
438 &dst_level
, dst_layer
, 1, &tmp_surfs
[1]);
440 struct blorp_batch batch
;
441 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
442 blorp_copy(&batch
, &src_surf
, src_level
, src_layer
,
443 &dst_surf
, dst_level
, dst_layer
,
444 src_x
, src_y
, dst_x
, dst_y
, src_width
, src_height
);
445 blorp_batch_finish(&batch
);
447 intel_miptree_finish_write(brw
, dst_mt
, dst_level
, dst_layer
, 1,
452 brw_blorp_copy_buffers(struct brw_context
*brw
,
453 struct brw_bo
*src_bo
,
455 struct brw_bo
*dst_bo
,
459 DBG("%s %d bytes from %p[%d] to %p[%d]",
460 __func__
, size
, src_bo
, src_offset
, dst_bo
, dst_offset
);
462 struct blorp_batch batch
;
463 struct blorp_address src
= { .buffer
= src_bo
, .offset
= src_offset
};
464 struct blorp_address dst
= { .buffer
= dst_bo
, .offset
= dst_offset
};
466 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
467 blorp_buffer_copy(&batch
, src
, dst
, size
);
468 blorp_batch_finish(&batch
);
472 static struct intel_mipmap_tree
*
473 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
475 struct intel_mipmap_tree
*mt
= irb
->mt
;
476 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
482 blorp_get_texture_swizzle(const struct intel_renderbuffer
*irb
)
484 return irb
->Base
.Base
._BaseFormat
== GL_RGB
?
485 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ONE
) :
490 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
491 struct intel_renderbuffer
*src_irb
, mesa_format src_format
,
492 struct intel_renderbuffer
*dst_irb
, mesa_format dst_format
,
493 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
494 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
495 GLenum filter
, bool mirror_x
, bool mirror_y
)
497 const struct gl_context
*ctx
= &brw
->ctx
;
499 /* Find source/dst miptrees */
500 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
501 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
503 const bool do_srgb
= ctx
->Color
.sRGBEnabled
;
506 brw_blorp_blit_miptrees(brw
,
507 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
508 src_format
, blorp_get_texture_swizzle(src_irb
),
509 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
511 srcX0
, srcY0
, srcX1
, srcY1
,
512 dstX0
, dstY0
, dstX1
, dstY1
,
513 filter
, mirror_x
, mirror_y
,
516 dst_irb
->need_downsample
= true;
520 try_blorp_blit(struct brw_context
*brw
,
521 const struct gl_framebuffer
*read_fb
,
522 const struct gl_framebuffer
*draw_fb
,
523 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
524 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
525 GLenum filter
, GLbitfield buffer_bit
)
527 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
528 struct gl_context
*ctx
= &brw
->ctx
;
530 /* Sync up the state of window system buffers. We need to do this before
531 * we go looking for the buffers.
533 intel_prepare_render(brw
);
535 bool mirror_x
, mirror_y
;
536 if (brw_meta_mirror_clip_and_scissor(ctx
, read_fb
, draw_fb
,
537 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
538 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
539 &mirror_x
, &mirror_y
))
543 struct intel_renderbuffer
*src_irb
;
544 struct intel_renderbuffer
*dst_irb
;
545 struct intel_mipmap_tree
*src_mt
;
546 struct intel_mipmap_tree
*dst_mt
;
547 switch (buffer_bit
) {
548 case GL_COLOR_BUFFER_BIT
:
549 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
550 for (unsigned i
= 0; i
< draw_fb
->_NumColorDrawBuffers
; ++i
) {
551 dst_irb
= intel_renderbuffer(draw_fb
->_ColorDrawBuffers
[i
]);
553 do_blorp_blit(brw
, buffer_bit
,
554 src_irb
, src_irb
->Base
.Base
.Format
,
555 dst_irb
, dst_irb
->Base
.Base
.Format
,
556 srcX0
, srcY0
, srcX1
, srcY1
,
557 dstX0
, dstY0
, dstX1
, dstY1
,
558 filter
, mirror_x
, mirror_y
);
561 case GL_DEPTH_BUFFER_BIT
:
563 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
565 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
566 src_mt
= find_miptree(buffer_bit
, src_irb
);
567 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
569 /* We can't handle format conversions between Z24 and other formats
570 * since we have to lie about the surface format. See the comments in
571 * brw_blorp_surface_info::set().
573 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
574 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
))
577 /* We also can't handle any combined depth-stencil formats because we
578 * have to reinterpret as a color format.
580 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
581 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
584 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
585 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
586 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
587 filter
, mirror_x
, mirror_y
);
589 case GL_STENCIL_BUFFER_BIT
:
590 /* Blorp doesn't support combined depth stencil which is all we have
593 if (devinfo
->gen
< 6)
597 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
599 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
600 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
601 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
602 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
603 filter
, mirror_x
, mirror_y
);
606 unreachable("not reached");
613 apply_y_flip(int *y0
, int *y1
, int height
)
615 int tmp
= height
- *y0
;
621 brw_blorp_copytexsubimage(struct brw_context
*brw
,
622 struct gl_renderbuffer
*src_rb
,
623 struct gl_texture_image
*dst_image
,
625 int srcX0
, int srcY0
,
626 int dstX0
, int dstY0
,
627 int width
, int height
)
629 struct gl_context
*ctx
= &brw
->ctx
;
630 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
631 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
633 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
634 if (brw
->ctx
._ImageTransferState
)
637 /* Sync up the state of window system buffers. We need to do this before
638 * we go looking at the src renderbuffer's miptree.
640 intel_prepare_render(brw
);
642 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
643 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
645 /* There is support for only up to eight samples. */
646 if (src_mt
->surf
.samples
> 8 || dst_mt
->surf
.samples
> 8)
649 if (_mesa_get_format_base_format(src_rb
->Format
) !=
650 _mesa_get_format_base_format(dst_image
->TexFormat
)) {
654 /* We can't handle format conversions between Z24 and other formats since
655 * we have to lie about the surface format. See the comments in
656 * brw_blorp_surface_info::set().
658 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
659 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
)) {
663 /* We also can't handle any combined depth-stencil formats because we
664 * have to reinterpret as a color format.
666 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
667 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
670 if (!brw
->mesa_format_supports_render
[dst_image
->TexFormat
])
673 /* Source clipping shouldn't be necessary, since copytexsubimage (in
674 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
677 * Destination clipping shouldn't be necessary since the restrictions on
678 * glCopyTexSubImage prevent the user from specifying a destination rectangle
679 * that falls outside the bounds of the destination texture.
680 * See error_check_subtexture_dimensions().
683 int srcY1
= srcY0
+ height
;
684 int srcX1
= srcX0
+ width
;
685 int dstX1
= dstX0
+ width
;
686 int dstY1
= dstY0
+ height
;
688 /* Account for the fact that in the system framebuffer, the origin is at
691 bool mirror_y
= _mesa_is_winsys_fbo(ctx
->ReadBuffer
);
693 apply_y_flip(&srcY0
, &srcY1
, src_rb
->Height
);
695 /* Account for face selection and texture view MinLayer */
696 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
697 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
699 brw_blorp_blit_miptrees(brw
,
700 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
701 src_rb
->Format
, blorp_get_texture_swizzle(src_irb
),
702 dst_mt
, dst_level
, dst_slice
,
703 dst_image
->TexFormat
,
704 srcX0
, srcY0
, srcX1
, srcY1
,
705 dstX0
, dstY0
, dstX1
, dstY1
,
706 GL_NEAREST
, false, mirror_y
,
709 /* If we're copying to a packed depth stencil texture and the source
710 * framebuffer has separate stencil, we need to also copy the stencil data
713 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
714 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
716 src_irb
= intel_renderbuffer(src_rb
);
717 src_mt
= src_irb
->mt
;
719 if (src_mt
->stencil_mt
)
720 src_mt
= src_mt
->stencil_mt
;
721 if (dst_mt
->stencil_mt
)
722 dst_mt
= dst_mt
->stencil_mt
;
724 if (src_mt
!= dst_mt
) {
725 brw_blorp_blit_miptrees(brw
,
726 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
728 blorp_get_texture_swizzle(src_irb
),
729 dst_mt
, dst_level
, dst_slice
,
731 srcX0
, srcY0
, srcX1
, srcY1
,
732 dstX0
, dstY0
, dstX1
, dstY1
,
733 GL_NEAREST
, false, mirror_y
,
743 brw_blorp_framebuffer(struct brw_context
*brw
,
744 struct gl_framebuffer
*readFb
,
745 struct gl_framebuffer
*drawFb
,
746 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
747 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
748 GLbitfield mask
, GLenum filter
)
750 static GLbitfield buffer_bits
[] = {
753 GL_STENCIL_BUFFER_BIT
,
756 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
757 if ((mask
& buffer_bits
[i
]) &&
758 try_blorp_blit(brw
, readFb
, drawFb
,
759 srcX0
, srcY0
, srcX1
, srcY1
,
760 dstX0
, dstY0
, dstX1
, dstY1
,
761 filter
, buffer_bits
[i
])) {
762 mask
&= ~buffer_bits
[i
];
769 static struct brw_bo
*
770 blorp_get_client_bo(struct brw_context
*brw
,
771 unsigned w
, unsigned h
, unsigned d
,
772 GLenum target
, GLenum format
, GLenum type
,
774 const struct gl_pixelstore_attrib
*packing
,
775 uint32_t *offset_out
, uint32_t *row_stride_out
,
776 uint32_t *image_stride_out
, bool read_only
)
778 /* Account for SKIP_PIXELS, SKIP_ROWS, ALIGNMENT, and SKIP_IMAGES */
779 const GLuint dims
= _mesa_get_texture_dimensions(target
);
780 const uint32_t first_pixel
= _mesa_image_offset(dims
, packing
, w
, h
,
781 format
, type
, 0, 0, 0);
782 const uint32_t last_pixel
= _mesa_image_offset(dims
, packing
, w
, h
,
785 const uint32_t stride
= _mesa_image_row_stride(packing
, w
, format
, type
);
786 const uint32_t cpp
= _mesa_bytes_per_pixel(format
, type
);
787 const uint32_t size
= last_pixel
- first_pixel
;
789 *row_stride_out
= stride
;
790 *image_stride_out
= _mesa_image_image_stride(packing
, w
, h
, format
, type
);
792 if (_mesa_is_bufferobj(packing
->BufferObj
)) {
793 const uint32_t offset
= first_pixel
+ (intptr_t)pixels
;
794 if (!read_only
&& ((offset
% cpp
) || (stride
% cpp
))) {
795 perf_debug("Bad PBO alignment; fallback to CPU mapping\n");
799 /* This is a user-provided PBO. We just need to get the BO out */
800 struct intel_buffer_object
*intel_pbo
=
801 intel_buffer_object(packing
->BufferObj
);
803 intel_bufferobj_buffer(brw
, intel_pbo
, offset
, size
, !read_only
);
805 /* We take a reference to the BO so that the caller can just always
806 * unref without having to worry about whether it's a user PBO or one
809 brw_bo_reference(bo
);
811 *offset_out
= offset
;
814 /* Someone should have already checked that there is data to upload. */
817 /* Creating a temp buffer currently only works for upload */
820 /* This is not a user-provided PBO. Instead, pixels is a pointer to CPU
821 * data which we need to copy into a BO.
824 brw_bo_alloc(brw
->bufmgr
, "tmp_tex_subimage_src", size
, 64);
826 perf_debug("intel_texsubimage: temp bo creation failed: size = %u\n",
831 if (brw_bo_subdata(bo
, 0, size
, pixels
+ first_pixel
)) {
832 perf_debug("intel_texsubimage: temp bo upload failed\n");
833 brw_bo_unreference(bo
);
842 /* Consider all the restrictions and determine the format of the source. */
844 blorp_get_client_format(struct brw_context
*brw
,
845 GLenum format
, GLenum type
,
846 const struct gl_pixelstore_attrib
*packing
)
848 if (brw
->ctx
._ImageTransferState
)
849 return MESA_FORMAT_NONE
;
851 if (packing
->SwapBytes
|| packing
->LsbFirst
|| packing
->Invert
) {
852 perf_debug("intel_texsubimage_blorp: unsupported gl_pixelstore_attrib\n");
853 return MESA_FORMAT_NONE
;
856 if (format
!= GL_RED
&&
862 format
!= GL_ALPHA
&&
863 format
!= GL_RED_INTEGER
&&
864 format
!= GL_RG_INTEGER
&&
865 format
!= GL_RGB_INTEGER
&&
866 format
!= GL_BGR_INTEGER
&&
867 format
!= GL_RGBA_INTEGER
&&
868 format
!= GL_BGRA_INTEGER
) {
869 perf_debug("intel_texsubimage_blorp: %s not supported",
870 _mesa_enum_to_string(format
));
871 return MESA_FORMAT_NONE
;
874 return _mesa_tex_format_from_format_and_type(&brw
->ctx
, format
, type
);
878 need_signed_unsigned_int_conversion(mesa_format src_format
,
879 mesa_format dst_format
)
881 const GLenum src_type
= _mesa_get_format_datatype(src_format
);
882 const GLenum dst_type
= _mesa_get_format_datatype(dst_format
);
883 return (src_type
== GL_INT
&& dst_type
== GL_UNSIGNED_INT
) ||
884 (src_type
== GL_UNSIGNED_INT
&& dst_type
== GL_INT
);
888 brw_blorp_upload_miptree(struct brw_context
*brw
,
889 struct intel_mipmap_tree
*dst_mt
,
890 mesa_format dst_format
,
891 uint32_t level
, uint32_t x
, uint32_t y
, uint32_t z
,
892 uint32_t width
, uint32_t height
, uint32_t depth
,
893 GLenum target
, GLenum format
, GLenum type
,
895 const struct gl_pixelstore_attrib
*packing
)
897 const mesa_format src_format
=
898 blorp_get_client_format(brw
, format
, type
, packing
);
899 if (src_format
== MESA_FORMAT_NONE
)
902 if (!brw
->mesa_format_supports_render
[dst_format
]) {
903 perf_debug("intel_texsubimage: can't use %s as render target\n",
904 _mesa_get_format_name(dst_format
));
908 /* This function relies on blorp_blit to upload the pixel data to the
909 * miptree. But, blorp_blit doesn't support signed to unsigned or
910 * unsigned to signed integer conversions.
912 if (need_signed_unsigned_int_conversion(src_format
, dst_format
))
915 uint32_t src_offset
, src_row_stride
, src_image_stride
;
916 struct brw_bo
*src_bo
=
917 blorp_get_client_bo(brw
, width
, height
, depth
,
918 target
, format
, type
, pixels
, packing
,
919 &src_offset
, &src_row_stride
,
920 &src_image_stride
, true);
924 /* Now that source is offset to correct starting point, adjust the
925 * given dimensions to treat 1D arrays as 2D.
927 if (target
== GL_TEXTURE_1D_ARRAY
) {
934 src_image_stride
= src_row_stride
;
937 intel_miptree_check_level_layer(dst_mt
, level
, z
+ depth
- 1);
941 /* Blit slice-by-slice creating a single-slice miptree for each layer. Even
942 * in case of linear buffers hardware wants image arrays to be aligned by
943 * four rows. This way hardware only gets one image at a time and any
944 * source alignment will do.
946 for (unsigned i
= 0; i
< depth
; ++i
) {
947 struct intel_mipmap_tree
*src_mt
= intel_miptree_create_for_bo(
948 brw
, src_bo
, src_format
,
949 src_offset
+ i
* src_image_stride
,
954 perf_debug("intel_texsubimage: miptree creation for src failed\n");
958 /* In case exact match is needed, copy using equivalent UINT formats
959 * preventing hardware from changing presentation for SNORM -1.
961 if (src_mt
->format
== dst_format
) {
962 brw_blorp_copy_miptrees(brw
, src_mt
, 0, 0,
963 dst_mt
, level
, z
+ i
,
964 0, 0, x
, y
, width
, height
);
966 brw_blorp_blit_miptrees(brw
, src_mt
, 0, 0,
967 src_format
, SWIZZLE_XYZW
,
968 dst_mt
, level
, z
+ i
,
971 x
, y
, x
+ width
, y
+ height
,
972 GL_NEAREST
, false, false, false, false);
975 intel_miptree_release(&src_mt
);
981 brw_bo_unreference(src_bo
);
987 brw_blorp_download_miptree(struct brw_context
*brw
,
988 struct intel_mipmap_tree
*src_mt
,
989 mesa_format src_format
, uint32_t src_swizzle
,
990 uint32_t level
, uint32_t x
, uint32_t y
, uint32_t z
,
991 uint32_t width
, uint32_t height
, uint32_t depth
,
992 GLenum target
, GLenum format
, GLenum type
,
993 bool y_flip
, const void *pixels
,
994 const struct gl_pixelstore_attrib
*packing
)
996 const mesa_format dst_format
=
997 blorp_get_client_format(brw
, format
, type
, packing
);
998 if (dst_format
== MESA_FORMAT_NONE
)
1001 if (!brw
->mesa_format_supports_render
[dst_format
]) {
1002 perf_debug("intel_texsubimage: can't use %s as render target\n",
1003 _mesa_get_format_name(dst_format
));
1007 /* This function relies on blorp_blit to download the pixel data from the
1008 * miptree. But, blorp_blit doesn't support signed to unsigned or unsigned
1009 * to signed integer conversions.
1011 if (need_signed_unsigned_int_conversion(src_format
, dst_format
))
1014 /* We can't fetch from LUMINANCE or intensity as that would require a
1015 * non-trivial swizzle.
1017 switch (_mesa_get_format_base_format(src_format
)) {
1019 case GL_LUMINANCE_ALPHA
:
1026 /* This pass only works for PBOs */
1027 assert(_mesa_is_bufferobj(packing
->BufferObj
));
1029 uint32_t dst_offset
, dst_row_stride
, dst_image_stride
;
1030 struct brw_bo
*dst_bo
=
1031 blorp_get_client_bo(brw
, width
, height
, depth
,
1032 target
, format
, type
, pixels
, packing
,
1033 &dst_offset
, &dst_row_stride
,
1034 &dst_image_stride
, false);
1038 /* Now that source is offset to correct starting point, adjust the
1039 * given dimensions to treat 1D arrays as 2D.
1041 if (target
== GL_TEXTURE_1D_ARRAY
) {
1048 dst_image_stride
= dst_row_stride
;
1051 intel_miptree_check_level_layer(src_mt
, level
, z
+ depth
- 1);
1054 int y1
= y
+ height
;
1056 apply_y_flip(&y0
, &y1
, minify(src_mt
->surf
.phys_level0_sa
.height
,
1057 level
- src_mt
->first_level
));
1060 bool result
= false;
1062 /* Blit slice-by-slice creating a single-slice miptree for each layer. Even
1063 * in case of linear buffers hardware wants image arrays to be aligned by
1064 * four rows. This way hardware only gets one image at a time and any
1065 * source alignment will do.
1067 for (unsigned i
= 0; i
< depth
; ++i
) {
1068 struct intel_mipmap_tree
*dst_mt
= intel_miptree_create_for_bo(
1069 brw
, dst_bo
, dst_format
,
1070 dst_offset
+ i
* dst_image_stride
,
1075 perf_debug("intel_texsubimage: miptree creation for src failed\n");
1079 /* In case exact match is needed, copy using equivalent UINT formats
1080 * preventing hardware from changing presentation for SNORM -1.
1082 if (dst_mt
->format
== src_format
&& !y_flip
&&
1083 src_swizzle
== SWIZZLE_XYZW
) {
1084 brw_blorp_copy_miptrees(brw
, src_mt
, level
, z
+ i
,
1086 x
, y
, 0, 0, width
, height
);
1088 brw_blorp_blit_miptrees(brw
, src_mt
, level
, z
+ i
,
1089 src_format
, src_swizzle
,
1090 dst_mt
, 0, 0, dst_format
,
1091 x
, y0
, x
+ width
, y1
,
1092 0, 0, width
, height
,
1093 GL_NEAREST
, false, y_flip
, false, false);
1096 intel_miptree_release(&dst_mt
);
1101 /* As we implement PBO transfers by binding the user-provided BO as a
1102 * fake framebuffer and rendering to it. This breaks the invariant of the
1103 * GL that nothing is able to render to a BO, causing nondeterministic
1104 * corruption issues because the render cache is not coherent with a
1105 * number of other caches that the BO could potentially be bound to
1108 * This could be solved in the same way that we guarantee texture
1109 * coherency after a texture is attached to a framebuffer and
1110 * rendered to, but that would involve checking *all* BOs bound to
1111 * the pipeline for the case we need to emit a cache flush due to
1112 * previous rendering to any of them -- Including vertex, index,
1113 * uniform, atomic counter, shader image, transform feedback,
1114 * indirect draw buffers, etc.
1116 * That would increase the per-draw call overhead even though it's
1117 * very unlikely that any of the BOs bound to the pipeline has been
1118 * rendered to via a PBO at any point, so it seems better to just
1119 * flush here unconditionally.
1121 brw_emit_mi_flush(brw
);
1124 brw_bo_unreference(dst_bo
);
1130 set_write_disables(const struct intel_renderbuffer
*irb
,
1131 const GLubyte
*color_mask
, bool *color_write_disable
)
1133 /* Format information in the renderbuffer represents the requirements
1134 * given by the client. There are cases where the backing miptree uses,
1135 * for example, RGBA to represent RGBX. Since the client is only expecting
1136 * RGB we can treat alpha as not used and write whatever we like into it.
1138 const GLenum base_format
= irb
->Base
.Base
._BaseFormat
;
1139 const int components
= _mesa_base_format_component_count(base_format
);
1140 bool disables
= false;
1142 assert(components
> 0);
1144 for (int i
= 0; i
< components
; i
++) {
1145 color_write_disable
[i
] = !color_mask
[i
];
1146 disables
= disables
|| !color_mask
[i
];
1153 do_single_blorp_clear(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
1154 struct gl_renderbuffer
*rb
, unsigned buf
,
1155 bool partial_clear
, bool encode_srgb
)
1157 struct gl_context
*ctx
= &brw
->ctx
;
1158 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
1159 uint32_t x0
, x1
, y0
, y1
;
1161 mesa_format format
= irb
->Base
.Base
.Format
;
1162 if (!encode_srgb
&& _mesa_get_format_color_encoding(format
) == GL_SRGB
)
1163 format
= _mesa_get_srgb_format_linear(format
);
1164 enum isl_format isl_format
= brw
->mesa_to_isl_render_format
[format
];
1168 if (rb
->Name
!= 0) {
1172 y0
= rb
->Height
- fb
->_Ymax
;
1173 y1
= rb
->Height
- fb
->_Ymin
;
1176 /* If the clear region is empty, just return. */
1177 if (x0
== x1
|| y0
== y1
)
1180 bool can_fast_clear
= !partial_clear
;
1182 bool color_write_disable
[4] = { false, false, false, false };
1183 if (set_write_disables(irb
, ctx
->Color
.ColorMask
[buf
], color_write_disable
))
1184 can_fast_clear
= false;
1186 /* We store clear colors as floats or uints as needed. If there are
1187 * texture views in play, the formats will not properly be respected
1188 * during resolves because the resolve operations only know about the
1189 * miptree and not the renderbuffer.
1191 if (irb
->Base
.Base
.Format
!= irb
->mt
->format
)
1192 can_fast_clear
= false;
1194 if (!irb
->mt
->supports_fast_clear
||
1195 !brw_is_color_fast_clear_compatible(brw
, irb
->mt
, &ctx
->Color
.ClearColor
))
1196 can_fast_clear
= false;
1198 /* Surface state can only record one fast clear color value. Therefore
1199 * unless different levels/layers agree on the color it can be used to
1200 * represent only single level/layer. Here it will be reserved for the
1201 * first slice (level 0, layer 0).
1203 if (irb
->layer_count
> 1 || irb
->mt_level
|| irb
->mt_layer
)
1204 can_fast_clear
= false;
1206 unsigned level
= irb
->mt_level
;
1207 const unsigned num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1209 /* If the MCS buffer hasn't been allocated yet, we need to allocate it now.
1211 if (can_fast_clear
&& !irb
->mt
->mcs_buf
) {
1212 assert(irb
->mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1213 if (!intel_miptree_alloc_ccs(brw
, irb
->mt
)) {
1214 /* There are a few reasons in addition to out-of-memory, that can
1215 * cause intel_miptree_alloc_non_msrt_mcs to fail. Try to recover by
1216 * falling back to non-fast clear.
1218 can_fast_clear
= false;
1222 if (can_fast_clear
) {
1223 const enum isl_aux_state aux_state
=
1224 intel_miptree_get_aux_state(irb
->mt
, irb
->mt_level
, irb
->mt_layer
);
1225 union isl_color_value clear_color
=
1226 brw_meta_convert_fast_clear_color(brw
, irb
->mt
,
1227 &ctx
->Color
.ClearColor
);
1229 bool same_clear_color
=
1230 !intel_miptree_set_clear_color(ctx
, irb
->mt
, clear_color
);
1232 /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
1233 * is redundant and can be skipped.
1235 if (aux_state
== ISL_AUX_STATE_CLEAR
&& same_clear_color
)
1238 DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__
,
1239 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
1241 /* We can't setup the blorp_surf until we've allocated the MCS above */
1242 struct isl_surf isl_tmp
[2];
1243 struct blorp_surf surf
;
1244 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, irb
->mt
->aux_usage
, true,
1245 &level
, irb
->mt_layer
, num_layers
, isl_tmp
);
1247 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1249 * "Any transition from any value in {Clear, Render, Resolve} to a
1250 * different value in {Clear, Render, Resolve} requires end of pipe
1253 * In other words, fast clear ops are not properly synchronized with
1254 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1255 * contents of the previous draw hit the render target before we resolve
1256 * and again afterwards to ensure that the resolve is complete before we
1257 * do any more regular drawing.
1259 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1261 struct blorp_batch batch
;
1262 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1263 blorp_fast_clear(&batch
, &surf
, isl_format
,
1264 level
, irb
->mt_layer
, num_layers
,
1266 blorp_batch_finish(&batch
);
1268 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1270 /* Now that the fast clear has occurred, put the buffer in
1271 * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
1274 intel_miptree_set_aux_state(brw
, irb
->mt
, irb
->mt_level
,
1275 irb
->mt_layer
, num_layers
,
1276 ISL_AUX_STATE_CLEAR
);
1278 DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__
,
1279 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
1281 enum isl_aux_usage aux_usage
=
1282 intel_miptree_render_aux_usage(brw
, irb
->mt
, isl_format
, false);
1283 intel_miptree_prepare_render(brw
, irb
->mt
, level
, irb
->mt_layer
,
1284 num_layers
, isl_format
, false);
1286 struct isl_surf isl_tmp
[2];
1287 struct blorp_surf surf
;
1288 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, aux_usage
, true,
1289 &level
, irb
->mt_layer
, num_layers
, isl_tmp
);
1291 union isl_color_value clear_color
;
1292 memcpy(clear_color
.f32
, ctx
->Color
.ClearColor
.f
, sizeof(float) * 4);
1294 struct blorp_batch batch
;
1295 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1296 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
1297 level
, irb
->mt_layer
, num_layers
,
1299 clear_color
, color_write_disable
);
1300 blorp_batch_finish(&batch
);
1302 intel_miptree_finish_render(brw
, irb
->mt
, level
, irb
->mt_layer
,
1303 num_layers
, isl_format
, false);
1310 brw_blorp_clear_color(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
1311 GLbitfield mask
, bool partial_clear
, bool encode_srgb
)
1313 for (unsigned buf
= 0; buf
< fb
->_NumColorDrawBuffers
; buf
++) {
1314 struct gl_renderbuffer
*rb
= fb
->_ColorDrawBuffers
[buf
];
1315 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
1317 /* Only clear the buffers present in the provided mask */
1318 if (((1 << fb
->_ColorDrawBufferIndexes
[buf
]) & mask
) == 0)
1321 /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
1322 * the framebuffer can be complete with some attachments missing. In
1323 * this case the _ColorDrawBuffers pointer will be NULL.
1328 do_single_blorp_clear(brw
, fb
, rb
, buf
, partial_clear
, encode_srgb
);
1329 irb
->need_downsample
= true;
1336 brw_blorp_clear_depth_stencil(struct brw_context
*brw
,
1337 struct gl_framebuffer
*fb
,
1338 GLbitfield mask
, bool partial_clear
)
1340 const struct gl_context
*ctx
= &brw
->ctx
;
1341 struct gl_renderbuffer
*depth_rb
=
1342 fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
;
1343 struct gl_renderbuffer
*stencil_rb
=
1344 fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
1346 if (!depth_rb
|| ctx
->Depth
.Mask
== GL_FALSE
)
1347 mask
&= ~BUFFER_BIT_DEPTH
;
1349 if (!stencil_rb
|| (ctx
->Stencil
.WriteMask
[0] & 0xff) == 0)
1350 mask
&= ~BUFFER_BIT_STENCIL
;
1352 if (!(mask
& (BUFFER_BITS_DEPTH_STENCIL
)))
1355 uint32_t x0
, x1
, y0
, y1
, rb_name
, rb_height
;
1357 rb_name
= depth_rb
->Name
;
1358 rb_height
= depth_rb
->Height
;
1360 assert(depth_rb
->Width
== stencil_rb
->Width
);
1361 assert(depth_rb
->Height
== stencil_rb
->Height
);
1365 rb_name
= stencil_rb
->Name
;
1366 rb_height
= stencil_rb
->Height
;
1375 y0
= rb_height
- fb
->_Ymax
;
1376 y1
= rb_height
- fb
->_Ymin
;
1379 /* If the clear region is empty, just return. */
1380 if (x0
== x1
|| y0
== y1
)
1383 uint32_t level
, start_layer
, num_layers
;
1384 struct isl_surf isl_tmp
[4];
1385 struct blorp_surf depth_surf
, stencil_surf
;
1387 struct intel_mipmap_tree
*depth_mt
= NULL
;
1388 if (mask
& BUFFER_BIT_DEPTH
) {
1389 struct intel_renderbuffer
*irb
= intel_renderbuffer(depth_rb
);
1390 depth_mt
= find_miptree(GL_DEPTH_BUFFER_BIT
, irb
);
1392 level
= irb
->mt_level
;
1393 start_layer
= irb
->mt_layer
;
1394 num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1396 intel_miptree_prepare_depth(brw
, depth_mt
, level
,
1397 start_layer
, num_layers
);
1399 unsigned depth_level
= level
;
1400 blorp_surf_for_miptree(brw
, &depth_surf
, depth_mt
, depth_mt
->aux_usage
,
1401 true, &depth_level
, start_layer
, num_layers
,
1403 assert(depth_level
== level
);
1406 uint8_t stencil_mask
= 0;
1407 struct intel_mipmap_tree
*stencil_mt
= NULL
;
1408 if (mask
& BUFFER_BIT_STENCIL
) {
1409 struct intel_renderbuffer
*irb
= intel_renderbuffer(stencil_rb
);
1410 stencil_mt
= find_miptree(GL_STENCIL_BUFFER_BIT
, irb
);
1412 if (mask
& BUFFER_BIT_DEPTH
) {
1413 assert(level
== irb
->mt_level
);
1414 assert(start_layer
== irb
->mt_layer
);
1415 assert(num_layers
== fb
->MaxNumLayers
? irb
->layer_count
: 1);
1417 level
= irb
->mt_level
;
1418 start_layer
= irb
->mt_layer
;
1419 num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1422 stencil_mask
= ctx
->Stencil
.WriteMask
[0] & 0xff;
1424 intel_miptree_prepare_access(brw
, stencil_mt
, level
, 1,
1425 start_layer
, num_layers
,
1426 ISL_AUX_USAGE_NONE
, false);
1428 unsigned stencil_level
= level
;
1429 blorp_surf_for_miptree(brw
, &stencil_surf
, stencil_mt
,
1430 ISL_AUX_USAGE_NONE
, true,
1431 &stencil_level
, start_layer
, num_layers
,
1435 assert((mask
& BUFFER_BIT_DEPTH
) || stencil_mask
);
1437 struct blorp_batch batch
;
1438 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1439 blorp_clear_depth_stencil(&batch
, &depth_surf
, &stencil_surf
,
1440 level
, start_layer
, num_layers
,
1442 (mask
& BUFFER_BIT_DEPTH
), ctx
->Depth
.Clear
,
1443 stencil_mask
, ctx
->Stencil
.Clear
);
1444 blorp_batch_finish(&batch
);
1446 if (mask
& BUFFER_BIT_DEPTH
) {
1447 intel_miptree_finish_depth(brw
, depth_mt
, level
,
1448 start_layer
, num_layers
, true);
1452 intel_miptree_finish_write(brw
, stencil_mt
, level
,
1453 start_layer
, num_layers
,
1454 ISL_AUX_USAGE_NONE
);
1459 brw_blorp_resolve_color(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1460 unsigned level
, unsigned layer
,
1461 enum blorp_fast_clear_op resolve_op
)
1463 DBG("%s to mt %p level %u layer %u\n", __FUNCTION__
, mt
, level
, layer
);
1465 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
1467 struct isl_surf isl_tmp
[1];
1468 struct blorp_surf surf
;
1469 blorp_surf_for_miptree(brw
, &surf
, mt
, mt
->aux_usage
, true,
1470 &level
, layer
, 1 /* num_layers */,
1473 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1475 * "Any transition from any value in {Clear, Render, Resolve} to a
1476 * different value in {Clear, Render, Resolve} requires end of pipe
1479 * In other words, fast clear ops are not properly synchronized with
1480 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1481 * contents of the previous draw hit the render target before we resolve
1482 * and again afterwards to ensure that the resolve is complete before we
1483 * do any more regular drawing.
1485 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1488 struct blorp_batch batch
;
1489 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1490 blorp_ccs_resolve(&batch
, &surf
, level
, layer
,
1491 brw_blorp_to_isl_format(brw
, format
, true),
1493 blorp_batch_finish(&batch
);
1495 /* See comment above */
1496 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1500 brw_blorp_mcs_partial_resolve(struct brw_context
*brw
,
1501 struct intel_mipmap_tree
*mt
,
1502 uint32_t start_layer
, uint32_t num_layers
)
1504 DBG("%s to mt %p layers %u-%u\n", __FUNCTION__
, mt
,
1505 start_layer
, start_layer
+ num_layers
- 1);
1507 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1509 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
1510 enum isl_format isl_format
= brw_blorp_to_isl_format(brw
, format
, true);
1512 struct isl_surf isl_tmp
[1];
1513 struct blorp_surf surf
;
1515 blorp_surf_for_miptree(brw
, &surf
, mt
, ISL_AUX_USAGE_MCS
, true,
1516 &level
, start_layer
, num_layers
, isl_tmp
);
1518 struct blorp_batch batch
;
1519 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1520 blorp_mcs_partial_resolve(&batch
, &surf
, isl_format
,
1521 start_layer
, num_layers
);
1522 blorp_batch_finish(&batch
);
1526 * Perform a HiZ or depth resolve operation.
1528 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
1529 * PRM, Volume 1, Part 2:
1530 * - 7.5.3.1 Depth Buffer Clear
1531 * - 7.5.3.2 Depth Buffer Resolve
1532 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1535 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1536 unsigned int level
, unsigned int start_layer
,
1537 unsigned int num_layers
, enum blorp_hiz_op op
)
1539 assert(intel_miptree_level_has_hiz(mt
, level
));
1540 assert(op
!= BLORP_HIZ_OP_NONE
);
1541 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1542 const char *opname
= NULL
;
1545 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
1546 opname
= "depth resolve";
1548 case BLORP_HIZ_OP_HIZ_RESOLVE
:
1549 opname
= "hiz ambiguate";
1551 case BLORP_HIZ_OP_DEPTH_CLEAR
:
1552 opname
= "depth clear";
1554 case BLORP_HIZ_OP_NONE
:
1559 DBG("%s %s to mt %p level %d layers %d-%d\n",
1560 __func__
, opname
, mt
, level
, start_layer
, start_layer
+ num_layers
- 1);
1562 /* The following stalls and flushes are only documented to be required for
1563 * HiZ clear operations. However, they also seem to be required for
1564 * resolve operations.
1566 if (devinfo
->gen
== 6) {
1567 /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
1569 * "If other rendering operations have preceded this clear, a
1570 * PIPE_CONTROL with write cache flush enabled and Z-inhibit
1571 * disabled must be issued before the rectangle primitive used for
1572 * the depth buffer clear operation.
1574 brw_emit_pipe_control_flush(brw
,
1575 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1576 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1577 PIPE_CONTROL_CS_STALL
);
1578 } else if (devinfo
->gen
>= 7) {
1580 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
1582 * If other rendering operations have preceded this clear, a
1583 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
1584 * enabled must be issued before the rectangle primitive used for
1585 * the depth buffer clear operation.
1587 * Same applies for Gen8 and Gen9.
1589 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
1590 * PIPE_CONTROL, Depth Cache Flush Enable:
1592 * This bit must not be set when Depth Stall Enable bit is set in
1595 * This is confirmed to hold for real, HSW gets immediate gpu hangs.
1597 * Therefore issue two pipe control flushes, one for cache flush and
1598 * another for depth stall.
1600 brw_emit_pipe_control_flush(brw
,
1601 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1602 PIPE_CONTROL_CS_STALL
);
1604 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
1607 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
&& mt
->hiz_buf
);
1609 struct isl_surf isl_tmp
[2];
1610 struct blorp_surf surf
;
1611 blorp_surf_for_miptree(brw
, &surf
, mt
, ISL_AUX_USAGE_HIZ
, true,
1612 &level
, start_layer
, num_layers
, isl_tmp
);
1614 struct blorp_batch batch
;
1615 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1616 blorp_hiz_op(&batch
, &surf
, level
, start_layer
, num_layers
, op
);
1617 blorp_batch_finish(&batch
);
1619 /* The following stalls and flushes are only documented to be required for
1620 * HiZ clear operations. However, they also seem to be required for
1621 * resolve operations.
1623 if (devinfo
->gen
== 6) {
1624 /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
1626 * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be
1627 * followed by a PIPE_CONTROL command with DEPTH_STALL bit set
1628 * and Then followed by Depth FLUSH'
1630 brw_emit_pipe_control_flush(brw
,
1631 PIPE_CONTROL_DEPTH_STALL
);
1633 brw_emit_pipe_control_flush(brw
,
1634 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1635 PIPE_CONTROL_CS_STALL
);
1636 } else if (devinfo
->gen
>= 8) {
1638 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
1640 * "Depth buffer clear pass using any of the methods (WM_STATE,
1641 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
1642 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
1643 * "set" before starting to render. DepthStall and DepthFlush are
1644 * not needed between consecutive depth clear passes nor is it
1645 * required if the depth clear pass was done with
1646 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
1648 * TODO: Such as the spec says, this could be conditional.
1650 brw_emit_pipe_control_flush(brw
,
1651 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1652 PIPE_CONTROL_DEPTH_STALL
);