2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/blend.h"
27 #include "main/bufferobj.h"
28 #include "main/enums.h"
29 #include "main/fbobject.h"
30 #include "main/image.h"
31 #include "main/renderbuffer.h"
32 #include "main/glformats.h"
34 #include "brw_blorp.h"
35 #include "brw_context.h"
36 #include "brw_defines.h"
37 #include "brw_meta_util.h"
38 #include "brw_state.h"
39 #include "intel_buffer_objects.h"
40 #include "intel_fbo.h"
41 #include "common/gen_debug.h"
43 #define FILE_DEBUG_FLAG DEBUG_BLORP
46 brw_blorp_lookup_shader(struct blorp_context
*blorp
,
47 const void *key
, uint32_t key_size
,
48 uint32_t *kernel_out
, void *prog_data_out
)
50 struct brw_context
*brw
= blorp
->driver_ctx
;
51 return brw_search_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
, key
, key_size
,
52 kernel_out
, prog_data_out
, true);
56 brw_blorp_upload_shader(struct blorp_context
*blorp
,
57 const void *key
, uint32_t key_size
,
58 const void *kernel
, uint32_t kernel_size
,
59 const struct brw_stage_prog_data
*prog_data
,
60 uint32_t prog_data_size
,
61 uint32_t *kernel_out
, void *prog_data_out
)
63 struct brw_context
*brw
= blorp
->driver_ctx
;
64 brw_upload_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
, key
, key_size
,
65 kernel
, kernel_size
, prog_data
, prog_data_size
,
66 kernel_out
, prog_data_out
);
71 brw_blorp_init(struct brw_context
*brw
)
73 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
75 blorp_init(&brw
->blorp
, brw
, &brw
->isl_dev
);
77 brw
->blorp
.compiler
= brw
->screen
->compiler
;
79 switch (devinfo
->gen
) {
81 if (devinfo
->is_g4x
) {
82 brw
->blorp
.exec
= gen45_blorp_exec
;
84 brw
->blorp
.exec
= gen4_blorp_exec
;
88 brw
->blorp
.exec
= gen5_blorp_exec
;
91 brw
->blorp
.exec
= gen6_blorp_exec
;
94 if (devinfo
->is_haswell
) {
95 brw
->blorp
.exec
= gen75_blorp_exec
;
97 brw
->blorp
.exec
= gen7_blorp_exec
;
101 brw
->blorp
.exec
= gen8_blorp_exec
;
104 brw
->blorp
.exec
= gen9_blorp_exec
;
107 brw
->blorp
.exec
= gen10_blorp_exec
;
110 brw
->blorp
.exec
= gen11_blorp_exec
;
114 unreachable("Invalid gen");
117 brw
->blorp
.lookup_shader
= brw_blorp_lookup_shader
;
118 brw
->blorp
.upload_shader
= brw_blorp_upload_shader
;
122 blorp_surf_for_miptree(struct brw_context
*brw
,
123 struct blorp_surf
*surf
,
124 const struct intel_mipmap_tree
*mt
,
125 enum isl_aux_usage aux_usage
,
126 bool is_render_target
,
128 unsigned start_layer
, unsigned num_layers
,
129 struct isl_surf tmp_surfs
[1])
131 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
133 if (mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
) {
134 const unsigned num_samples
= mt
->surf
.samples
;
135 for (unsigned i
= 0; i
< num_layers
; i
++) {
136 for (unsigned s
= 0; s
< num_samples
; s
++) {
137 const unsigned phys_layer
= (start_layer
+ i
) * num_samples
+ s
;
138 intel_miptree_check_level_layer(mt
, *level
, phys_layer
);
142 for (unsigned i
= 0; i
< num_layers
; i
++)
143 intel_miptree_check_level_layer(mt
, *level
, start_layer
+ i
);
146 *surf
= (struct blorp_surf
) {
148 .addr
= (struct blorp_address
) {
150 .offset
= mt
->offset
,
151 .reloc_flags
= is_render_target
? EXEC_OBJECT_WRITE
: 0,
152 .mocs
= brw_get_bo_mocs(devinfo
, mt
->bo
),
154 .aux_usage
= aux_usage
,
155 .tile_x_sa
= mt
->level
[*level
].level_x
,
156 .tile_y_sa
= mt
->level
[*level
].level_y
,
159 if (surf
->aux_usage
== ISL_AUX_USAGE_HIZ
&&
160 !intel_miptree_level_has_hiz(mt
, *level
))
161 surf
->aux_usage
= ISL_AUX_USAGE_NONE
;
163 if (surf
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
164 /* We only really need a clear color if we also have an auxiliary
165 * surface. Without one, it does nothing.
168 intel_miptree_get_clear_color(devinfo
, mt
, mt
->surf
.format
,
169 !is_render_target
, (struct brw_bo
**)
170 &surf
->clear_color_addr
.buffer
,
171 &surf
->clear_color_addr
.offset
);
173 surf
->aux_surf
= &mt
->aux_buf
->surf
;
174 surf
->aux_addr
= (struct blorp_address
) {
175 .reloc_flags
= is_render_target
? EXEC_OBJECT_WRITE
: 0,
176 .mocs
= surf
->addr
.mocs
,
179 surf
->aux_addr
.buffer
= mt
->aux_buf
->bo
;
180 surf
->aux_addr
.offset
= mt
->aux_buf
->offset
;
182 surf
->aux_addr
= (struct blorp_address
) {
185 memset(&surf
->clear_color
, 0, sizeof(surf
->clear_color
));
187 assert((surf
->aux_usage
== ISL_AUX_USAGE_NONE
) ==
188 (surf
->aux_addr
.buffer
== NULL
));
190 /* ISL wants real levels, not offset ones. */
191 *level
-= mt
->first_level
;
195 brw_blorp_supports_dst_format(struct brw_context
*brw
, mesa_format format
)
197 /* If it's renderable, it's definitely supported. */
198 if (brw
->mesa_format_supports_render
[format
])
201 /* BLORP can't compress anything */
202 if (_mesa_is_format_compressed(format
))
205 /* No exotic formats such as GL_LUMINANCE_ALPHA */
206 if (_mesa_get_format_bits(format
, GL_RED_BITS
) == 0 &&
207 _mesa_get_format_bits(format
, GL_DEPTH_BITS
) == 0 &&
208 _mesa_get_format_bits(format
, GL_STENCIL_BITS
) == 0)
214 static enum isl_format
215 brw_blorp_to_isl_format(struct brw_context
*brw
, mesa_format format
,
216 bool is_render_target
)
219 case MESA_FORMAT_NONE
:
220 return ISL_FORMAT_UNSUPPORTED
;
221 case MESA_FORMAT_S_UINT8
:
222 return ISL_FORMAT_R8_UINT
;
223 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
224 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
225 return ISL_FORMAT_R24_UNORM_X8_TYPELESS
;
226 case MESA_FORMAT_Z_FLOAT32
:
227 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
228 return ISL_FORMAT_R32_FLOAT
;
229 case MESA_FORMAT_Z_UNORM16
:
230 return ISL_FORMAT_R16_UNORM
;
232 if (is_render_target
) {
233 assert(brw_blorp_supports_dst_format(brw
, format
));
234 if (brw
->mesa_format_supports_render
[format
]) {
235 return brw
->mesa_to_isl_render_format
[format
];
237 return brw_isl_format_for_mesa_format(format
);
240 /* Some destinations (is_render_target == true) are supported by
241 * blorp even though we technically can't render to them.
243 return brw_isl_format_for_mesa_format(format
);
249 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
250 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
252 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
255 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
257 * which is simply adding 4 then modding by 8 (or anding with 7).
259 * We then may need to apply workarounds for textureGather hardware bugs.
261 static enum isl_channel_select
262 swizzle_to_scs(GLenum swizzle
)
264 return (enum isl_channel_select
)((swizzle
+ 4) & 7);
268 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
269 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
270 * the physical layer holding sample 0. So, for example, if
271 * src_mt->surf.samples == 4, then logical layer n corresponds to src_layer ==
275 brw_blorp_blit_miptrees(struct brw_context
*brw
,
276 struct intel_mipmap_tree
*src_mt
,
277 unsigned src_level
, unsigned src_layer
,
278 mesa_format src_format
, int src_swizzle
,
279 struct intel_mipmap_tree
*dst_mt
,
280 unsigned dst_level
, unsigned dst_layer
,
281 mesa_format dst_format
,
282 float src_x0
, float src_y0
,
283 float src_x1
, float src_y1
,
284 float dst_x0
, float dst_y0
,
285 float dst_x1
, float dst_y1
,
286 GLenum gl_filter
, bool mirror_x
, bool mirror_y
,
287 bool decode_srgb
, bool encode_srgb
)
289 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
291 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f) "
292 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
294 src_mt
->surf
.samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
295 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
296 dst_mt
->surf
.samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
297 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
300 if (!decode_srgb
&& _mesa_get_format_color_encoding(src_format
) == GL_SRGB
)
301 src_format
= _mesa_get_srgb_format_linear(src_format
);
303 if (!encode_srgb
&& _mesa_get_format_color_encoding(dst_format
) == GL_SRGB
)
304 dst_format
= _mesa_get_srgb_format_linear(dst_format
);
306 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
307 * texture, the above code configures the source format for L32_FLOAT or
308 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
309 * the SAMPLE message appears to handle multisampled L32_FLOAT and
310 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
311 * around the problem by using a source format of R32_FLOAT. This
312 * shouldn't affect rendering correctness, since the destination format is
313 * R32_FLOAT, so only the contents of the red channel matters.
315 if (devinfo
->gen
== 6 &&
316 src_mt
->surf
.samples
> 1 && dst_mt
->surf
.samples
<= 1 &&
317 src_mt
->format
== dst_mt
->format
&&
318 (dst_format
== MESA_FORMAT_L_FLOAT32
||
319 dst_format
== MESA_FORMAT_I_FLOAT32
)) {
320 src_format
= dst_format
= MESA_FORMAT_R_FLOAT32
;
323 enum blorp_filter blorp_filter
;
324 if (fabsf(dst_x1
- dst_x0
) == fabsf(src_x1
- src_x0
) &&
325 fabsf(dst_y1
- dst_y0
) == fabsf(src_y1
- src_y0
)) {
326 if (src_mt
->surf
.samples
> 1 && dst_mt
->surf
.samples
<= 1) {
327 /* From the OpenGL ES 3.2 specification, section 16.2.1:
329 * "If the read framebuffer is multisampled (its effective value
330 * of SAMPLE_BUFFERS is one) and the draw framebuffer is not (its
331 * value of SAMPLE_BUFFERS is zero), the samples corresponding to
332 * each pixel location in the source are converted to a single
333 * sample before being written to the destination. The filter
334 * parameter is ignored. If the source formats are integer types
335 * or stencil values, a single sample’s value is selected for each
336 * pixel. If the source formats are floating-point or normalized
337 * types, the sample values for each pixel are resolved in an
338 * implementation-dependent manner. If the source formats are
339 * depth values, sample values are resolved in an implementation-
340 * dependent manner where the result will be between the minimum
341 * and maximum depth values in the pixel."
343 * For depth and stencil resolves, we choose to always use the value
346 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
347 if (base_format
== GL_DEPTH_COMPONENT
||
348 base_format
== GL_STENCIL_INDEX
||
349 base_format
== GL_DEPTH_STENCIL
||
350 _mesa_is_format_integer(src_mt
->format
)) {
351 /* The OpenGL ES 3.2 spec says:
353 * "If the source formats are integer types or stencil values,
354 * a single sample's value is selected for each pixel."
356 * Just take sample 0 in this case.
358 blorp_filter
= BLORP_FILTER_SAMPLE_0
;
360 blorp_filter
= BLORP_FILTER_AVERAGE
;
363 /* From the OpenGL 4.6 specification, section 18.3.1:
365 * "If the source and destination dimensions are identical, no
366 * filtering is applied."
368 * Using BLORP_FILTER_NONE will also handle the upsample case by
369 * replicating the one value in the source to all values in the
372 blorp_filter
= BLORP_FILTER_NONE
;
374 } else if (gl_filter
== GL_LINEAR
||
375 gl_filter
== GL_SCALED_RESOLVE_FASTEST_EXT
||
376 gl_filter
== GL_SCALED_RESOLVE_NICEST_EXT
) {
377 blorp_filter
= BLORP_FILTER_BILINEAR
;
379 blorp_filter
= BLORP_FILTER_NEAREST
;
382 enum isl_format src_isl_format
=
383 brw_blorp_to_isl_format(brw
, src_format
, false);
384 enum isl_aux_usage src_aux_usage
=
385 intel_miptree_texture_aux_usage(brw
, src_mt
, src_isl_format
);
386 /* We do format workarounds for some depth formats so we can't reliably
387 * sample with HiZ. One of these days, we should fix that.
389 if (src_aux_usage
== ISL_AUX_USAGE_HIZ
)
390 src_aux_usage
= ISL_AUX_USAGE_NONE
;
391 const bool src_clear_supported
=
392 src_aux_usage
!= ISL_AUX_USAGE_NONE
&& src_mt
->format
== src_format
;
393 intel_miptree_prepare_access(brw
, src_mt
, src_level
, 1, src_layer
, 1,
394 src_aux_usage
, src_clear_supported
);
396 enum isl_format dst_isl_format
=
397 brw_blorp_to_isl_format(brw
, dst_format
, true);
398 enum isl_aux_usage dst_aux_usage
=
399 intel_miptree_render_aux_usage(brw
, dst_mt
, dst_isl_format
,
401 const bool dst_clear_supported
= dst_aux_usage
!= ISL_AUX_USAGE_NONE
;
402 intel_miptree_prepare_access(brw
, dst_mt
, dst_level
, 1, dst_layer
, 1,
403 dst_aux_usage
, dst_clear_supported
);
405 struct isl_surf tmp_surfs
[2];
406 struct blorp_surf src_surf
, dst_surf
;
407 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, src_aux_usage
, false,
408 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
409 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, dst_aux_usage
, true,
410 &dst_level
, dst_layer
, 1, &tmp_surfs
[1]);
412 struct isl_swizzle src_isl_swizzle
= {
413 .r
= swizzle_to_scs(GET_SWZ(src_swizzle
, 0)),
414 .g
= swizzle_to_scs(GET_SWZ(src_swizzle
, 1)),
415 .b
= swizzle_to_scs(GET_SWZ(src_swizzle
, 2)),
416 .a
= swizzle_to_scs(GET_SWZ(src_swizzle
, 3)),
419 struct blorp_batch batch
;
420 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
421 blorp_blit(&batch
, &src_surf
, src_level
, src_layer
,
422 src_isl_format
, src_isl_swizzle
,
423 &dst_surf
, dst_level
, dst_layer
,
424 dst_isl_format
, ISL_SWIZZLE_IDENTITY
,
425 src_x0
, src_y0
, src_x1
, src_y1
,
426 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
427 blorp_filter
, mirror_x
, mirror_y
);
428 blorp_batch_finish(&batch
);
430 intel_miptree_finish_write(brw
, dst_mt
, dst_level
, dst_layer
, 1,
435 brw_blorp_copy_miptrees(struct brw_context
*brw
,
436 struct intel_mipmap_tree
*src_mt
,
437 unsigned src_level
, unsigned src_layer
,
438 struct intel_mipmap_tree
*dst_mt
,
439 unsigned dst_level
, unsigned dst_layer
,
440 unsigned src_x
, unsigned src_y
,
441 unsigned dst_x
, unsigned dst_y
,
442 unsigned src_width
, unsigned src_height
)
444 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
446 DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
447 "to %dx %s mt %p %d %d (%d,%d)\n",
449 src_mt
->surf
.samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
450 src_level
, src_layer
, src_x
, src_y
, src_width
, src_height
,
451 dst_mt
->surf
.samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
452 dst_level
, dst_layer
, dst_x
, dst_y
);
454 enum isl_aux_usage src_aux_usage
, dst_aux_usage
;
455 bool src_clear_supported
, dst_clear_supported
;
457 switch (src_mt
->aux_usage
) {
458 case ISL_AUX_USAGE_MCS
:
459 case ISL_AUX_USAGE_CCS_E
:
460 src_aux_usage
= src_mt
->aux_usage
;
461 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
462 * we're going to re-interpret the format as an integer format possibly
463 * with a different number of components, we can't handle clear colors
466 src_clear_supported
= devinfo
->gen
>= 9;
469 src_aux_usage
= ISL_AUX_USAGE_NONE
;
470 src_clear_supported
= false;
474 switch (dst_mt
->aux_usage
) {
475 case ISL_AUX_USAGE_MCS
:
476 case ISL_AUX_USAGE_CCS_E
:
477 dst_aux_usage
= dst_mt
->aux_usage
;
478 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
479 * we're going to re-interpret the format as an integer format possibly
480 * with a different number of components, we can't handle clear colors
483 dst_clear_supported
= devinfo
->gen
>= 9;
486 dst_aux_usage
= ISL_AUX_USAGE_NONE
;
487 dst_clear_supported
= false;
491 intel_miptree_prepare_access(brw
, src_mt
, src_level
, 1, src_layer
, 1,
492 src_aux_usage
, src_clear_supported
);
493 intel_miptree_prepare_access(brw
, dst_mt
, dst_level
, 1, dst_layer
, 1,
494 dst_aux_usage
, dst_clear_supported
);
496 struct isl_surf tmp_surfs
[2];
497 struct blorp_surf src_surf
, dst_surf
;
498 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, src_aux_usage
, false,
499 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
500 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, dst_aux_usage
, true,
501 &dst_level
, dst_layer
, 1, &tmp_surfs
[1]);
503 /* The hardware seems to have issues with having a two different format
504 * views of the same texture in the sampler cache at the same time. It's
505 * unclear exactly what the issue is but it hurts glCopyImageSubData
506 * particularly badly because it does a lot of format reinterprets. We
507 * badly need better understanding of the issue and a better fix but this
508 * works for now and fixes CTS tests.
510 * TODO: Remove this hack!
512 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
|
513 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
515 struct blorp_batch batch
;
516 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
517 blorp_copy(&batch
, &src_surf
, src_level
, src_layer
,
518 &dst_surf
, dst_level
, dst_layer
,
519 src_x
, src_y
, dst_x
, dst_y
, src_width
, src_height
);
520 blorp_batch_finish(&batch
);
522 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
|
523 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
525 intel_miptree_finish_write(brw
, dst_mt
, dst_level
, dst_layer
, 1,
530 brw_blorp_copy_buffers(struct brw_context
*brw
,
531 struct brw_bo
*src_bo
,
533 struct brw_bo
*dst_bo
,
537 DBG("%s %d bytes from %p[%d] to %p[%d]",
538 __func__
, size
, src_bo
, src_offset
, dst_bo
, dst_offset
);
540 struct blorp_batch batch
;
541 struct blorp_address src
= { .buffer
= src_bo
, .offset
= src_offset
};
542 struct blorp_address dst
= { .buffer
= dst_bo
, .offset
= dst_offset
};
544 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
545 blorp_buffer_copy(&batch
, src
, dst
, size
);
546 blorp_batch_finish(&batch
);
550 static struct intel_mipmap_tree
*
551 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
553 struct intel_mipmap_tree
*mt
= irb
->mt
;
554 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
560 blorp_get_texture_swizzle(const struct intel_renderbuffer
*irb
)
562 return irb
->Base
.Base
._BaseFormat
== GL_RGB
?
563 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ONE
) :
568 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
569 struct intel_renderbuffer
*src_irb
, mesa_format src_format
,
570 struct intel_renderbuffer
*dst_irb
, mesa_format dst_format
,
571 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
572 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
573 GLenum filter
, bool mirror_x
, bool mirror_y
)
575 const struct gl_context
*ctx
= &brw
->ctx
;
577 /* Find source/dst miptrees */
578 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
579 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
581 const bool do_srgb
= ctx
->Color
.sRGBEnabled
;
584 brw_blorp_blit_miptrees(brw
,
585 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
586 src_format
, blorp_get_texture_swizzle(src_irb
),
587 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
589 srcX0
, srcY0
, srcX1
, srcY1
,
590 dstX0
, dstY0
, dstX1
, dstY1
,
591 filter
, mirror_x
, mirror_y
,
594 dst_irb
->need_downsample
= true;
598 try_blorp_blit(struct brw_context
*brw
,
599 const struct gl_framebuffer
*read_fb
,
600 const struct gl_framebuffer
*draw_fb
,
601 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
602 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
603 GLenum filter
, GLbitfield buffer_bit
)
605 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
606 struct gl_context
*ctx
= &brw
->ctx
;
608 /* Sync up the state of window system buffers. We need to do this before
609 * we go looking for the buffers.
611 intel_prepare_render(brw
);
613 bool mirror_x
, mirror_y
;
614 if (brw_meta_mirror_clip_and_scissor(ctx
, read_fb
, draw_fb
,
615 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
616 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
617 &mirror_x
, &mirror_y
))
621 struct intel_renderbuffer
*src_irb
;
622 struct intel_renderbuffer
*dst_irb
;
623 struct intel_mipmap_tree
*src_mt
;
624 struct intel_mipmap_tree
*dst_mt
;
625 switch (buffer_bit
) {
626 case GL_COLOR_BUFFER_BIT
:
627 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
628 for (unsigned i
= 0; i
< draw_fb
->_NumColorDrawBuffers
; ++i
) {
629 dst_irb
= intel_renderbuffer(draw_fb
->_ColorDrawBuffers
[i
]);
631 do_blorp_blit(brw
, buffer_bit
,
632 src_irb
, src_irb
->Base
.Base
.Format
,
633 dst_irb
, dst_irb
->Base
.Base
.Format
,
634 srcX0
, srcY0
, srcX1
, srcY1
,
635 dstX0
, dstY0
, dstX1
, dstY1
,
636 filter
, mirror_x
, mirror_y
);
639 case GL_DEPTH_BUFFER_BIT
:
641 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
643 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
644 src_mt
= find_miptree(buffer_bit
, src_irb
);
645 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
647 /* We also can't handle any combined depth-stencil formats because we
648 * have to reinterpret as a color format.
650 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
651 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
654 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
655 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
656 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
657 filter
, mirror_x
, mirror_y
);
659 case GL_STENCIL_BUFFER_BIT
:
660 /* Blorp doesn't support combined depth stencil which is all we have
663 if (devinfo
->gen
< 6)
667 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
669 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
670 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
671 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
672 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
673 filter
, mirror_x
, mirror_y
);
676 unreachable("not reached");
683 apply_y_flip(int *y0
, int *y1
, int height
)
685 int tmp
= height
- *y0
;
691 brw_blorp_copytexsubimage(struct brw_context
*brw
,
692 struct gl_renderbuffer
*src_rb
,
693 struct gl_texture_image
*dst_image
,
695 int srcX0
, int srcY0
,
696 int dstX0
, int dstY0
,
697 int width
, int height
)
699 struct gl_context
*ctx
= &brw
->ctx
;
700 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
701 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
703 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
704 if (brw
->ctx
._ImageTransferState
)
707 /* Sync up the state of window system buffers. We need to do this before
708 * we go looking at the src renderbuffer's miptree.
710 intel_prepare_render(brw
);
712 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
713 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
715 /* We can't handle any combined depth-stencil formats because we have to
716 * reinterpret as a color format.
718 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
719 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
722 if (!brw_blorp_supports_dst_format(brw
, dst_image
->TexFormat
))
725 /* Source clipping shouldn't be necessary, since copytexsubimage (in
726 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
729 * Destination clipping shouldn't be necessary since the restrictions on
730 * glCopyTexSubImage prevent the user from specifying a destination rectangle
731 * that falls outside the bounds of the destination texture.
732 * See error_check_subtexture_dimensions().
735 int srcY1
= srcY0
+ height
;
736 int srcX1
= srcX0
+ width
;
737 int dstX1
= dstX0
+ width
;
738 int dstY1
= dstY0
+ height
;
740 /* Account for the fact that in the system framebuffer, the origin is at
743 bool mirror_y
= ctx
->ReadBuffer
->FlipY
;
745 apply_y_flip(&srcY0
, &srcY1
, src_rb
->Height
);
747 /* Account for face selection and texture view MinLayer */
748 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
749 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
751 brw_blorp_blit_miptrees(brw
,
752 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
753 src_rb
->Format
, blorp_get_texture_swizzle(src_irb
),
754 dst_mt
, dst_level
, dst_slice
,
755 dst_image
->TexFormat
,
756 srcX0
, srcY0
, srcX1
, srcY1
,
757 dstX0
, dstY0
, dstX1
, dstY1
,
758 GL_NEAREST
, false, mirror_y
,
761 /* If we're copying to a packed depth stencil texture and the source
762 * framebuffer has separate stencil, we need to also copy the stencil data
765 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
766 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
768 src_irb
= intel_renderbuffer(src_rb
);
769 src_mt
= src_irb
->mt
;
771 if (src_mt
->stencil_mt
)
772 src_mt
= src_mt
->stencil_mt
;
773 if (dst_mt
->stencil_mt
)
774 dst_mt
= dst_mt
->stencil_mt
;
776 if (src_mt
!= dst_mt
) {
777 brw_blorp_blit_miptrees(brw
,
778 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
780 blorp_get_texture_swizzle(src_irb
),
781 dst_mt
, dst_level
, dst_slice
,
783 srcX0
, srcY0
, srcX1
, srcY1
,
784 dstX0
, dstY0
, dstX1
, dstY1
,
785 GL_NEAREST
, false, mirror_y
,
795 brw_blorp_framebuffer(struct brw_context
*brw
,
796 struct gl_framebuffer
*readFb
,
797 struct gl_framebuffer
*drawFb
,
798 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
799 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
800 GLbitfield mask
, GLenum filter
)
802 static GLbitfield buffer_bits
[] = {
805 GL_STENCIL_BUFFER_BIT
,
808 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
809 if ((mask
& buffer_bits
[i
]) &&
810 try_blorp_blit(brw
, readFb
, drawFb
,
811 srcX0
, srcY0
, srcX1
, srcY1
,
812 dstX0
, dstY0
, dstX1
, dstY1
,
813 filter
, buffer_bits
[i
])) {
814 mask
&= ~buffer_bits
[i
];
821 static struct brw_bo
*
822 blorp_get_client_bo(struct brw_context
*brw
,
823 unsigned w
, unsigned h
, unsigned d
,
824 GLenum target
, GLenum format
, GLenum type
,
826 const struct gl_pixelstore_attrib
*packing
,
827 uint32_t *offset_out
, uint32_t *row_stride_out
,
828 uint32_t *image_stride_out
, bool read_only
)
830 /* Account for SKIP_PIXELS, SKIP_ROWS, ALIGNMENT, and SKIP_IMAGES */
831 const GLuint dims
= _mesa_get_texture_dimensions(target
);
832 const uint32_t first_pixel
= _mesa_image_offset(dims
, packing
, w
, h
,
833 format
, type
, 0, 0, 0);
834 const uint32_t last_pixel
= _mesa_image_offset(dims
, packing
, w
, h
,
837 const uint32_t stride
= _mesa_image_row_stride(packing
, w
, format
, type
);
838 const uint32_t cpp
= _mesa_bytes_per_pixel(format
, type
);
839 const uint32_t size
= last_pixel
- first_pixel
;
841 *row_stride_out
= stride
;
842 *image_stride_out
= _mesa_image_image_stride(packing
, w
, h
, format
, type
);
844 if (_mesa_is_bufferobj(packing
->BufferObj
)) {
845 const uint32_t offset
= first_pixel
+ (intptr_t)pixels
;
846 if (!read_only
&& ((offset
% cpp
) || (stride
% cpp
))) {
847 perf_debug("Bad PBO alignment; fallback to CPU mapping\n");
851 /* This is a user-provided PBO. We just need to get the BO out */
852 struct intel_buffer_object
*intel_pbo
=
853 intel_buffer_object(packing
->BufferObj
);
855 intel_bufferobj_buffer(brw
, intel_pbo
, offset
, size
, !read_only
);
857 /* We take a reference to the BO so that the caller can just always
858 * unref without having to worry about whether it's a user PBO or one
861 brw_bo_reference(bo
);
863 *offset_out
= offset
;
866 /* Someone should have already checked that there is data to upload. */
869 /* Creating a temp buffer currently only works for upload */
872 /* This is not a user-provided PBO. Instead, pixels is a pointer to CPU
873 * data which we need to copy into a BO.
876 brw_bo_alloc(brw
->bufmgr
, "tmp_tex_subimage_src", size
,
879 perf_debug("intel_texsubimage: temp bo creation failed: size = %u\n",
884 if (brw_bo_subdata(bo
, 0, size
, pixels
+ first_pixel
)) {
885 perf_debug("intel_texsubimage: temp bo upload failed\n");
886 brw_bo_unreference(bo
);
895 /* Consider all the restrictions and determine the format of the source. */
897 blorp_get_client_format(struct brw_context
*brw
,
898 GLenum format
, GLenum type
,
899 const struct gl_pixelstore_attrib
*packing
)
901 if (brw
->ctx
._ImageTransferState
)
902 return MESA_FORMAT_NONE
;
904 if (packing
->SwapBytes
|| packing
->LsbFirst
|| packing
->Invert
) {
905 perf_debug("intel_texsubimage_blorp: unsupported gl_pixelstore_attrib\n");
906 return MESA_FORMAT_NONE
;
909 if (format
!= GL_RED
&&
915 format
!= GL_ALPHA
&&
916 format
!= GL_RED_INTEGER
&&
917 format
!= GL_RG_INTEGER
&&
918 format
!= GL_RGB_INTEGER
&&
919 format
!= GL_BGR_INTEGER
&&
920 format
!= GL_RGBA_INTEGER
&&
921 format
!= GL_BGRA_INTEGER
) {
922 perf_debug("intel_texsubimage_blorp: %s not supported",
923 _mesa_enum_to_string(format
));
924 return MESA_FORMAT_NONE
;
927 return _mesa_tex_format_from_format_and_type(&brw
->ctx
, format
, type
);
931 need_signed_unsigned_int_conversion(mesa_format src_format
,
932 mesa_format dst_format
)
934 const GLenum src_type
= _mesa_get_format_datatype(src_format
);
935 const GLenum dst_type
= _mesa_get_format_datatype(dst_format
);
936 return (src_type
== GL_INT
&& dst_type
== GL_UNSIGNED_INT
) ||
937 (src_type
== GL_UNSIGNED_INT
&& dst_type
== GL_INT
);
941 brw_blorp_upload_miptree(struct brw_context
*brw
,
942 struct intel_mipmap_tree
*dst_mt
,
943 mesa_format dst_format
,
944 uint32_t level
, uint32_t x
, uint32_t y
, uint32_t z
,
945 uint32_t width
, uint32_t height
, uint32_t depth
,
946 GLenum target
, GLenum format
, GLenum type
,
948 const struct gl_pixelstore_attrib
*packing
)
950 const mesa_format src_format
=
951 blorp_get_client_format(brw
, format
, type
, packing
);
952 if (src_format
== MESA_FORMAT_NONE
)
955 if (!brw
->mesa_format_supports_render
[dst_format
]) {
956 perf_debug("intel_texsubimage: can't use %s as render target\n",
957 _mesa_get_format_name(dst_format
));
961 /* This function relies on blorp_blit to upload the pixel data to the
962 * miptree. But, blorp_blit doesn't support signed to unsigned or
963 * unsigned to signed integer conversions.
965 if (need_signed_unsigned_int_conversion(src_format
, dst_format
))
968 uint32_t src_offset
, src_row_stride
, src_image_stride
;
969 struct brw_bo
*src_bo
=
970 blorp_get_client_bo(brw
, width
, height
, depth
,
971 target
, format
, type
, pixels
, packing
,
972 &src_offset
, &src_row_stride
,
973 &src_image_stride
, true);
977 /* Now that source is offset to correct starting point, adjust the
978 * given dimensions to treat 1D arrays as 2D.
980 if (target
== GL_TEXTURE_1D_ARRAY
) {
987 src_image_stride
= src_row_stride
;
990 intel_miptree_check_level_layer(dst_mt
, level
, z
+ depth
- 1);
994 /* Blit slice-by-slice creating a single-slice miptree for each layer. Even
995 * in case of linear buffers hardware wants image arrays to be aligned by
996 * four rows. This way hardware only gets one image at a time and any
997 * source alignment will do.
999 for (unsigned i
= 0; i
< depth
; ++i
) {
1000 struct intel_mipmap_tree
*src_mt
= intel_miptree_create_for_bo(
1001 brw
, src_bo
, src_format
,
1002 src_offset
+ i
* src_image_stride
,
1005 ISL_TILING_LINEAR
, 0);
1008 perf_debug("intel_texsubimage: miptree creation for src failed\n");
1012 /* In case exact match is needed, copy using equivalent UINT formats
1013 * preventing hardware from changing presentation for SNORM -1.
1015 if (src_mt
->format
== dst_format
) {
1016 brw_blorp_copy_miptrees(brw
, src_mt
, 0, 0,
1017 dst_mt
, level
, z
+ i
,
1018 0, 0, x
, y
, width
, height
);
1020 brw_blorp_blit_miptrees(brw
, src_mt
, 0, 0,
1021 src_format
, SWIZZLE_XYZW
,
1022 dst_mt
, level
, z
+ i
,
1024 0, 0, width
, height
,
1025 x
, y
, x
+ width
, y
+ height
,
1026 GL_NEAREST
, false, false, false, false);
1029 intel_miptree_release(&src_mt
);
1035 brw_bo_unreference(src_bo
);
1041 brw_blorp_download_miptree(struct brw_context
*brw
,
1042 struct intel_mipmap_tree
*src_mt
,
1043 mesa_format src_format
, uint32_t src_swizzle
,
1044 uint32_t level
, uint32_t x
, uint32_t y
, uint32_t z
,
1045 uint32_t width
, uint32_t height
, uint32_t depth
,
1046 GLenum target
, GLenum format
, GLenum type
,
1047 bool y_flip
, const void *pixels
,
1048 const struct gl_pixelstore_attrib
*packing
)
1050 const mesa_format dst_format
=
1051 blorp_get_client_format(brw
, format
, type
, packing
);
1052 if (dst_format
== MESA_FORMAT_NONE
)
1055 if (!brw
->mesa_format_supports_render
[dst_format
]) {
1056 perf_debug("intel_texsubimage: can't use %s as render target\n",
1057 _mesa_get_format_name(dst_format
));
1061 /* This function relies on blorp_blit to download the pixel data from the
1062 * miptree. But, blorp_blit doesn't support signed to unsigned or unsigned
1063 * to signed integer conversions.
1065 if (need_signed_unsigned_int_conversion(src_format
, dst_format
))
1068 /* We can't fetch from LUMINANCE or intensity as that would require a
1069 * non-trivial swizzle.
1071 switch (_mesa_get_format_base_format(src_format
)) {
1073 case GL_LUMINANCE_ALPHA
:
1080 /* This pass only works for PBOs */
1081 assert(_mesa_is_bufferobj(packing
->BufferObj
));
1083 uint32_t dst_offset
, dst_row_stride
, dst_image_stride
;
1084 struct brw_bo
*dst_bo
=
1085 blorp_get_client_bo(brw
, width
, height
, depth
,
1086 target
, format
, type
, pixels
, packing
,
1087 &dst_offset
, &dst_row_stride
,
1088 &dst_image_stride
, false);
1092 /* Now that source is offset to correct starting point, adjust the
1093 * given dimensions to treat 1D arrays as 2D.
1095 if (target
== GL_TEXTURE_1D_ARRAY
) {
1102 dst_image_stride
= dst_row_stride
;
1105 intel_miptree_check_level_layer(src_mt
, level
, z
+ depth
- 1);
1108 int y1
= y
+ height
;
1110 apply_y_flip(&y0
, &y1
, minify(src_mt
->surf
.phys_level0_sa
.height
,
1111 level
- src_mt
->first_level
));
1114 bool result
= false;
1116 /* Blit slice-by-slice creating a single-slice miptree for each layer. Even
1117 * in case of linear buffers hardware wants image arrays to be aligned by
1118 * four rows. This way hardware only gets one image at a time and any
1119 * source alignment will do.
1121 for (unsigned i
= 0; i
< depth
; ++i
) {
1122 struct intel_mipmap_tree
*dst_mt
= intel_miptree_create_for_bo(
1123 brw
, dst_bo
, dst_format
,
1124 dst_offset
+ i
* dst_image_stride
,
1127 ISL_TILING_LINEAR
, 0);
1130 perf_debug("intel_texsubimage: miptree creation for src failed\n");
1134 /* In case exact match is needed, copy using equivalent UINT formats
1135 * preventing hardware from changing presentation for SNORM -1.
1137 if (dst_mt
->format
== src_format
&& !y_flip
&&
1138 src_swizzle
== SWIZZLE_XYZW
) {
1139 brw_blorp_copy_miptrees(brw
, src_mt
, level
, z
+ i
,
1141 x
, y
, 0, 0, width
, height
);
1143 brw_blorp_blit_miptrees(brw
, src_mt
, level
, z
+ i
,
1144 src_format
, src_swizzle
,
1145 dst_mt
, 0, 0, dst_format
,
1146 x
, y0
, x
+ width
, y1
,
1147 0, 0, width
, height
,
1148 GL_NEAREST
, false, y_flip
, false, false);
1151 intel_miptree_release(&dst_mt
);
1156 /* As we implement PBO transfers by binding the user-provided BO as a
1157 * fake framebuffer and rendering to it. This breaks the invariant of the
1158 * GL that nothing is able to render to a BO, causing nondeterministic
1159 * corruption issues because the render cache is not coherent with a
1160 * number of other caches that the BO could potentially be bound to
1163 * This could be solved in the same way that we guarantee texture
1164 * coherency after a texture is attached to a framebuffer and
1165 * rendered to, but that would involve checking *all* BOs bound to
1166 * the pipeline for the case we need to emit a cache flush due to
1167 * previous rendering to any of them -- Including vertex, index,
1168 * uniform, atomic counter, shader image, transform feedback,
1169 * indirect draw buffers, etc.
1171 * That would increase the per-draw call overhead even though it's
1172 * very unlikely that any of the BOs bound to the pipeline has been
1173 * rendered to via a PBO at any point, so it seems better to just
1174 * flush here unconditionally.
1176 brw_emit_mi_flush(brw
);
1179 brw_bo_unreference(dst_bo
);
1185 set_write_disables(const struct intel_renderbuffer
*irb
,
1186 const unsigned color_mask
, bool *color_write_disable
)
1188 /* Format information in the renderbuffer represents the requirements
1189 * given by the client. There are cases where the backing miptree uses,
1190 * for example, RGBA to represent RGBX. Since the client is only expecting
1191 * RGB we can treat alpha as not used and write whatever we like into it.
1193 const GLenum base_format
= irb
->Base
.Base
._BaseFormat
;
1194 const int components
= _mesa_base_format_component_count(base_format
);
1195 bool disables
= false;
1197 assert(components
> 0);
1199 for (int i
= 0; i
< components
; i
++) {
1200 color_write_disable
[i
] = !(color_mask
& (1 << i
));
1201 disables
= disables
|| color_write_disable
[i
];
1208 do_single_blorp_clear(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
1209 struct gl_renderbuffer
*rb
, unsigned buf
,
1210 bool partial_clear
, bool encode_srgb
)
1212 struct gl_context
*ctx
= &brw
->ctx
;
1213 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
1214 uint32_t x0
, x1
, y0
, y1
;
1216 mesa_format format
= irb
->Base
.Base
.Format
;
1217 if (!encode_srgb
&& _mesa_get_format_color_encoding(format
) == GL_SRGB
)
1218 format
= _mesa_get_srgb_format_linear(format
);
1219 enum isl_format isl_format
= brw
->mesa_to_isl_render_format
[format
];
1223 if (rb
->Name
!= 0) {
1227 y0
= rb
->Height
- fb
->_Ymax
;
1228 y1
= rb
->Height
- fb
->_Ymin
;
1231 /* If the clear region is empty, just return. */
1232 if (x0
== x1
|| y0
== y1
)
1235 bool can_fast_clear
= !partial_clear
;
1237 bool color_write_disable
[4] = { false, false, false, false };
1238 if (set_write_disables(irb
, GET_COLORMASK(ctx
->Color
.ColorMask
, buf
),
1239 color_write_disable
))
1240 can_fast_clear
= false;
1242 /* We store clear colors as floats or uints as needed. If there are
1243 * texture views in play, the formats will not properly be respected
1244 * during resolves because the resolve operations only know about the
1245 * miptree and not the renderbuffer.
1247 if (irb
->Base
.Base
.Format
!= irb
->mt
->format
)
1248 can_fast_clear
= false;
1250 if (!irb
->mt
->supports_fast_clear
||
1251 !brw_is_color_fast_clear_compatible(brw
, irb
->mt
, &ctx
->Color
.ClearColor
))
1252 can_fast_clear
= false;
1254 /* Surface state can only record one fast clear color value. Therefore
1255 * unless different levels/layers agree on the color it can be used to
1256 * represent only single level/layer. Here it will be reserved for the
1257 * first slice (level 0, layer 0).
1259 if (irb
->layer_count
> 1 || irb
->mt_level
|| irb
->mt_layer
)
1260 can_fast_clear
= false;
1262 unsigned level
= irb
->mt_level
;
1263 const unsigned num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1265 /* If the MCS buffer hasn't been allocated yet, we need to allocate it now.
1267 if (can_fast_clear
&& !irb
->mt
->aux_buf
) {
1268 assert(irb
->mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1269 if (!intel_miptree_alloc_aux(brw
, irb
->mt
)) {
1270 /* We're out of memory. Fall back to a non-fast clear. */
1271 can_fast_clear
= false;
1275 /* FINISHME: Debug and enable fast clears */
1276 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1277 if (devinfo
->gen
>= 11)
1278 can_fast_clear
= false;
1280 if (can_fast_clear
) {
1281 const enum isl_aux_state aux_state
=
1282 intel_miptree_get_aux_state(irb
->mt
, irb
->mt_level
, irb
->mt_layer
);
1283 union isl_color_value clear_color
=
1284 brw_meta_convert_fast_clear_color(brw
, irb
->mt
,
1285 &ctx
->Color
.ClearColor
);
1287 intel_miptree_set_clear_color(brw
, irb
->mt
, clear_color
);
1289 /* If the buffer is already in ISL_AUX_STATE_CLEAR, the clear
1290 * is redundant and can be skipped.
1292 if (aux_state
== ISL_AUX_STATE_CLEAR
)
1295 DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__
,
1296 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
1298 /* We can't setup the blorp_surf until we've allocated the MCS above */
1299 struct isl_surf isl_tmp
[2];
1300 struct blorp_surf surf
;
1301 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, irb
->mt
->aux_usage
, true,
1302 &level
, irb
->mt_layer
, num_layers
, isl_tmp
);
1304 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1306 * "Any transition from any value in {Clear, Render, Resolve} to a
1307 * different value in {Clear, Render, Resolve} requires end of pipe
1310 * In other words, fast clear ops are not properly synchronized with
1311 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1312 * contents of the previous draw hit the render target before we resolve
1313 * and again afterwards to ensure that the resolve is complete before we
1314 * do any more regular drawing.
1316 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1318 struct blorp_batch batch
;
1319 blorp_batch_init(&brw
->blorp
, &batch
, brw
,
1320 BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
);
1321 blorp_fast_clear(&batch
, &surf
, isl_format
,
1322 level
, irb
->mt_layer
, num_layers
,
1324 blorp_batch_finish(&batch
);
1326 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1328 /* Now that the fast clear has occurred, put the buffer in
1329 * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
1332 intel_miptree_set_aux_state(brw
, irb
->mt
, irb
->mt_level
,
1333 irb
->mt_layer
, num_layers
,
1334 ISL_AUX_STATE_CLEAR
);
1336 DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__
,
1337 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
1339 enum isl_aux_usage aux_usage
=
1340 intel_miptree_render_aux_usage(brw
, irb
->mt
, isl_format
,
1342 intel_miptree_prepare_render(brw
, irb
->mt
, level
, irb
->mt_layer
,
1343 num_layers
, aux_usage
);
1345 struct isl_surf isl_tmp
[2];
1346 struct blorp_surf surf
;
1347 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, aux_usage
, true,
1348 &level
, irb
->mt_layer
, num_layers
, isl_tmp
);
1350 union isl_color_value clear_color
;
1351 memcpy(clear_color
.f32
, ctx
->Color
.ClearColor
.f
, sizeof(float) * 4);
1353 struct blorp_batch batch
;
1354 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1355 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
1356 level
, irb
->mt_layer
, num_layers
,
1358 clear_color
, color_write_disable
);
1359 blorp_batch_finish(&batch
);
1361 intel_miptree_finish_render(brw
, irb
->mt
, level
, irb
->mt_layer
,
1362 num_layers
, aux_usage
);
1369 brw_blorp_clear_color(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
1370 GLbitfield mask
, bool partial_clear
, bool encode_srgb
)
1372 for (unsigned buf
= 0; buf
< fb
->_NumColorDrawBuffers
; buf
++) {
1373 struct gl_renderbuffer
*rb
= fb
->_ColorDrawBuffers
[buf
];
1374 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
1376 /* Only clear the buffers present in the provided mask */
1377 if (((1 << fb
->_ColorDrawBufferIndexes
[buf
]) & mask
) == 0)
1380 /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
1381 * the framebuffer can be complete with some attachments missing. In
1382 * this case the _ColorDrawBuffers pointer will be NULL.
1387 do_single_blorp_clear(brw
, fb
, rb
, buf
, partial_clear
, encode_srgb
);
1388 irb
->need_downsample
= true;
1395 brw_blorp_clear_depth_stencil(struct brw_context
*brw
,
1396 struct gl_framebuffer
*fb
,
1397 GLbitfield mask
, bool partial_clear
)
1399 const struct gl_context
*ctx
= &brw
->ctx
;
1400 struct gl_renderbuffer
*depth_rb
=
1401 fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
;
1402 struct gl_renderbuffer
*stencil_rb
=
1403 fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
1405 if (!depth_rb
|| ctx
->Depth
.Mask
== GL_FALSE
)
1406 mask
&= ~BUFFER_BIT_DEPTH
;
1408 if (!stencil_rb
|| (ctx
->Stencil
.WriteMask
[0] & 0xff) == 0)
1409 mask
&= ~BUFFER_BIT_STENCIL
;
1411 if (!(mask
& (BUFFER_BITS_DEPTH_STENCIL
)))
1414 uint32_t x0
, x1
, y0
, y1
, rb_name
, rb_height
;
1416 rb_name
= depth_rb
->Name
;
1417 rb_height
= depth_rb
->Height
;
1419 assert(depth_rb
->Width
== stencil_rb
->Width
);
1420 assert(depth_rb
->Height
== stencil_rb
->Height
);
1424 rb_name
= stencil_rb
->Name
;
1425 rb_height
= stencil_rb
->Height
;
1434 y0
= rb_height
- fb
->_Ymax
;
1435 y1
= rb_height
- fb
->_Ymin
;
1438 /* If the clear region is empty, just return. */
1439 if (x0
== x1
|| y0
== y1
)
1442 uint32_t level
, start_layer
, num_layers
;
1443 struct isl_surf isl_tmp
[4];
1444 struct blorp_surf depth_surf
, stencil_surf
;
1446 struct intel_mipmap_tree
*depth_mt
= NULL
;
1447 if (mask
& BUFFER_BIT_DEPTH
) {
1448 struct intel_renderbuffer
*irb
= intel_renderbuffer(depth_rb
);
1449 depth_mt
= find_miptree(GL_DEPTH_BUFFER_BIT
, irb
);
1451 level
= irb
->mt_level
;
1452 start_layer
= irb
->mt_layer
;
1453 num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1455 intel_miptree_prepare_depth(brw
, depth_mt
, level
,
1456 start_layer
, num_layers
);
1458 unsigned depth_level
= level
;
1459 blorp_surf_for_miptree(brw
, &depth_surf
, depth_mt
, depth_mt
->aux_usage
,
1460 true, &depth_level
, start_layer
, num_layers
,
1462 assert(depth_level
== level
);
1465 uint8_t stencil_mask
= 0;
1466 struct intel_mipmap_tree
*stencil_mt
= NULL
;
1467 if (mask
& BUFFER_BIT_STENCIL
) {
1468 struct intel_renderbuffer
*irb
= intel_renderbuffer(stencil_rb
);
1469 stencil_mt
= find_miptree(GL_STENCIL_BUFFER_BIT
, irb
);
1471 if (mask
& BUFFER_BIT_DEPTH
) {
1472 assert(level
== irb
->mt_level
);
1473 assert(start_layer
== irb
->mt_layer
);
1474 assert(num_layers
== fb
->MaxNumLayers
? irb
->layer_count
: 1);
1477 level
= irb
->mt_level
;
1478 start_layer
= irb
->mt_layer
;
1479 num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1481 stencil_mask
= ctx
->Stencil
.WriteMask
[0] & 0xff;
1483 intel_miptree_prepare_access(brw
, stencil_mt
, level
, 1,
1484 start_layer
, num_layers
,
1485 ISL_AUX_USAGE_NONE
, false);
1487 unsigned stencil_level
= level
;
1488 blorp_surf_for_miptree(brw
, &stencil_surf
, stencil_mt
,
1489 ISL_AUX_USAGE_NONE
, true,
1490 &stencil_level
, start_layer
, num_layers
,
1494 assert((mask
& BUFFER_BIT_DEPTH
) || stencil_mask
);
1496 struct blorp_batch batch
;
1497 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1498 blorp_clear_depth_stencil(&batch
, &depth_surf
, &stencil_surf
,
1499 level
, start_layer
, num_layers
,
1501 (mask
& BUFFER_BIT_DEPTH
), ctx
->Depth
.Clear
,
1502 stencil_mask
, ctx
->Stencil
.Clear
);
1503 blorp_batch_finish(&batch
);
1505 if (mask
& BUFFER_BIT_DEPTH
) {
1506 intel_miptree_finish_depth(brw
, depth_mt
, level
,
1507 start_layer
, num_layers
, true);
1511 intel_miptree_finish_write(brw
, stencil_mt
, level
,
1512 start_layer
, num_layers
,
1513 ISL_AUX_USAGE_NONE
);
1518 brw_blorp_resolve_color(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1519 unsigned level
, unsigned layer
,
1520 enum isl_aux_op resolve_op
)
1522 DBG("%s to mt %p level %u layer %u\n", __FUNCTION__
, mt
, level
, layer
);
1524 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
1526 struct isl_surf isl_tmp
[1];
1527 struct blorp_surf surf
;
1528 blorp_surf_for_miptree(brw
, &surf
, mt
, mt
->aux_usage
, true,
1529 &level
, layer
, 1 /* num_layers */,
1532 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1534 * "Any transition from any value in {Clear, Render, Resolve} to a
1535 * different value in {Clear, Render, Resolve} requires end of pipe
1538 * In other words, fast clear ops are not properly synchronized with
1539 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1540 * contents of the previous draw hit the render target before we resolve
1541 * and again afterwards to ensure that the resolve is complete before we
1542 * do any more regular drawing.
1544 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1547 struct blorp_batch batch
;
1548 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1549 blorp_ccs_resolve(&batch
, &surf
, level
, layer
, 1,
1550 brw_blorp_to_isl_format(brw
, format
, true),
1552 blorp_batch_finish(&batch
);
1554 /* See comment above */
1555 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1559 brw_blorp_mcs_partial_resolve(struct brw_context
*brw
,
1560 struct intel_mipmap_tree
*mt
,
1561 uint32_t start_layer
, uint32_t num_layers
)
1563 DBG("%s to mt %p layers %u-%u\n", __FUNCTION__
, mt
,
1564 start_layer
, start_layer
+ num_layers
- 1);
1566 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1568 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
1569 enum isl_format isl_format
= brw_blorp_to_isl_format(brw
, format
, true);
1571 struct isl_surf isl_tmp
[1];
1572 struct blorp_surf surf
;
1574 blorp_surf_for_miptree(brw
, &surf
, mt
, ISL_AUX_USAGE_MCS
, true,
1575 &level
, start_layer
, num_layers
, isl_tmp
);
1577 struct blorp_batch batch
;
1578 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1579 blorp_mcs_partial_resolve(&batch
, &surf
, isl_format
,
1580 start_layer
, num_layers
);
1581 blorp_batch_finish(&batch
);
1585 * Perform a HiZ or depth resolve operation.
1587 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
1588 * PRM, Volume 1, Part 2:
1589 * - 7.5.3.1 Depth Buffer Clear
1590 * - 7.5.3.2 Depth Buffer Resolve
1591 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1594 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1595 unsigned int level
, unsigned int start_layer
,
1596 unsigned int num_layers
, enum isl_aux_op op
)
1598 assert(intel_miptree_level_has_hiz(mt
, level
));
1599 assert(op
!= ISL_AUX_OP_NONE
);
1600 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1601 const char *opname
= NULL
;
1604 case ISL_AUX_OP_FULL_RESOLVE
:
1605 opname
= "depth resolve";
1607 case ISL_AUX_OP_AMBIGUATE
:
1608 opname
= "hiz ambiguate";
1610 case ISL_AUX_OP_FAST_CLEAR
:
1611 opname
= "depth clear";
1613 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1614 case ISL_AUX_OP_NONE
:
1615 unreachable("Invalid HiZ op");
1618 DBG("%s %s to mt %p level %d layers %d-%d\n",
1619 __func__
, opname
, mt
, level
, start_layer
, start_layer
+ num_layers
- 1);
1621 /* The following stalls and flushes are only documented to be required for
1622 * HiZ clear operations. However, they also seem to be required for
1623 * resolve operations.
1625 if (devinfo
->gen
== 6) {
1626 /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
1628 * "If other rendering operations have preceded this clear, a
1629 * PIPE_CONTROL with write cache flush enabled and Z-inhibit
1630 * disabled must be issued before the rectangle primitive used for
1631 * the depth buffer clear operation.
1633 brw_emit_pipe_control_flush(brw
,
1634 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1635 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1636 PIPE_CONTROL_CS_STALL
);
1637 } else if (devinfo
->gen
>= 7) {
1639 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
1641 * If other rendering operations have preceded this clear, a
1642 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
1643 * enabled must be issued before the rectangle primitive used for
1644 * the depth buffer clear operation.
1646 * Same applies for Gen8 and Gen9.
1648 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
1649 * PIPE_CONTROL, Depth Cache Flush Enable:
1651 * This bit must not be set when Depth Stall Enable bit is set in
1654 * This is confirmed to hold for real, HSW gets immediate gpu hangs.
1656 * Therefore issue two pipe control flushes, one for cache flush and
1657 * another for depth stall.
1659 brw_emit_pipe_control_flush(brw
,
1660 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1661 PIPE_CONTROL_CS_STALL
);
1663 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
1666 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
&& mt
->aux_buf
);
1668 struct isl_surf isl_tmp
[2];
1669 struct blorp_surf surf
;
1670 blorp_surf_for_miptree(brw
, &surf
, mt
, ISL_AUX_USAGE_HIZ
, true,
1671 &level
, start_layer
, num_layers
, isl_tmp
);
1673 struct blorp_batch batch
;
1674 blorp_batch_init(&brw
->blorp
, &batch
, brw
,
1675 BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
);
1676 blorp_hiz_op(&batch
, &surf
, level
, start_layer
, num_layers
, op
);
1677 blorp_batch_finish(&batch
);
1679 /* The following stalls and flushes are only documented to be required for
1680 * HiZ clear operations. However, they also seem to be required for
1681 * resolve operations.
1683 if (devinfo
->gen
== 6) {
1684 /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
1686 * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be
1687 * followed by a PIPE_CONTROL command with DEPTH_STALL bit set
1688 * and Then followed by Depth FLUSH'
1690 brw_emit_pipe_control_flush(brw
,
1691 PIPE_CONTROL_DEPTH_STALL
);
1693 brw_emit_pipe_control_flush(brw
,
1694 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1695 PIPE_CONTROL_CS_STALL
);
1696 } else if (devinfo
->gen
>= 8) {
1698 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
1700 * "Depth buffer clear pass using any of the methods (WM_STATE,
1701 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
1702 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
1703 * "set" before starting to render. DepthStall and DepthFlush are
1704 * not needed between consecutive depth clear passes nor is it
1705 * required if the depth clear pass was done with
1706 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
1708 * TODO: Such as the spec says, this could be conditional.
1710 brw_emit_pipe_control_flush(brw
,
1711 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1712 PIPE_CONTROL_DEPTH_STALL
);