2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/blend.h"
27 #include "main/bufferobj.h"
28 #include "main/enums.h"
29 #include "main/fbobject.h"
30 #include "main/image.h"
31 #include "main/renderbuffer.h"
32 #include "main/glformats.h"
34 #include "brw_blorp.h"
35 #include "brw_context.h"
36 #include "brw_defines.h"
37 #include "brw_meta_util.h"
38 #include "brw_state.h"
39 #include "intel_buffer_objects.h"
40 #include "intel_fbo.h"
41 #include "common/gen_debug.h"
43 #define FILE_DEBUG_FLAG DEBUG_BLORP
46 brw_blorp_lookup_shader(struct blorp_context
*blorp
,
47 const void *key
, uint32_t key_size
,
48 uint32_t *kernel_out
, void *prog_data_out
)
50 struct brw_context
*brw
= blorp
->driver_ctx
;
51 return brw_search_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
,
52 key
, key_size
, kernel_out
, prog_data_out
);
56 brw_blorp_upload_shader(struct blorp_context
*blorp
,
57 const void *key
, uint32_t key_size
,
58 const void *kernel
, uint32_t kernel_size
,
59 const struct brw_stage_prog_data
*prog_data
,
60 uint32_t prog_data_size
,
61 uint32_t *kernel_out
, void *prog_data_out
)
63 struct brw_context
*brw
= blorp
->driver_ctx
;
64 brw_upload_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
, key
, key_size
,
65 kernel
, kernel_size
, prog_data
, prog_data_size
,
66 kernel_out
, prog_data_out
);
71 brw_blorp_init(struct brw_context
*brw
)
73 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
75 blorp_init(&brw
->blorp
, brw
, &brw
->isl_dev
);
77 brw
->blorp
.compiler
= brw
->screen
->compiler
;
79 switch (devinfo
->gen
) {
81 if (devinfo
->is_g4x
) {
82 brw
->blorp
.exec
= gen45_blorp_exec
;
84 brw
->blorp
.exec
= gen4_blorp_exec
;
88 brw
->blorp
.exec
= gen5_blorp_exec
;
91 brw
->blorp
.exec
= gen6_blorp_exec
;
94 if (devinfo
->is_haswell
) {
95 brw
->blorp
.exec
= gen75_blorp_exec
;
97 brw
->blorp
.exec
= gen7_blorp_exec
;
101 brw
->blorp
.exec
= gen8_blorp_exec
;
104 brw
->blorp
.exec
= gen9_blorp_exec
;
107 brw
->blorp
.exec
= gen10_blorp_exec
;
110 unreachable("Invalid gen");
113 brw
->blorp
.lookup_shader
= brw_blorp_lookup_shader
;
114 brw
->blorp
.upload_shader
= brw_blorp_upload_shader
;
118 blorp_surf_for_miptree(struct brw_context
*brw
,
119 struct blorp_surf
*surf
,
120 struct intel_mipmap_tree
*mt
,
121 enum isl_aux_usage aux_usage
,
122 bool is_render_target
,
124 unsigned start_layer
, unsigned num_layers
,
125 struct isl_surf tmp_surfs
[1])
127 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
129 if (mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
) {
130 const unsigned num_samples
= mt
->surf
.samples
;
131 for (unsigned i
= 0; i
< num_layers
; i
++) {
132 for (unsigned s
= 0; s
< num_samples
; s
++) {
133 const unsigned phys_layer
= (start_layer
+ i
) * num_samples
+ s
;
134 intel_miptree_check_level_layer(mt
, *level
, phys_layer
);
138 for (unsigned i
= 0; i
< num_layers
; i
++)
139 intel_miptree_check_level_layer(mt
, *level
, start_layer
+ i
);
142 *surf
= (struct blorp_surf
) {
144 .addr
= (struct blorp_address
) {
146 .offset
= mt
->offset
,
147 .reloc_flags
= is_render_target
? EXEC_OBJECT_WRITE
: 0,
148 .mocs
= brw_get_bo_mocs(devinfo
, mt
->bo
),
150 .aux_usage
= aux_usage
,
153 struct isl_surf
*aux_surf
= NULL
;
155 aux_surf
= &mt
->mcs_buf
->surf
;
156 else if (mt
->hiz_buf
)
157 aux_surf
= &mt
->hiz_buf
->surf
;
159 if (mt
->format
== MESA_FORMAT_S_UINT8
&& is_render_target
&&
161 mt
->r8stencil_needs_update
= true;
163 if (surf
->aux_usage
== ISL_AUX_USAGE_HIZ
&&
164 !intel_miptree_level_has_hiz(mt
, *level
))
165 surf
->aux_usage
= ISL_AUX_USAGE_NONE
;
167 if (surf
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
168 /* We only really need a clear color if we also have an auxiliary
169 * surface. Without one, it does nothing.
171 surf
->clear_color
= mt
->fast_clear_color
;
173 surf
->aux_surf
= aux_surf
;
174 surf
->aux_addr
= (struct blorp_address
) {
175 .reloc_flags
= is_render_target
? EXEC_OBJECT_WRITE
: 0,
176 .mocs
= surf
->addr
.mocs
,
180 surf
->aux_addr
.buffer
= mt
->mcs_buf
->bo
;
181 surf
->aux_addr
.offset
= mt
->mcs_buf
->offset
;
184 assert(surf
->aux_usage
== ISL_AUX_USAGE_HIZ
);
186 surf
->aux_addr
.buffer
= mt
->hiz_buf
->bo
;
187 surf
->aux_addr
.offset
= mt
->hiz_buf
->offset
;
190 surf
->aux_addr
= (struct blorp_address
) {
193 memset(&surf
->clear_color
, 0, sizeof(surf
->clear_color
));
195 assert((surf
->aux_usage
== ISL_AUX_USAGE_NONE
) ==
196 (surf
->aux_addr
.buffer
== NULL
));
198 /* ISL wants real levels, not offset ones. */
199 *level
-= mt
->first_level
;
202 static enum isl_format
203 brw_blorp_to_isl_format(struct brw_context
*brw
, mesa_format format
,
204 bool is_render_target
)
207 case MESA_FORMAT_NONE
:
208 return ISL_FORMAT_UNSUPPORTED
;
209 case MESA_FORMAT_S_UINT8
:
210 return ISL_FORMAT_R8_UINT
;
211 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
212 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
213 return ISL_FORMAT_R24_UNORM_X8_TYPELESS
;
214 case MESA_FORMAT_Z_FLOAT32
:
215 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
216 return ISL_FORMAT_R32_FLOAT
;
217 case MESA_FORMAT_Z_UNORM16
:
218 return ISL_FORMAT_R16_UNORM
;
220 if (is_render_target
) {
221 assert(brw
->mesa_format_supports_render
[format
]);
222 return brw
->mesa_to_isl_render_format
[format
];
224 return brw_isl_format_for_mesa_format(format
);
232 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
233 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
235 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
238 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
240 * which is simply adding 4 then modding by 8 (or anding with 7).
242 * We then may need to apply workarounds for textureGather hardware bugs.
244 static enum isl_channel_select
245 swizzle_to_scs(GLenum swizzle
)
247 return (enum isl_channel_select
)((swizzle
+ 4) & 7);
251 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
252 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
253 * the physical layer holding sample 0. So, for example, if
254 * src_mt->surf.samples == 4, then logical layer n corresponds to src_layer ==
258 brw_blorp_blit_miptrees(struct brw_context
*brw
,
259 struct intel_mipmap_tree
*src_mt
,
260 unsigned src_level
, unsigned src_layer
,
261 mesa_format src_format
, int src_swizzle
,
262 struct intel_mipmap_tree
*dst_mt
,
263 unsigned dst_level
, unsigned dst_layer
,
264 mesa_format dst_format
,
265 float src_x0
, float src_y0
,
266 float src_x1
, float src_y1
,
267 float dst_x0
, float dst_y0
,
268 float dst_x1
, float dst_y1
,
269 GLenum filter
, bool mirror_x
, bool mirror_y
,
270 bool decode_srgb
, bool encode_srgb
)
272 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
274 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
275 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
277 src_mt
->surf
.samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
278 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
279 dst_mt
->surf
.samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
280 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
283 if (!decode_srgb
&& _mesa_get_format_color_encoding(src_format
) == GL_SRGB
)
284 src_format
= _mesa_get_srgb_format_linear(src_format
);
286 if (!encode_srgb
&& _mesa_get_format_color_encoding(dst_format
) == GL_SRGB
)
287 dst_format
= _mesa_get_srgb_format_linear(dst_format
);
289 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
290 * texture, the above code configures the source format for L32_FLOAT or
291 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
292 * the SAMPLE message appears to handle multisampled L32_FLOAT and
293 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
294 * around the problem by using a source format of R32_FLOAT. This
295 * shouldn't affect rendering correctness, since the destination format is
296 * R32_FLOAT, so only the contents of the red channel matters.
298 if (devinfo
->gen
== 6 &&
299 src_mt
->surf
.samples
> 1 && dst_mt
->surf
.samples
<= 1 &&
300 src_mt
->format
== dst_mt
->format
&&
301 (dst_format
== MESA_FORMAT_L_FLOAT32
||
302 dst_format
== MESA_FORMAT_I_FLOAT32
)) {
303 src_format
= dst_format
= MESA_FORMAT_R_FLOAT32
;
306 enum isl_format src_isl_format
=
307 brw_blorp_to_isl_format(brw
, src_format
, false);
308 enum isl_aux_usage src_aux_usage
=
309 intel_miptree_texture_aux_usage(brw
, src_mt
, src_isl_format
);
310 /* We do format workarounds for some depth formats so we can't reliably
311 * sample with HiZ. One of these days, we should fix that.
313 if (src_aux_usage
== ISL_AUX_USAGE_HIZ
)
314 src_aux_usage
= ISL_AUX_USAGE_NONE
;
315 const bool src_clear_supported
=
316 src_aux_usage
!= ISL_AUX_USAGE_NONE
&& src_mt
->format
== src_format
;
317 intel_miptree_prepare_access(brw
, src_mt
, src_level
, 1, src_layer
, 1,
318 src_aux_usage
, src_clear_supported
);
320 enum isl_format dst_isl_format
=
321 brw_blorp_to_isl_format(brw
, dst_format
, true);
322 enum isl_aux_usage dst_aux_usage
=
323 intel_miptree_render_aux_usage(brw
, dst_mt
, dst_isl_format
,
325 const bool dst_clear_supported
= dst_aux_usage
!= ISL_AUX_USAGE_NONE
;
326 intel_miptree_prepare_access(brw
, dst_mt
, dst_level
, 1, dst_layer
, 1,
327 dst_aux_usage
, dst_clear_supported
);
329 struct isl_surf tmp_surfs
[2];
330 struct blorp_surf src_surf
, dst_surf
;
331 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, src_aux_usage
, false,
332 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
333 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, dst_aux_usage
, true,
334 &dst_level
, dst_layer
, 1, &tmp_surfs
[1]);
336 struct isl_swizzle src_isl_swizzle
= {
337 .r
= swizzle_to_scs(GET_SWZ(src_swizzle
, 0)),
338 .g
= swizzle_to_scs(GET_SWZ(src_swizzle
, 1)),
339 .b
= swizzle_to_scs(GET_SWZ(src_swizzle
, 2)),
340 .a
= swizzle_to_scs(GET_SWZ(src_swizzle
, 3)),
343 struct blorp_batch batch
;
344 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
345 blorp_blit(&batch
, &src_surf
, src_level
, src_layer
,
346 src_isl_format
, src_isl_swizzle
,
347 &dst_surf
, dst_level
, dst_layer
,
348 dst_isl_format
, ISL_SWIZZLE_IDENTITY
,
349 src_x0
, src_y0
, src_x1
, src_y1
,
350 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
351 filter
, mirror_x
, mirror_y
);
352 blorp_batch_finish(&batch
);
354 intel_miptree_finish_write(brw
, dst_mt
, dst_level
, dst_layer
, 1,
359 brw_blorp_copy_miptrees(struct brw_context
*brw
,
360 struct intel_mipmap_tree
*src_mt
,
361 unsigned src_level
, unsigned src_layer
,
362 struct intel_mipmap_tree
*dst_mt
,
363 unsigned dst_level
, unsigned dst_layer
,
364 unsigned src_x
, unsigned src_y
,
365 unsigned dst_x
, unsigned dst_y
,
366 unsigned src_width
, unsigned src_height
)
368 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
370 DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
371 "to %dx %s mt %p %d %d (%d,%d)\n",
373 src_mt
->surf
.samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
374 src_level
, src_layer
, src_x
, src_y
, src_width
, src_height
,
375 dst_mt
->surf
.samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
376 dst_level
, dst_layer
, dst_x
, dst_y
);
378 enum isl_aux_usage src_aux_usage
, dst_aux_usage
;
379 bool src_clear_supported
, dst_clear_supported
;
381 switch (src_mt
->aux_usage
) {
382 case ISL_AUX_USAGE_MCS
:
383 case ISL_AUX_USAGE_CCS_E
:
384 src_aux_usage
= src_mt
->aux_usage
;
385 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
386 * we're going to re-interpret the format as an integer format possibly
387 * with a different number of components, we can't handle clear colors
390 src_clear_supported
= devinfo
->gen
>= 9;
393 src_aux_usage
= ISL_AUX_USAGE_NONE
;
394 src_clear_supported
= false;
398 switch (dst_mt
->aux_usage
) {
399 case ISL_AUX_USAGE_MCS
:
400 case ISL_AUX_USAGE_CCS_E
:
401 dst_aux_usage
= dst_mt
->aux_usage
;
402 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
403 * we're going to re-interpret the format as an integer format possibly
404 * with a different number of components, we can't handle clear colors
407 dst_clear_supported
= devinfo
->gen
>= 9;
410 dst_aux_usage
= ISL_AUX_USAGE_NONE
;
411 dst_clear_supported
= false;
415 intel_miptree_prepare_access(brw
, src_mt
, src_level
, 1, src_layer
, 1,
416 src_aux_usage
, src_clear_supported
);
417 intel_miptree_prepare_access(brw
, dst_mt
, dst_level
, 1, dst_layer
, 1,
418 dst_aux_usage
, dst_clear_supported
);
420 struct isl_surf tmp_surfs
[2];
421 struct blorp_surf src_surf
, dst_surf
;
422 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, src_aux_usage
, false,
423 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
424 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, dst_aux_usage
, true,
425 &dst_level
, dst_layer
, 1, &tmp_surfs
[1]);
427 struct blorp_batch batch
;
428 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
429 blorp_copy(&batch
, &src_surf
, src_level
, src_layer
,
430 &dst_surf
, dst_level
, dst_layer
,
431 src_x
, src_y
, dst_x
, dst_y
, src_width
, src_height
);
432 blorp_batch_finish(&batch
);
434 intel_miptree_finish_write(brw
, dst_mt
, dst_level
, dst_layer
, 1,
439 brw_blorp_copy_buffers(struct brw_context
*brw
,
440 struct brw_bo
*src_bo
,
442 struct brw_bo
*dst_bo
,
446 DBG("%s %d bytes from %p[%d] to %p[%d]",
447 __func__
, size
, src_bo
, src_offset
, dst_bo
, dst_offset
);
449 struct blorp_batch batch
;
450 struct blorp_address src
= { .buffer
= src_bo
, .offset
= src_offset
};
451 struct blorp_address dst
= { .buffer
= dst_bo
, .offset
= dst_offset
};
453 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
454 blorp_buffer_copy(&batch
, src
, dst
, size
);
455 blorp_batch_finish(&batch
);
459 static struct intel_mipmap_tree
*
460 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
462 struct intel_mipmap_tree
*mt
= irb
->mt
;
463 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
469 blorp_get_texture_swizzle(const struct intel_renderbuffer
*irb
)
471 return irb
->Base
.Base
._BaseFormat
== GL_RGB
?
472 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ONE
) :
477 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
478 struct intel_renderbuffer
*src_irb
, mesa_format src_format
,
479 struct intel_renderbuffer
*dst_irb
, mesa_format dst_format
,
480 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
481 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
482 GLenum filter
, bool mirror_x
, bool mirror_y
)
484 const struct gl_context
*ctx
= &brw
->ctx
;
486 /* Find source/dst miptrees */
487 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
488 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
490 const bool do_srgb
= ctx
->Color
.sRGBEnabled
;
493 brw_blorp_blit_miptrees(brw
,
494 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
495 src_format
, blorp_get_texture_swizzle(src_irb
),
496 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
498 srcX0
, srcY0
, srcX1
, srcY1
,
499 dstX0
, dstY0
, dstX1
, dstY1
,
500 filter
, mirror_x
, mirror_y
,
503 dst_irb
->need_downsample
= true;
507 try_blorp_blit(struct brw_context
*brw
,
508 const struct gl_framebuffer
*read_fb
,
509 const struct gl_framebuffer
*draw_fb
,
510 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
511 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
512 GLenum filter
, GLbitfield buffer_bit
)
514 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
515 struct gl_context
*ctx
= &brw
->ctx
;
517 /* Sync up the state of window system buffers. We need to do this before
518 * we go looking for the buffers.
520 intel_prepare_render(brw
);
522 bool mirror_x
, mirror_y
;
523 if (brw_meta_mirror_clip_and_scissor(ctx
, read_fb
, draw_fb
,
524 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
525 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
526 &mirror_x
, &mirror_y
))
530 struct intel_renderbuffer
*src_irb
;
531 struct intel_renderbuffer
*dst_irb
;
532 struct intel_mipmap_tree
*src_mt
;
533 struct intel_mipmap_tree
*dst_mt
;
534 switch (buffer_bit
) {
535 case GL_COLOR_BUFFER_BIT
:
536 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
537 for (unsigned i
= 0; i
< draw_fb
->_NumColorDrawBuffers
; ++i
) {
538 dst_irb
= intel_renderbuffer(draw_fb
->_ColorDrawBuffers
[i
]);
540 do_blorp_blit(brw
, buffer_bit
,
541 src_irb
, src_irb
->Base
.Base
.Format
,
542 dst_irb
, dst_irb
->Base
.Base
.Format
,
543 srcX0
, srcY0
, srcX1
, srcY1
,
544 dstX0
, dstY0
, dstX1
, dstY1
,
545 filter
, mirror_x
, mirror_y
);
548 case GL_DEPTH_BUFFER_BIT
:
550 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
552 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
553 src_mt
= find_miptree(buffer_bit
, src_irb
);
554 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
556 /* We can't handle format conversions between Z24 and other formats
557 * since we have to lie about the surface format. See the comments in
558 * brw_blorp_surface_info::set().
560 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
561 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
))
564 /* We also can't handle any combined depth-stencil formats because we
565 * have to reinterpret as a color format.
567 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
568 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
571 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
572 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
573 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
574 filter
, mirror_x
, mirror_y
);
576 case GL_STENCIL_BUFFER_BIT
:
577 /* Blorp doesn't support combined depth stencil which is all we have
580 if (devinfo
->gen
< 6)
584 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
586 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
587 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
588 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
589 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
590 filter
, mirror_x
, mirror_y
);
593 unreachable("not reached");
600 apply_y_flip(int *y0
, int *y1
, int height
)
602 int tmp
= height
- *y0
;
608 brw_blorp_copytexsubimage(struct brw_context
*brw
,
609 struct gl_renderbuffer
*src_rb
,
610 struct gl_texture_image
*dst_image
,
612 int srcX0
, int srcY0
,
613 int dstX0
, int dstY0
,
614 int width
, int height
)
616 struct gl_context
*ctx
= &brw
->ctx
;
617 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
618 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
620 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
621 if (brw
->ctx
._ImageTransferState
)
624 /* Sync up the state of window system buffers. We need to do this before
625 * we go looking at the src renderbuffer's miptree.
627 intel_prepare_render(brw
);
629 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
630 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
632 /* There is support for only up to eight samples. */
633 if (src_mt
->surf
.samples
> 8 || dst_mt
->surf
.samples
> 8)
636 if (_mesa_get_format_base_format(src_rb
->Format
) !=
637 _mesa_get_format_base_format(dst_image
->TexFormat
)) {
641 /* We can't handle format conversions between Z24 and other formats since
642 * we have to lie about the surface format. See the comments in
643 * brw_blorp_surface_info::set().
645 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
646 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
)) {
650 /* We also can't handle any combined depth-stencil formats because we
651 * have to reinterpret as a color format.
653 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
654 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
657 if (!brw
->mesa_format_supports_render
[dst_image
->TexFormat
])
660 /* Source clipping shouldn't be necessary, since copytexsubimage (in
661 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
664 * Destination clipping shouldn't be necessary since the restrictions on
665 * glCopyTexSubImage prevent the user from specifying a destination rectangle
666 * that falls outside the bounds of the destination texture.
667 * See error_check_subtexture_dimensions().
670 int srcY1
= srcY0
+ height
;
671 int srcX1
= srcX0
+ width
;
672 int dstX1
= dstX0
+ width
;
673 int dstY1
= dstY0
+ height
;
675 /* Account for the fact that in the system framebuffer, the origin is at
678 bool mirror_y
= _mesa_is_winsys_fbo(ctx
->ReadBuffer
);
680 apply_y_flip(&srcY0
, &srcY1
, src_rb
->Height
);
682 /* Account for face selection and texture view MinLayer */
683 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
684 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
686 brw_blorp_blit_miptrees(brw
,
687 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
688 src_rb
->Format
, blorp_get_texture_swizzle(src_irb
),
689 dst_mt
, dst_level
, dst_slice
,
690 dst_image
->TexFormat
,
691 srcX0
, srcY0
, srcX1
, srcY1
,
692 dstX0
, dstY0
, dstX1
, dstY1
,
693 GL_NEAREST
, false, mirror_y
,
696 /* If we're copying to a packed depth stencil texture and the source
697 * framebuffer has separate stencil, we need to also copy the stencil data
700 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
701 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
703 src_irb
= intel_renderbuffer(src_rb
);
704 src_mt
= src_irb
->mt
;
706 if (src_mt
->stencil_mt
)
707 src_mt
= src_mt
->stencil_mt
;
708 if (dst_mt
->stencil_mt
)
709 dst_mt
= dst_mt
->stencil_mt
;
711 if (src_mt
!= dst_mt
) {
712 brw_blorp_blit_miptrees(brw
,
713 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
715 blorp_get_texture_swizzle(src_irb
),
716 dst_mt
, dst_level
, dst_slice
,
718 srcX0
, srcY0
, srcX1
, srcY1
,
719 dstX0
, dstY0
, dstX1
, dstY1
,
720 GL_NEAREST
, false, mirror_y
,
730 brw_blorp_framebuffer(struct brw_context
*brw
,
731 struct gl_framebuffer
*readFb
,
732 struct gl_framebuffer
*drawFb
,
733 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
734 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
735 GLbitfield mask
, GLenum filter
)
737 static GLbitfield buffer_bits
[] = {
740 GL_STENCIL_BUFFER_BIT
,
743 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
744 if ((mask
& buffer_bits
[i
]) &&
745 try_blorp_blit(brw
, readFb
, drawFb
,
746 srcX0
, srcY0
, srcX1
, srcY1
,
747 dstX0
, dstY0
, dstX1
, dstY1
,
748 filter
, buffer_bits
[i
])) {
749 mask
&= ~buffer_bits
[i
];
756 static struct brw_bo
*
757 blorp_get_client_bo(struct brw_context
*brw
,
758 unsigned w
, unsigned h
, unsigned d
,
759 GLenum target
, GLenum format
, GLenum type
,
761 const struct gl_pixelstore_attrib
*packing
,
762 uint32_t *offset_out
, uint32_t *row_stride_out
,
763 uint32_t *image_stride_out
, bool read_only
)
765 /* Account for SKIP_PIXELS, SKIP_ROWS, ALIGNMENT, and SKIP_IMAGES */
766 const GLuint dims
= _mesa_get_texture_dimensions(target
);
767 const uint32_t first_pixel
= _mesa_image_offset(dims
, packing
, w
, h
,
768 format
, type
, 0, 0, 0);
769 const uint32_t last_pixel
= _mesa_image_offset(dims
, packing
, w
, h
,
772 const uint32_t stride
= _mesa_image_row_stride(packing
, w
, format
, type
);
773 const uint32_t cpp
= _mesa_bytes_per_pixel(format
, type
);
774 const uint32_t size
= last_pixel
- first_pixel
;
776 *row_stride_out
= stride
;
777 *image_stride_out
= _mesa_image_image_stride(packing
, w
, h
, format
, type
);
779 if (_mesa_is_bufferobj(packing
->BufferObj
)) {
780 const uint32_t offset
= first_pixel
+ (intptr_t)pixels
;
781 if (!read_only
&& ((offset
% cpp
) || (stride
% cpp
))) {
782 perf_debug("Bad PBO alignment; fallback to CPU mapping\n");
786 /* This is a user-provided PBO. We just need to get the BO out */
787 struct intel_buffer_object
*intel_pbo
=
788 intel_buffer_object(packing
->BufferObj
);
790 intel_bufferobj_buffer(brw
, intel_pbo
, offset
, size
, !read_only
);
792 /* We take a reference to the BO so that the caller can just always
793 * unref without having to worry about whether it's a user PBO or one
796 brw_bo_reference(bo
);
798 *offset_out
= offset
;
801 /* Someone should have already checked that there is data to upload. */
804 /* Creating a temp buffer currently only works for upload */
807 /* This is not a user-provided PBO. Instead, pixels is a pointer to CPU
808 * data which we need to copy into a BO.
811 brw_bo_alloc(brw
->bufmgr
, "tmp_tex_subimage_src", size
, 64);
813 perf_debug("intel_texsubimage: temp bo creation failed: size = %u\n",
818 if (brw_bo_subdata(bo
, 0, size
, pixels
+ first_pixel
)) {
819 perf_debug("intel_texsubimage: temp bo upload failed\n");
820 brw_bo_unreference(bo
);
829 /* Consider all the restrictions and determine the format of the source. */
831 blorp_get_client_format(struct brw_context
*brw
,
832 GLenum format
, GLenum type
,
833 const struct gl_pixelstore_attrib
*packing
)
835 if (brw
->ctx
._ImageTransferState
)
836 return MESA_FORMAT_NONE
;
838 if (packing
->SwapBytes
|| packing
->LsbFirst
|| packing
->Invert
) {
839 perf_debug("intel_texsubimage_blorp: unsupported gl_pixelstore_attrib\n");
840 return MESA_FORMAT_NONE
;
843 if (format
!= GL_RED
&&
849 format
!= GL_ALPHA
&&
850 format
!= GL_RED_INTEGER
&&
851 format
!= GL_RG_INTEGER
&&
852 format
!= GL_RGB_INTEGER
&&
853 format
!= GL_BGR_INTEGER
&&
854 format
!= GL_RGBA_INTEGER
&&
855 format
!= GL_BGRA_INTEGER
) {
856 perf_debug("intel_texsubimage_blorp: %s not supported",
857 _mesa_enum_to_string(format
));
858 return MESA_FORMAT_NONE
;
861 return _mesa_tex_format_from_format_and_type(&brw
->ctx
, format
, type
);
865 need_signed_unsigned_int_conversion(mesa_format src_format
,
866 mesa_format dst_format
)
868 const GLenum src_type
= _mesa_get_format_datatype(src_format
);
869 const GLenum dst_type
= _mesa_get_format_datatype(dst_format
);
870 return (src_type
== GL_INT
&& dst_type
== GL_UNSIGNED_INT
) ||
871 (src_type
== GL_UNSIGNED_INT
&& dst_type
== GL_INT
);
875 brw_blorp_upload_miptree(struct brw_context
*brw
,
876 struct intel_mipmap_tree
*dst_mt
,
877 mesa_format dst_format
,
878 uint32_t level
, uint32_t x
, uint32_t y
, uint32_t z
,
879 uint32_t width
, uint32_t height
, uint32_t depth
,
880 GLenum target
, GLenum format
, GLenum type
,
882 const struct gl_pixelstore_attrib
*packing
)
884 const mesa_format src_format
=
885 blorp_get_client_format(brw
, format
, type
, packing
);
886 if (src_format
== MESA_FORMAT_NONE
)
889 if (!brw
->mesa_format_supports_render
[dst_format
]) {
890 perf_debug("intel_texsubimage: can't use %s as render target\n",
891 _mesa_get_format_name(dst_format
));
895 /* This function relies on blorp_blit to upload the pixel data to the
896 * miptree. But, blorp_blit doesn't support signed to unsigned or
897 * unsigned to signed integer conversions.
899 if (need_signed_unsigned_int_conversion(src_format
, dst_format
))
902 uint32_t src_offset
, src_row_stride
, src_image_stride
;
903 struct brw_bo
*src_bo
=
904 blorp_get_client_bo(brw
, width
, height
, depth
,
905 target
, format
, type
, pixels
, packing
,
906 &src_offset
, &src_row_stride
,
907 &src_image_stride
, true);
911 /* Now that source is offset to correct starting point, adjust the
912 * given dimensions to treat 1D arrays as 2D.
914 if (target
== GL_TEXTURE_1D_ARRAY
) {
921 src_image_stride
= src_row_stride
;
924 intel_miptree_check_level_layer(dst_mt
, level
, z
+ depth
- 1);
928 /* Blit slice-by-slice creating a single-slice miptree for each layer. Even
929 * in case of linear buffers hardware wants image arrays to be aligned by
930 * four rows. This way hardware only gets one image at a time and any
931 * source alignment will do.
933 for (unsigned i
= 0; i
< depth
; ++i
) {
934 struct intel_mipmap_tree
*src_mt
= intel_miptree_create_for_bo(
935 brw
, src_bo
, src_format
,
936 src_offset
+ i
* src_image_stride
,
939 ISL_TILING_LINEAR
, 0);
942 perf_debug("intel_texsubimage: miptree creation for src failed\n");
946 /* In case exact match is needed, copy using equivalent UINT formats
947 * preventing hardware from changing presentation for SNORM -1.
949 if (src_mt
->format
== dst_format
) {
950 brw_blorp_copy_miptrees(brw
, src_mt
, 0, 0,
951 dst_mt
, level
, z
+ i
,
952 0, 0, x
, y
, width
, height
);
954 brw_blorp_blit_miptrees(brw
, src_mt
, 0, 0,
955 src_format
, SWIZZLE_XYZW
,
956 dst_mt
, level
, z
+ i
,
959 x
, y
, x
+ width
, y
+ height
,
960 GL_NEAREST
, false, false, false, false);
963 intel_miptree_release(&src_mt
);
969 brw_bo_unreference(src_bo
);
975 brw_blorp_download_miptree(struct brw_context
*brw
,
976 struct intel_mipmap_tree
*src_mt
,
977 mesa_format src_format
, uint32_t src_swizzle
,
978 uint32_t level
, uint32_t x
, uint32_t y
, uint32_t z
,
979 uint32_t width
, uint32_t height
, uint32_t depth
,
980 GLenum target
, GLenum format
, GLenum type
,
981 bool y_flip
, const void *pixels
,
982 const struct gl_pixelstore_attrib
*packing
)
984 const mesa_format dst_format
=
985 blorp_get_client_format(brw
, format
, type
, packing
);
986 if (dst_format
== MESA_FORMAT_NONE
)
989 if (!brw
->mesa_format_supports_render
[dst_format
]) {
990 perf_debug("intel_texsubimage: can't use %s as render target\n",
991 _mesa_get_format_name(dst_format
));
995 /* This function relies on blorp_blit to download the pixel data from the
996 * miptree. But, blorp_blit doesn't support signed to unsigned or unsigned
997 * to signed integer conversions.
999 if (need_signed_unsigned_int_conversion(src_format
, dst_format
))
1002 /* We can't fetch from LUMINANCE or intensity as that would require a
1003 * non-trivial swizzle.
1005 switch (_mesa_get_format_base_format(src_format
)) {
1007 case GL_LUMINANCE_ALPHA
:
1014 /* This pass only works for PBOs */
1015 assert(_mesa_is_bufferobj(packing
->BufferObj
));
1017 uint32_t dst_offset
, dst_row_stride
, dst_image_stride
;
1018 struct brw_bo
*dst_bo
=
1019 blorp_get_client_bo(brw
, width
, height
, depth
,
1020 target
, format
, type
, pixels
, packing
,
1021 &dst_offset
, &dst_row_stride
,
1022 &dst_image_stride
, false);
1026 /* Now that source is offset to correct starting point, adjust the
1027 * given dimensions to treat 1D arrays as 2D.
1029 if (target
== GL_TEXTURE_1D_ARRAY
) {
1036 dst_image_stride
= dst_row_stride
;
1039 intel_miptree_check_level_layer(src_mt
, level
, z
+ depth
- 1);
1042 int y1
= y
+ height
;
1044 apply_y_flip(&y0
, &y1
, minify(src_mt
->surf
.phys_level0_sa
.height
,
1045 level
- src_mt
->first_level
));
1048 bool result
= false;
1050 /* Blit slice-by-slice creating a single-slice miptree for each layer. Even
1051 * in case of linear buffers hardware wants image arrays to be aligned by
1052 * four rows. This way hardware only gets one image at a time and any
1053 * source alignment will do.
1055 for (unsigned i
= 0; i
< depth
; ++i
) {
1056 struct intel_mipmap_tree
*dst_mt
= intel_miptree_create_for_bo(
1057 brw
, dst_bo
, dst_format
,
1058 dst_offset
+ i
* dst_image_stride
,
1061 ISL_TILING_LINEAR
, 0);
1064 perf_debug("intel_texsubimage: miptree creation for src failed\n");
1068 /* In case exact match is needed, copy using equivalent UINT formats
1069 * preventing hardware from changing presentation for SNORM -1.
1071 if (dst_mt
->format
== src_format
&& !y_flip
&&
1072 src_swizzle
== SWIZZLE_XYZW
) {
1073 brw_blorp_copy_miptrees(brw
, src_mt
, level
, z
+ i
,
1075 x
, y
, 0, 0, width
, height
);
1077 brw_blorp_blit_miptrees(brw
, src_mt
, level
, z
+ i
,
1078 src_format
, src_swizzle
,
1079 dst_mt
, 0, 0, dst_format
,
1080 x
, y0
, x
+ width
, y1
,
1081 0, 0, width
, height
,
1082 GL_NEAREST
, false, y_flip
, false, false);
1085 intel_miptree_release(&dst_mt
);
1090 /* As we implement PBO transfers by binding the user-provided BO as a
1091 * fake framebuffer and rendering to it. This breaks the invariant of the
1092 * GL that nothing is able to render to a BO, causing nondeterministic
1093 * corruption issues because the render cache is not coherent with a
1094 * number of other caches that the BO could potentially be bound to
1097 * This could be solved in the same way that we guarantee texture
1098 * coherency after a texture is attached to a framebuffer and
1099 * rendered to, but that would involve checking *all* BOs bound to
1100 * the pipeline for the case we need to emit a cache flush due to
1101 * previous rendering to any of them -- Including vertex, index,
1102 * uniform, atomic counter, shader image, transform feedback,
1103 * indirect draw buffers, etc.
1105 * That would increase the per-draw call overhead even though it's
1106 * very unlikely that any of the BOs bound to the pipeline has been
1107 * rendered to via a PBO at any point, so it seems better to just
1108 * flush here unconditionally.
1110 brw_emit_mi_flush(brw
);
1113 brw_bo_unreference(dst_bo
);
1119 set_write_disables(const struct intel_renderbuffer
*irb
,
1120 const GLubyte
*color_mask
, bool *color_write_disable
)
1122 /* Format information in the renderbuffer represents the requirements
1123 * given by the client. There are cases where the backing miptree uses,
1124 * for example, RGBA to represent RGBX. Since the client is only expecting
1125 * RGB we can treat alpha as not used and write whatever we like into it.
1127 const GLenum base_format
= irb
->Base
.Base
._BaseFormat
;
1128 const int components
= _mesa_base_format_component_count(base_format
);
1129 bool disables
= false;
1131 assert(components
> 0);
1133 for (int i
= 0; i
< components
; i
++) {
1134 color_write_disable
[i
] = !color_mask
[i
];
1135 disables
= disables
|| !color_mask
[i
];
1142 do_single_blorp_clear(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
1143 struct gl_renderbuffer
*rb
, unsigned buf
,
1144 bool partial_clear
, bool encode_srgb
)
1146 struct gl_context
*ctx
= &brw
->ctx
;
1147 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
1148 uint32_t x0
, x1
, y0
, y1
;
1150 mesa_format format
= irb
->Base
.Base
.Format
;
1151 if (!encode_srgb
&& _mesa_get_format_color_encoding(format
) == GL_SRGB
)
1152 format
= _mesa_get_srgb_format_linear(format
);
1153 enum isl_format isl_format
= brw
->mesa_to_isl_render_format
[format
];
1157 if (rb
->Name
!= 0) {
1161 y0
= rb
->Height
- fb
->_Ymax
;
1162 y1
= rb
->Height
- fb
->_Ymin
;
1165 /* If the clear region is empty, just return. */
1166 if (x0
== x1
|| y0
== y1
)
1169 bool can_fast_clear
= !partial_clear
;
1171 bool color_write_disable
[4] = { false, false, false, false };
1172 if (set_write_disables(irb
, ctx
->Color
.ColorMask
[buf
], color_write_disable
))
1173 can_fast_clear
= false;
1175 /* We store clear colors as floats or uints as needed. If there are
1176 * texture views in play, the formats will not properly be respected
1177 * during resolves because the resolve operations only know about the
1178 * miptree and not the renderbuffer.
1180 if (irb
->Base
.Base
.Format
!= irb
->mt
->format
)
1181 can_fast_clear
= false;
1183 if (!irb
->mt
->supports_fast_clear
||
1184 !brw_is_color_fast_clear_compatible(brw
, irb
->mt
, &ctx
->Color
.ClearColor
))
1185 can_fast_clear
= false;
1187 /* Surface state can only record one fast clear color value. Therefore
1188 * unless different levels/layers agree on the color it can be used to
1189 * represent only single level/layer. Here it will be reserved for the
1190 * first slice (level 0, layer 0).
1192 if (irb
->layer_count
> 1 || irb
->mt_level
|| irb
->mt_layer
)
1193 can_fast_clear
= false;
1195 unsigned level
= irb
->mt_level
;
1196 const unsigned num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1198 /* If the MCS buffer hasn't been allocated yet, we need to allocate it now.
1200 if (can_fast_clear
&& !irb
->mt
->mcs_buf
) {
1201 assert(irb
->mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1202 if (!intel_miptree_alloc_ccs(brw
, irb
->mt
)) {
1203 /* There are a few reasons in addition to out-of-memory, that can
1204 * cause intel_miptree_alloc_non_msrt_mcs to fail. Try to recover by
1205 * falling back to non-fast clear.
1207 can_fast_clear
= false;
1211 if (can_fast_clear
) {
1212 const enum isl_aux_state aux_state
=
1213 intel_miptree_get_aux_state(irb
->mt
, irb
->mt_level
, irb
->mt_layer
);
1214 union isl_color_value clear_color
=
1215 brw_meta_convert_fast_clear_color(brw
, irb
->mt
,
1216 &ctx
->Color
.ClearColor
);
1218 bool same_clear_color
=
1219 !intel_miptree_set_clear_color(ctx
, irb
->mt
, clear_color
);
1221 /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
1222 * is redundant and can be skipped.
1224 if (aux_state
== ISL_AUX_STATE_CLEAR
&& same_clear_color
)
1227 DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__
,
1228 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
1230 /* We can't setup the blorp_surf until we've allocated the MCS above */
1231 struct isl_surf isl_tmp
[2];
1232 struct blorp_surf surf
;
1233 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, irb
->mt
->aux_usage
, true,
1234 &level
, irb
->mt_layer
, num_layers
, isl_tmp
);
1236 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1238 * "Any transition from any value in {Clear, Render, Resolve} to a
1239 * different value in {Clear, Render, Resolve} requires end of pipe
1242 * In other words, fast clear ops are not properly synchronized with
1243 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1244 * contents of the previous draw hit the render target before we resolve
1245 * and again afterwards to ensure that the resolve is complete before we
1246 * do any more regular drawing.
1248 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1250 struct blorp_batch batch
;
1251 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1252 blorp_fast_clear(&batch
, &surf
, isl_format
,
1253 level
, irb
->mt_layer
, num_layers
,
1255 blorp_batch_finish(&batch
);
1257 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1259 /* Now that the fast clear has occurred, put the buffer in
1260 * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
1263 intel_miptree_set_aux_state(brw
, irb
->mt
, irb
->mt_level
,
1264 irb
->mt_layer
, num_layers
,
1265 ISL_AUX_STATE_CLEAR
);
1267 DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__
,
1268 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
1270 enum isl_aux_usage aux_usage
=
1271 intel_miptree_render_aux_usage(brw
, irb
->mt
, isl_format
,
1273 intel_miptree_prepare_render(brw
, irb
->mt
, level
, irb
->mt_layer
,
1274 num_layers
, aux_usage
);
1276 struct isl_surf isl_tmp
[2];
1277 struct blorp_surf surf
;
1278 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, aux_usage
, true,
1279 &level
, irb
->mt_layer
, num_layers
, isl_tmp
);
1281 union isl_color_value clear_color
;
1282 memcpy(clear_color
.f32
, ctx
->Color
.ClearColor
.f
, sizeof(float) * 4);
1284 struct blorp_batch batch
;
1285 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1286 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
1287 level
, irb
->mt_layer
, num_layers
,
1289 clear_color
, color_write_disable
);
1290 blorp_batch_finish(&batch
);
1292 intel_miptree_finish_render(brw
, irb
->mt
, level
, irb
->mt_layer
,
1293 num_layers
, aux_usage
);
1300 brw_blorp_clear_color(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
1301 GLbitfield mask
, bool partial_clear
, bool encode_srgb
)
1303 for (unsigned buf
= 0; buf
< fb
->_NumColorDrawBuffers
; buf
++) {
1304 struct gl_renderbuffer
*rb
= fb
->_ColorDrawBuffers
[buf
];
1305 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
1307 /* Only clear the buffers present in the provided mask */
1308 if (((1 << fb
->_ColorDrawBufferIndexes
[buf
]) & mask
) == 0)
1311 /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
1312 * the framebuffer can be complete with some attachments missing. In
1313 * this case the _ColorDrawBuffers pointer will be NULL.
1318 do_single_blorp_clear(brw
, fb
, rb
, buf
, partial_clear
, encode_srgb
);
1319 irb
->need_downsample
= true;
1326 brw_blorp_clear_depth_stencil(struct brw_context
*brw
,
1327 struct gl_framebuffer
*fb
,
1328 GLbitfield mask
, bool partial_clear
)
1330 const struct gl_context
*ctx
= &brw
->ctx
;
1331 struct gl_renderbuffer
*depth_rb
=
1332 fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
;
1333 struct gl_renderbuffer
*stencil_rb
=
1334 fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
1336 if (!depth_rb
|| ctx
->Depth
.Mask
== GL_FALSE
)
1337 mask
&= ~BUFFER_BIT_DEPTH
;
1339 if (!stencil_rb
|| (ctx
->Stencil
.WriteMask
[0] & 0xff) == 0)
1340 mask
&= ~BUFFER_BIT_STENCIL
;
1342 if (!(mask
& (BUFFER_BITS_DEPTH_STENCIL
)))
1345 uint32_t x0
, x1
, y0
, y1
, rb_name
, rb_height
;
1347 rb_name
= depth_rb
->Name
;
1348 rb_height
= depth_rb
->Height
;
1350 assert(depth_rb
->Width
== stencil_rb
->Width
);
1351 assert(depth_rb
->Height
== stencil_rb
->Height
);
1355 rb_name
= stencil_rb
->Name
;
1356 rb_height
= stencil_rb
->Height
;
1365 y0
= rb_height
- fb
->_Ymax
;
1366 y1
= rb_height
- fb
->_Ymin
;
1369 /* If the clear region is empty, just return. */
1370 if (x0
== x1
|| y0
== y1
)
1373 uint32_t level
, start_layer
, num_layers
;
1374 struct isl_surf isl_tmp
[4];
1375 struct blorp_surf depth_surf
, stencil_surf
;
1377 struct intel_mipmap_tree
*depth_mt
= NULL
;
1378 if (mask
& BUFFER_BIT_DEPTH
) {
1379 struct intel_renderbuffer
*irb
= intel_renderbuffer(depth_rb
);
1380 depth_mt
= find_miptree(GL_DEPTH_BUFFER_BIT
, irb
);
1382 level
= irb
->mt_level
;
1383 start_layer
= irb
->mt_layer
;
1384 num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1386 intel_miptree_prepare_depth(brw
, depth_mt
, level
,
1387 start_layer
, num_layers
);
1389 unsigned depth_level
= level
;
1390 blorp_surf_for_miptree(brw
, &depth_surf
, depth_mt
, depth_mt
->aux_usage
,
1391 true, &depth_level
, start_layer
, num_layers
,
1393 assert(depth_level
== level
);
1396 uint8_t stencil_mask
= 0;
1397 struct intel_mipmap_tree
*stencil_mt
= NULL
;
1398 if (mask
& BUFFER_BIT_STENCIL
) {
1399 struct intel_renderbuffer
*irb
= intel_renderbuffer(stencil_rb
);
1400 stencil_mt
= find_miptree(GL_STENCIL_BUFFER_BIT
, irb
);
1402 if (mask
& BUFFER_BIT_DEPTH
) {
1403 assert(level
== irb
->mt_level
);
1404 assert(start_layer
== irb
->mt_layer
);
1405 assert(num_layers
== fb
->MaxNumLayers
? irb
->layer_count
: 1);
1407 level
= irb
->mt_level
;
1408 start_layer
= irb
->mt_layer
;
1409 num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1412 stencil_mask
= ctx
->Stencil
.WriteMask
[0] & 0xff;
1414 intel_miptree_prepare_access(brw
, stencil_mt
, level
, 1,
1415 start_layer
, num_layers
,
1416 ISL_AUX_USAGE_NONE
, false);
1418 unsigned stencil_level
= level
;
1419 blorp_surf_for_miptree(brw
, &stencil_surf
, stencil_mt
,
1420 ISL_AUX_USAGE_NONE
, true,
1421 &stencil_level
, start_layer
, num_layers
,
1425 assert((mask
& BUFFER_BIT_DEPTH
) || stencil_mask
);
1427 struct blorp_batch batch
;
1428 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1429 blorp_clear_depth_stencil(&batch
, &depth_surf
, &stencil_surf
,
1430 level
, start_layer
, num_layers
,
1432 (mask
& BUFFER_BIT_DEPTH
), ctx
->Depth
.Clear
,
1433 stencil_mask
, ctx
->Stencil
.Clear
);
1434 blorp_batch_finish(&batch
);
1436 if (mask
& BUFFER_BIT_DEPTH
) {
1437 intel_miptree_finish_depth(brw
, depth_mt
, level
,
1438 start_layer
, num_layers
, true);
1442 intel_miptree_finish_write(brw
, stencil_mt
, level
,
1443 start_layer
, num_layers
,
1444 ISL_AUX_USAGE_NONE
);
1449 brw_blorp_resolve_color(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1450 unsigned level
, unsigned layer
,
1451 enum blorp_fast_clear_op resolve_op
)
1453 DBG("%s to mt %p level %u layer %u\n", __FUNCTION__
, mt
, level
, layer
);
1455 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
1457 struct isl_surf isl_tmp
[1];
1458 struct blorp_surf surf
;
1459 blorp_surf_for_miptree(brw
, &surf
, mt
, mt
->aux_usage
, true,
1460 &level
, layer
, 1 /* num_layers */,
1463 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1465 * "Any transition from any value in {Clear, Render, Resolve} to a
1466 * different value in {Clear, Render, Resolve} requires end of pipe
1469 * In other words, fast clear ops are not properly synchronized with
1470 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1471 * contents of the previous draw hit the render target before we resolve
1472 * and again afterwards to ensure that the resolve is complete before we
1473 * do any more regular drawing.
1475 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1478 struct blorp_batch batch
;
1479 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1480 blorp_ccs_resolve(&batch
, &surf
, level
, layer
, 1,
1481 brw_blorp_to_isl_format(brw
, format
, true),
1483 blorp_batch_finish(&batch
);
1485 /* See comment above */
1486 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1490 brw_blorp_mcs_partial_resolve(struct brw_context
*brw
,
1491 struct intel_mipmap_tree
*mt
,
1492 uint32_t start_layer
, uint32_t num_layers
)
1494 DBG("%s to mt %p layers %u-%u\n", __FUNCTION__
, mt
,
1495 start_layer
, start_layer
+ num_layers
- 1);
1497 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1499 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
1500 enum isl_format isl_format
= brw_blorp_to_isl_format(brw
, format
, true);
1502 struct isl_surf isl_tmp
[1];
1503 struct blorp_surf surf
;
1505 blorp_surf_for_miptree(brw
, &surf
, mt
, ISL_AUX_USAGE_MCS
, true,
1506 &level
, start_layer
, num_layers
, isl_tmp
);
1508 struct blorp_batch batch
;
1509 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1510 blorp_mcs_partial_resolve(&batch
, &surf
, isl_format
,
1511 start_layer
, num_layers
);
1512 blorp_batch_finish(&batch
);
1516 * Perform a HiZ or depth resolve operation.
1518 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
1519 * PRM, Volume 1, Part 2:
1520 * - 7.5.3.1 Depth Buffer Clear
1521 * - 7.5.3.2 Depth Buffer Resolve
1522 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1525 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1526 unsigned int level
, unsigned int start_layer
,
1527 unsigned int num_layers
, enum blorp_hiz_op op
)
1529 assert(intel_miptree_level_has_hiz(mt
, level
));
1530 assert(op
!= BLORP_HIZ_OP_NONE
);
1531 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1532 const char *opname
= NULL
;
1535 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
1536 opname
= "depth resolve";
1538 case BLORP_HIZ_OP_HIZ_RESOLVE
:
1539 opname
= "hiz ambiguate";
1541 case BLORP_HIZ_OP_DEPTH_CLEAR
:
1542 opname
= "depth clear";
1544 case BLORP_HIZ_OP_NONE
:
1549 DBG("%s %s to mt %p level %d layers %d-%d\n",
1550 __func__
, opname
, mt
, level
, start_layer
, start_layer
+ num_layers
- 1);
1552 /* The following stalls and flushes are only documented to be required for
1553 * HiZ clear operations. However, they also seem to be required for
1554 * resolve operations.
1556 if (devinfo
->gen
== 6) {
1557 /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
1559 * "If other rendering operations have preceded this clear, a
1560 * PIPE_CONTROL with write cache flush enabled and Z-inhibit
1561 * disabled must be issued before the rectangle primitive used for
1562 * the depth buffer clear operation.
1564 brw_emit_pipe_control_flush(brw
,
1565 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1566 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1567 PIPE_CONTROL_CS_STALL
);
1568 } else if (devinfo
->gen
>= 7) {
1570 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
1572 * If other rendering operations have preceded this clear, a
1573 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
1574 * enabled must be issued before the rectangle primitive used for
1575 * the depth buffer clear operation.
1577 * Same applies for Gen8 and Gen9.
1579 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
1580 * PIPE_CONTROL, Depth Cache Flush Enable:
1582 * This bit must not be set when Depth Stall Enable bit is set in
1585 * This is confirmed to hold for real, HSW gets immediate gpu hangs.
1587 * Therefore issue two pipe control flushes, one for cache flush and
1588 * another for depth stall.
1590 brw_emit_pipe_control_flush(brw
,
1591 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1592 PIPE_CONTROL_CS_STALL
);
1594 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
1597 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
&& mt
->hiz_buf
);
1599 struct isl_surf isl_tmp
[2];
1600 struct blorp_surf surf
;
1601 blorp_surf_for_miptree(brw
, &surf
, mt
, ISL_AUX_USAGE_HIZ
, true,
1602 &level
, start_layer
, num_layers
, isl_tmp
);
1604 struct blorp_batch batch
;
1605 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1606 blorp_hiz_op(&batch
, &surf
, level
, start_layer
, num_layers
, op
);
1607 blorp_batch_finish(&batch
);
1609 /* The following stalls and flushes are only documented to be required for
1610 * HiZ clear operations. However, they also seem to be required for
1611 * resolve operations.
1613 if (devinfo
->gen
== 6) {
1614 /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
1616 * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be
1617 * followed by a PIPE_CONTROL command with DEPTH_STALL bit set
1618 * and Then followed by Depth FLUSH'
1620 brw_emit_pipe_control_flush(brw
,
1621 PIPE_CONTROL_DEPTH_STALL
);
1623 brw_emit_pipe_control_flush(brw
,
1624 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1625 PIPE_CONTROL_CS_STALL
);
1626 } else if (devinfo
->gen
>= 8) {
1628 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
1630 * "Depth buffer clear pass using any of the methods (WM_STATE,
1631 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
1632 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
1633 * "set" before starting to render. DepthStall and DepthFlush are
1634 * not needed between consecutive depth clear passes nor is it
1635 * required if the depth clear pass was done with
1636 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
1638 * TODO: Such as the spec says, this could be conditional.
1640 brw_emit_pipe_control_flush(brw
,
1641 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1642 PIPE_CONTROL_DEPTH_STALL
);