2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/blend.h"
27 #include "main/fbobject.h"
28 #include "main/renderbuffer.h"
29 #include "main/glformats.h"
31 #include "brw_blorp.h"
32 #include "brw_context.h"
33 #include "brw_defines.h"
34 #include "brw_meta_util.h"
35 #include "brw_state.h"
36 #include "intel_fbo.h"
37 #include "common/gen_debug.h"
39 #define FILE_DEBUG_FLAG DEBUG_BLORP
42 brw_blorp_lookup_shader(struct blorp_context
*blorp
,
43 const void *key
, uint32_t key_size
,
44 uint32_t *kernel_out
, void *prog_data_out
)
46 struct brw_context
*brw
= blorp
->driver_ctx
;
47 return brw_search_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
,
48 key
, key_size
, kernel_out
, prog_data_out
);
52 brw_blorp_upload_shader(struct blorp_context
*blorp
,
53 const void *key
, uint32_t key_size
,
54 const void *kernel
, uint32_t kernel_size
,
55 const struct brw_stage_prog_data
*prog_data
,
56 uint32_t prog_data_size
,
57 uint32_t *kernel_out
, void *prog_data_out
)
59 struct brw_context
*brw
= blorp
->driver_ctx
;
60 brw_upload_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
, key
, key_size
,
61 kernel
, kernel_size
, prog_data
, prog_data_size
,
62 kernel_out
, prog_data_out
);
67 brw_blorp_init(struct brw_context
*brw
)
69 blorp_init(&brw
->blorp
, brw
, &brw
->isl_dev
);
71 brw
->blorp
.compiler
= brw
->screen
->compiler
;
76 brw
->blorp
.exec
= gen45_blorp_exec
;
78 brw
->blorp
.exec
= gen4_blorp_exec
;
82 brw
->blorp
.exec
= gen5_blorp_exec
;
85 brw
->blorp
.mocs
.tex
= 0;
86 brw
->blorp
.mocs
.rb
= 0;
87 brw
->blorp
.mocs
.vb
= 0;
88 brw
->blorp
.exec
= gen6_blorp_exec
;
91 brw
->blorp
.mocs
.tex
= GEN7_MOCS_L3
;
92 brw
->blorp
.mocs
.rb
= GEN7_MOCS_L3
;
93 brw
->blorp
.mocs
.vb
= GEN7_MOCS_L3
;
94 if (brw
->is_haswell
) {
95 brw
->blorp
.exec
= gen75_blorp_exec
;
97 brw
->blorp
.exec
= gen7_blorp_exec
;
101 brw
->blorp
.mocs
.tex
= BDW_MOCS_WB
;
102 brw
->blorp
.mocs
.rb
= BDW_MOCS_PTE
;
103 brw
->blorp
.mocs
.vb
= BDW_MOCS_WB
;
104 brw
->blorp
.exec
= gen8_blorp_exec
;
107 brw
->blorp
.mocs
.tex
= SKL_MOCS_WB
;
108 brw
->blorp
.mocs
.rb
= SKL_MOCS_PTE
;
109 brw
->blorp
.mocs
.vb
= SKL_MOCS_WB
;
110 brw
->blorp
.exec
= gen9_blorp_exec
;
113 unreachable("Invalid gen");
116 brw
->blorp
.lookup_shader
= brw_blorp_lookup_shader
;
117 brw
->blorp
.upload_shader
= brw_blorp_upload_shader
;
121 apply_gen6_stencil_hiz_offset(struct isl_surf
*surf
,
122 struct intel_mipmap_tree
*mt
,
126 assert(mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
);
128 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
129 /* Note: we can't compute the stencil offset using
130 * intel_miptree_get_aligned_offset(), because the miptree
131 * claims that the region is untiled even though it's W tiled.
133 *offset
= mt
->level
[lod
].level_y
* mt
->pitch
+
134 mt
->level
[lod
].level_x
* 64;
136 *offset
= intel_miptree_get_aligned_offset(mt
,
137 mt
->level
[lod
].level_x
,
138 mt
->level
[lod
].level_y
);
141 surf
->logical_level0_px
.width
= minify(surf
->logical_level0_px
.width
, lod
);
142 surf
->logical_level0_px
.height
= minify(surf
->logical_level0_px
.height
, lod
);
143 surf
->phys_level0_sa
.width
= minify(surf
->phys_level0_sa
.width
, lod
);
144 surf
->phys_level0_sa
.height
= minify(surf
->phys_level0_sa
.height
, lod
);
146 surf
->array_pitch_el_rows
=
147 ALIGN(surf
->phys_level0_sa
.height
, surf
->image_alignment_el
.height
);
151 blorp_surf_for_miptree(struct brw_context
*brw
,
152 struct blorp_surf
*surf
,
153 struct intel_mipmap_tree
*mt
,
154 bool is_render_target
,
155 uint32_t safe_aux_usage
,
157 unsigned start_layer
, unsigned num_layers
,
158 struct isl_surf tmp_surfs
[2])
160 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
161 mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
162 const unsigned num_samples
= MAX2(1, mt
->num_samples
);
163 for (unsigned i
= 0; i
< num_layers
; i
++) {
164 for (unsigned s
= 0; s
< num_samples
; s
++) {
165 const unsigned phys_layer
= (start_layer
+ i
) * num_samples
+ s
;
166 intel_miptree_check_level_layer(mt
, *level
, phys_layer
);
170 for (unsigned i
= 0; i
< num_layers
; i
++)
171 intel_miptree_check_level_layer(mt
, *level
, start_layer
+ i
);
174 intel_miptree_get_isl_surf(brw
, mt
, &tmp_surfs
[0]);
175 surf
->surf
= &tmp_surfs
[0];
176 surf
->addr
= (struct blorp_address
) {
178 .offset
= mt
->offset
,
179 .read_domains
= is_render_target
? I915_GEM_DOMAIN_RENDER
:
180 I915_GEM_DOMAIN_SAMPLER
,
181 .write_domain
= is_render_target
? I915_GEM_DOMAIN_RENDER
: 0,
184 if (brw
->gen
== 6 && mt
->format
== MESA_FORMAT_S_UINT8
&&
185 mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
186 /* Sandy bridge stencil and HiZ use this ALL_SLICES_AT_EACH_LOD hack in
187 * order to allow for layered rendering. The hack makes each LOD of the
188 * stencil or HiZ buffer a single tightly packed array surface at some
189 * offset into the surface. Since ISL doesn't know how to deal with the
190 * crazy ALL_SLICES_AT_EACH_LOD layout and since we have to do a manual
191 * offset of it anyway, we might as well do the offset here and keep the
192 * hacks inside the i965 driver.
194 * See also gen6_depth_stencil_state.c
197 apply_gen6_stencil_hiz_offset(&tmp_surfs
[0], mt
, *level
, &offset
);
198 surf
->addr
.offset
+= offset
;
202 struct isl_surf
*aux_surf
= &tmp_surfs
[1];
203 intel_miptree_get_aux_isl_surf(brw
, mt
, aux_surf
, &surf
->aux_usage
);
205 if (surf
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
206 if (surf
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
207 /* If we're not going to use it as a depth buffer, resolve HiZ */
208 if (!(safe_aux_usage
& (1 << ISL_AUX_USAGE_HIZ
))) {
209 for (unsigned i
= 0; i
< num_layers
; i
++) {
210 intel_miptree_slice_resolve_depth(brw
, mt
, *level
,
213 /* If we're rendering to it then we'll need a HiZ resolve once
214 * we're done before we can use it with HiZ again.
216 if (is_render_target
)
217 intel_miptree_slice_set_needs_hiz_resolve(mt
, *level
,
220 surf
->aux_usage
= ISL_AUX_USAGE_NONE
;
222 } else if (!(safe_aux_usage
& (1 << surf
->aux_usage
))) {
224 if (safe_aux_usage
& (1 << ISL_AUX_USAGE_CCS_E
))
225 flags
|= INTEL_MIPTREE_IGNORE_CCS_E
;
227 intel_miptree_resolve_color(brw
, mt
,
228 *level
, start_layer
, num_layers
, flags
);
230 assert(!intel_miptree_has_color_unresolved(mt
, *level
, 1,
231 start_layer
, num_layers
));
232 surf
->aux_usage
= ISL_AUX_USAGE_NONE
;
236 if (is_render_target
)
237 intel_miptree_used_for_rendering(brw
, mt
, *level
,
238 start_layer
, num_layers
);
240 if (surf
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
241 /* We only really need a clear color if we also have an auxiliary
242 * surface. Without one, it does nothing.
244 surf
->clear_color
= intel_miptree_get_isl_clear_color(brw
, mt
);
246 surf
->aux_surf
= aux_surf
;
247 surf
->aux_addr
= (struct blorp_address
) {
248 .read_domains
= is_render_target
? I915_GEM_DOMAIN_RENDER
:
249 I915_GEM_DOMAIN_SAMPLER
,
250 .write_domain
= is_render_target
? I915_GEM_DOMAIN_RENDER
: 0,
254 surf
->aux_addr
.buffer
= mt
->mcs_buf
->bo
;
255 surf
->aux_addr
.offset
= mt
->mcs_buf
->offset
;
257 assert(surf
->aux_usage
== ISL_AUX_USAGE_HIZ
);
259 surf
->aux_addr
.buffer
= mt
->hiz_buf
->aux_base
.bo
;
260 surf
->aux_addr
.offset
= mt
->hiz_buf
->aux_base
.offset
;
262 struct intel_mipmap_tree
*hiz_mt
= mt
->hiz_buf
->mt
;
264 assert(brw
->gen
== 6 &&
265 hiz_mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
);
267 /* gen6 requires the HiZ buffer to be manually offset to the
268 * right location. We could fixup the surf but it doesn't
269 * matter since most of those fields don't matter.
271 apply_gen6_stencil_hiz_offset(aux_surf
, hiz_mt
, *level
,
272 &surf
->aux_addr
.offset
);
273 assert(hiz_mt
->pitch
== aux_surf
->row_pitch
);
277 surf
->aux_addr
= (struct blorp_address
) {
280 memset(&surf
->clear_color
, 0, sizeof(surf
->clear_color
));
282 assert((surf
->aux_usage
== ISL_AUX_USAGE_NONE
) ==
283 (surf
->aux_addr
.buffer
== NULL
));
285 /* ISL wants real levels, not offset ones. */
286 *level
-= mt
->first_level
;
289 static enum isl_format
290 brw_blorp_to_isl_format(struct brw_context
*brw
, mesa_format format
,
291 bool is_render_target
)
294 case MESA_FORMAT_NONE
:
295 return ISL_FORMAT_UNSUPPORTED
;
296 case MESA_FORMAT_S_UINT8
:
297 return ISL_FORMAT_R8_UINT
;
298 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
299 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
300 return ISL_FORMAT_R24_UNORM_X8_TYPELESS
;
301 case MESA_FORMAT_Z_FLOAT32
:
302 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
303 return ISL_FORMAT_R32_FLOAT
;
304 case MESA_FORMAT_Z_UNORM16
:
305 return ISL_FORMAT_R16_UNORM
;
307 if (is_render_target
) {
308 assert(brw
->format_supported_as_render_target
[format
]);
309 return brw
->render_target_format
[format
];
311 return brw_isl_format_for_mesa_format(format
);
319 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
320 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
322 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
325 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
327 * which is simply adding 4 then modding by 8 (or anding with 7).
329 * We then may need to apply workarounds for textureGather hardware bugs.
331 static enum isl_channel_select
332 swizzle_to_scs(GLenum swizzle
)
334 return (enum isl_channel_select
)((swizzle
+ 4) & 7);
338 physical_to_logical_layer(struct intel_mipmap_tree
*mt
,
339 unsigned physical_layer
)
341 if (mt
->num_samples
> 1 &&
342 (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
343 mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
)) {
344 assert(physical_layer
% mt
->num_samples
== 0);
345 return physical_layer
/ mt
->num_samples
;
347 return physical_layer
;
352 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
353 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
354 * the physical layer holding sample 0. So, for example, if
355 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
359 brw_blorp_blit_miptrees(struct brw_context
*brw
,
360 struct intel_mipmap_tree
*src_mt
,
361 unsigned src_level
, unsigned src_layer
,
362 mesa_format src_format
, int src_swizzle
,
363 struct intel_mipmap_tree
*dst_mt
,
364 unsigned dst_level
, unsigned dst_layer
,
365 mesa_format dst_format
,
366 float src_x0
, float src_y0
,
367 float src_x1
, float src_y1
,
368 float dst_x0
, float dst_y0
,
369 float dst_x1
, float dst_y1
,
370 GLenum filter
, bool mirror_x
, bool mirror_y
,
371 bool decode_srgb
, bool encode_srgb
)
373 /* Blorp operates in logical layers */
374 src_layer
= physical_to_logical_layer(src_mt
, src_layer
);
375 dst_layer
= physical_to_logical_layer(dst_mt
, dst_layer
);
377 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
378 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
380 src_mt
->num_samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
381 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
382 dst_mt
->num_samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
383 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
386 if (!decode_srgb
&& _mesa_get_format_color_encoding(src_format
) == GL_SRGB
)
387 src_format
= _mesa_get_srgb_format_linear(src_format
);
389 if (!encode_srgb
&& _mesa_get_format_color_encoding(dst_format
) == GL_SRGB
)
390 dst_format
= _mesa_get_srgb_format_linear(dst_format
);
392 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
393 * texture, the above code configures the source format for L32_FLOAT or
394 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
395 * the SAMPLE message appears to handle multisampled L32_FLOAT and
396 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
397 * around the problem by using a source format of R32_FLOAT. This
398 * shouldn't affect rendering correctness, since the destination format is
399 * R32_FLOAT, so only the contents of the red channel matters.
402 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1 &&
403 src_mt
->format
== dst_mt
->format
&&
404 (dst_format
== MESA_FORMAT_L_FLOAT32
||
405 dst_format
== MESA_FORMAT_I_FLOAT32
)) {
406 src_format
= dst_format
= MESA_FORMAT_R_FLOAT32
;
409 uint32_t src_usage_flags
= (1 << ISL_AUX_USAGE_MCS
);
410 if (src_format
== src_mt
->format
)
411 src_usage_flags
|= (1 << ISL_AUX_USAGE_CCS_E
);
413 uint32_t dst_usage_flags
= (1 << ISL_AUX_USAGE_MCS
);
414 if (dst_format
== dst_mt
->format
) {
415 dst_usage_flags
|= (1 << ISL_AUX_USAGE_CCS_E
) |
416 (1 << ISL_AUX_USAGE_CCS_D
);
419 struct isl_surf tmp_surfs
[4];
420 struct blorp_surf src_surf
, dst_surf
;
421 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, false, src_usage_flags
,
422 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
423 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, true, dst_usage_flags
,
424 &dst_level
, dst_layer
, 1, &tmp_surfs
[2]);
426 struct isl_swizzle src_isl_swizzle
= {
427 .r
= swizzle_to_scs(GET_SWZ(src_swizzle
, 0)),
428 .g
= swizzle_to_scs(GET_SWZ(src_swizzle
, 1)),
429 .b
= swizzle_to_scs(GET_SWZ(src_swizzle
, 2)),
430 .a
= swizzle_to_scs(GET_SWZ(src_swizzle
, 3)),
433 struct blorp_batch batch
;
434 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
435 blorp_blit(&batch
, &src_surf
, src_level
, src_layer
,
436 brw_blorp_to_isl_format(brw
, src_format
, false), src_isl_swizzle
,
437 &dst_surf
, dst_level
, dst_layer
,
438 brw_blorp_to_isl_format(brw
, dst_format
, true),
439 ISL_SWIZZLE_IDENTITY
,
440 src_x0
, src_y0
, src_x1
, src_y1
,
441 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
442 filter
, mirror_x
, mirror_y
);
443 blorp_batch_finish(&batch
);
447 brw_blorp_copy_miptrees(struct brw_context
*brw
,
448 struct intel_mipmap_tree
*src_mt
,
449 unsigned src_level
, unsigned src_layer
,
450 struct intel_mipmap_tree
*dst_mt
,
451 unsigned dst_level
, unsigned dst_layer
,
452 unsigned src_x
, unsigned src_y
,
453 unsigned dst_x
, unsigned dst_y
,
454 unsigned src_width
, unsigned src_height
)
456 DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
457 "to %dx %s mt %p %d %d (%d,%d)\n",
459 src_mt
->num_samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
460 src_level
, src_layer
, src_x
, src_y
, src_width
, src_height
,
461 dst_mt
->num_samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
462 dst_level
, dst_layer
, dst_x
, dst_y
);
464 struct isl_surf tmp_surfs
[4];
465 struct blorp_surf src_surf
, dst_surf
;
466 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, false,
467 (1 << ISL_AUX_USAGE_MCS
) |
468 (1 << ISL_AUX_USAGE_CCS_E
),
469 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
470 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, true,
471 (1 << ISL_AUX_USAGE_MCS
) |
472 (1 << ISL_AUX_USAGE_CCS_E
),
473 &dst_level
, dst_layer
, 1, &tmp_surfs
[2]);
475 struct blorp_batch batch
;
476 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
477 blorp_copy(&batch
, &src_surf
, src_level
, src_layer
,
478 &dst_surf
, dst_level
, dst_layer
,
479 src_x
, src_y
, dst_x
, dst_y
, src_width
, src_height
);
480 blorp_batch_finish(&batch
);
483 static struct intel_mipmap_tree
*
484 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
486 struct intel_mipmap_tree
*mt
= irb
->mt
;
487 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
493 blorp_get_texture_swizzle(const struct intel_renderbuffer
*irb
)
495 return irb
->Base
.Base
._BaseFormat
== GL_RGB
?
496 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ONE
) :
501 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
502 struct intel_renderbuffer
*src_irb
, mesa_format src_format
,
503 struct intel_renderbuffer
*dst_irb
, mesa_format dst_format
,
504 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
505 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
506 GLenum filter
, bool mirror_x
, bool mirror_y
)
508 const struct gl_context
*ctx
= &brw
->ctx
;
510 /* Find source/dst miptrees */
511 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
512 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
514 const bool do_srgb
= ctx
->Color
.sRGBEnabled
;
517 brw_blorp_blit_miptrees(brw
,
518 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
519 src_format
, blorp_get_texture_swizzle(src_irb
),
520 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
522 srcX0
, srcY0
, srcX1
, srcY1
,
523 dstX0
, dstY0
, dstX1
, dstY1
,
524 filter
, mirror_x
, mirror_y
,
527 dst_irb
->need_downsample
= true;
531 try_blorp_blit(struct brw_context
*brw
,
532 const struct gl_framebuffer
*read_fb
,
533 const struct gl_framebuffer
*draw_fb
,
534 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
535 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
536 GLenum filter
, GLbitfield buffer_bit
)
538 struct gl_context
*ctx
= &brw
->ctx
;
540 /* Sync up the state of window system buffers. We need to do this before
541 * we go looking for the buffers.
543 intel_prepare_render(brw
);
545 bool mirror_x
, mirror_y
;
546 if (brw_meta_mirror_clip_and_scissor(ctx
, read_fb
, draw_fb
,
547 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
548 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
549 &mirror_x
, &mirror_y
))
553 struct intel_renderbuffer
*src_irb
;
554 struct intel_renderbuffer
*dst_irb
;
555 struct intel_mipmap_tree
*src_mt
;
556 struct intel_mipmap_tree
*dst_mt
;
557 switch (buffer_bit
) {
558 case GL_COLOR_BUFFER_BIT
:
559 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
560 for (unsigned i
= 0; i
< draw_fb
->_NumColorDrawBuffers
; ++i
) {
561 dst_irb
= intel_renderbuffer(draw_fb
->_ColorDrawBuffers
[i
]);
563 do_blorp_blit(brw
, buffer_bit
,
564 src_irb
, src_irb
->Base
.Base
.Format
,
565 dst_irb
, dst_irb
->Base
.Base
.Format
,
566 srcX0
, srcY0
, srcX1
, srcY1
,
567 dstX0
, dstY0
, dstX1
, dstY1
,
568 filter
, mirror_x
, mirror_y
);
571 case GL_DEPTH_BUFFER_BIT
:
573 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
575 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
576 src_mt
= find_miptree(buffer_bit
, src_irb
);
577 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
579 /* We can't handle format conversions between Z24 and other formats
580 * since we have to lie about the surface format. See the comments in
581 * brw_blorp_surface_info::set().
583 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
584 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
))
587 /* We also can't handle any combined depth-stencil formats because we
588 * have to reinterpret as a color format.
590 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
591 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
594 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
595 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
596 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
597 filter
, mirror_x
, mirror_y
);
599 case GL_STENCIL_BUFFER_BIT
:
600 /* Blorp doesn't support combined depth stencil which is all we have
607 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
609 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
610 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
611 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
612 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
613 filter
, mirror_x
, mirror_y
);
616 unreachable("not reached");
623 brw_blorp_copytexsubimage(struct brw_context
*brw
,
624 struct gl_renderbuffer
*src_rb
,
625 struct gl_texture_image
*dst_image
,
627 int srcX0
, int srcY0
,
628 int dstX0
, int dstY0
,
629 int width
, int height
)
631 struct gl_context
*ctx
= &brw
->ctx
;
632 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
633 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
635 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
636 if (brw
->ctx
._ImageTransferState
)
639 /* Sync up the state of window system buffers. We need to do this before
640 * we go looking at the src renderbuffer's miptree.
642 intel_prepare_render(brw
);
644 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
645 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
647 /* There is support for only up to eight samples. */
648 if (src_mt
->num_samples
> 8 || dst_mt
->num_samples
> 8)
651 if (_mesa_get_format_base_format(src_rb
->Format
) !=
652 _mesa_get_format_base_format(dst_image
->TexFormat
)) {
656 /* We can't handle format conversions between Z24 and other formats since
657 * we have to lie about the surface format. See the comments in
658 * brw_blorp_surface_info::set().
660 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
661 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
)) {
665 /* We also can't handle any combined depth-stencil formats because we
666 * have to reinterpret as a color format.
668 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
669 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
672 if (!brw
->format_supported_as_render_target
[dst_image
->TexFormat
])
675 /* Source clipping shouldn't be necessary, since copytexsubimage (in
676 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
679 * Destination clipping shouldn't be necessary since the restrictions on
680 * glCopyTexSubImage prevent the user from specifying a destination rectangle
681 * that falls outside the bounds of the destination texture.
682 * See error_check_subtexture_dimensions().
685 int srcY1
= srcY0
+ height
;
686 int srcX1
= srcX0
+ width
;
687 int dstX1
= dstX0
+ width
;
688 int dstY1
= dstY0
+ height
;
690 /* Account for the fact that in the system framebuffer, the origin is at
693 bool mirror_y
= false;
694 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
695 GLint tmp
= src_rb
->Height
- srcY0
;
696 srcY0
= src_rb
->Height
- srcY1
;
701 /* Account for face selection and texture view MinLayer */
702 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
703 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
705 brw_blorp_blit_miptrees(brw
,
706 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
707 src_rb
->Format
, blorp_get_texture_swizzle(src_irb
),
708 dst_mt
, dst_level
, dst_slice
,
709 dst_image
->TexFormat
,
710 srcX0
, srcY0
, srcX1
, srcY1
,
711 dstX0
, dstY0
, dstX1
, dstY1
,
712 GL_NEAREST
, false, mirror_y
,
715 /* If we're copying to a packed depth stencil texture and the source
716 * framebuffer has separate stencil, we need to also copy the stencil data
719 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
720 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
722 src_irb
= intel_renderbuffer(src_rb
);
723 src_mt
= src_irb
->mt
;
725 if (src_mt
->stencil_mt
)
726 src_mt
= src_mt
->stencil_mt
;
727 if (dst_mt
->stencil_mt
)
728 dst_mt
= dst_mt
->stencil_mt
;
730 if (src_mt
!= dst_mt
) {
731 brw_blorp_blit_miptrees(brw
,
732 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
734 blorp_get_texture_swizzle(src_irb
),
735 dst_mt
, dst_level
, dst_slice
,
737 srcX0
, srcY0
, srcX1
, srcY1
,
738 dstX0
, dstY0
, dstX1
, dstY1
,
739 GL_NEAREST
, false, mirror_y
,
749 brw_blorp_framebuffer(struct brw_context
*brw
,
750 struct gl_framebuffer
*readFb
,
751 struct gl_framebuffer
*drawFb
,
752 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
753 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
754 GLbitfield mask
, GLenum filter
)
756 static GLbitfield buffer_bits
[] = {
759 GL_STENCIL_BUFFER_BIT
,
762 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
763 if ((mask
& buffer_bits
[i
]) &&
764 try_blorp_blit(brw
, readFb
, drawFb
,
765 srcX0
, srcY0
, srcX1
, srcY1
,
766 dstX0
, dstY0
, dstX1
, dstY1
,
767 filter
, buffer_bits
[i
])) {
768 mask
&= ~buffer_bits
[i
];
776 set_write_disables(const struct intel_renderbuffer
*irb
,
777 const GLubyte
*color_mask
, bool *color_write_disable
)
779 /* Format information in the renderbuffer represents the requirements
780 * given by the client. There are cases where the backing miptree uses,
781 * for example, RGBA to represent RGBX. Since the client is only expecting
782 * RGB we can treat alpha as not used and write whatever we like into it.
784 const GLenum base_format
= irb
->Base
.Base
._BaseFormat
;
785 const int components
= _mesa_base_format_component_count(base_format
);
786 bool disables
= false;
788 assert(components
> 0);
790 for (int i
= 0; i
< components
; i
++) {
791 color_write_disable
[i
] = !color_mask
[i
];
792 disables
= disables
|| !color_mask
[i
];
799 irb_logical_mt_layer(struct intel_renderbuffer
*irb
)
801 return physical_to_logical_layer(irb
->mt
, irb
->mt_layer
);
805 do_single_blorp_clear(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
806 struct gl_renderbuffer
*rb
, unsigned buf
,
807 bool partial_clear
, bool encode_srgb
)
809 struct gl_context
*ctx
= &brw
->ctx
;
810 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
811 mesa_format format
= irb
->mt
->format
;
812 uint32_t x0
, x1
, y0
, y1
;
814 if (!encode_srgb
&& _mesa_get_format_color_encoding(format
) == GL_SRGB
)
815 format
= _mesa_get_srgb_format_linear(format
);
823 y0
= rb
->Height
- fb
->_Ymax
;
824 y1
= rb
->Height
- fb
->_Ymin
;
827 /* If the clear region is empty, just return. */
828 if (x0
== x1
|| y0
== y1
)
831 bool can_fast_clear
= !partial_clear
;
833 bool color_write_disable
[4] = { false, false, false, false };
834 if (set_write_disables(irb
, ctx
->Color
.ColorMask
[buf
], color_write_disable
))
835 can_fast_clear
= false;
837 if (irb
->mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
||
838 !brw_is_color_fast_clear_compatible(brw
, irb
->mt
, &ctx
->Color
.ClearColor
))
839 can_fast_clear
= false;
841 const unsigned logical_layer
= irb_logical_mt_layer(irb
);
842 const enum intel_fast_clear_state fast_clear_state
=
843 intel_miptree_get_fast_clear_state(irb
->mt
, irb
->mt_level
,
846 /* Surface state can only record one fast clear color value. Therefore
847 * unless different levels/layers agree on the color it can be used to
848 * represent only single level/layer. Here it will be reserved for the
849 * first slice (level 0, layer 0).
851 if (irb
->layer_count
> 1 || irb
->mt_level
|| irb
->mt_layer
)
852 can_fast_clear
= false;
854 if (can_fast_clear
) {
855 union gl_color_union override_color
=
856 brw_meta_convert_fast_clear_color(brw
, irb
->mt
,
857 &ctx
->Color
.ClearColor
);
859 /* Record the clear color in the miptree so that it will be
860 * programmed in SURFACE_STATE by later rendering and resolve
863 const bool color_updated
= brw_meta_set_fast_clear_color(
864 brw
, &irb
->mt
->gen9_fast_clear_color
,
867 /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
868 * is redundant and can be skipped.
870 if (!color_updated
&& fast_clear_state
== INTEL_FAST_CLEAR_STATE_CLEAR
)
873 /* If the MCS buffer hasn't been allocated yet, we need to allocate
876 if (!irb
->mt
->mcs_buf
) {
877 assert(!intel_miptree_is_lossless_compressed(brw
, irb
->mt
));
878 if (!intel_miptree_alloc_non_msrt_mcs(brw
, irb
->mt
, false)) {
879 /* MCS allocation failed--probably this will only happen in
880 * out-of-memory conditions. But in any case, try to recover
881 * by falling back to a non-blorp clear technique.
888 const unsigned num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
890 /* We can't setup the blorp_surf until we've allocated the MCS above */
891 struct isl_surf isl_tmp
[2];
892 struct blorp_surf surf
;
893 unsigned level
= irb
->mt_level
;
894 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, true,
895 (1 << ISL_AUX_USAGE_MCS
) |
896 (1 << ISL_AUX_USAGE_CCS_E
) |
897 (1 << ISL_AUX_USAGE_CCS_D
),
898 &level
, logical_layer
, num_layers
, isl_tmp
);
900 if (can_fast_clear
) {
901 DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__
,
902 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
904 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
906 * "Any transition from any value in {Clear, Render, Resolve} to a
907 * different value in {Clear, Render, Resolve} requires end of pipe
910 * In other words, fast clear ops are not properly synchronized with
911 * other drawing. We need to use a PIPE_CONTROL to ensure that the
912 * contents of the previous draw hit the render target before we resolve
913 * and again afterwards to ensure that the resolve is complete before we
914 * do any more regular drawing.
916 brw_emit_pipe_control_flush(brw
,
917 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
918 PIPE_CONTROL_CS_STALL
);
920 struct blorp_batch batch
;
921 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
922 blorp_fast_clear(&batch
, &surf
,
923 brw
->render_target_format
[format
],
924 level
, logical_layer
, num_layers
,
926 blorp_batch_finish(&batch
);
928 brw_emit_pipe_control_flush(brw
,
929 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
930 PIPE_CONTROL_CS_STALL
);
932 /* Now that the fast clear has occurred, put the buffer in
933 * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
936 intel_miptree_set_fast_clear_state(brw
, irb
->mt
, irb
->mt_level
,
937 logical_layer
, num_layers
,
938 INTEL_FAST_CLEAR_STATE_CLEAR
);
940 DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__
,
941 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
943 union isl_color_value clear_color
;
944 memcpy(clear_color
.f32
, ctx
->Color
.ClearColor
.f
, sizeof(float) * 4);
946 struct blorp_batch batch
;
947 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
948 blorp_clear(&batch
, &surf
,
949 brw
->render_target_format
[format
],
950 ISL_SWIZZLE_IDENTITY
,
951 level
, irb_logical_mt_layer(irb
), num_layers
,
953 clear_color
, color_write_disable
);
954 blorp_batch_finish(&batch
);
961 brw_blorp_clear_color(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
962 GLbitfield mask
, bool partial_clear
, bool encode_srgb
)
964 for (unsigned buf
= 0; buf
< fb
->_NumColorDrawBuffers
; buf
++) {
965 struct gl_renderbuffer
*rb
= fb
->_ColorDrawBuffers
[buf
];
966 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
968 /* Only clear the buffers present in the provided mask */
969 if (((1 << fb
->_ColorDrawBufferIndexes
[buf
]) & mask
) == 0)
972 /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
973 * the framebuffer can be complete with some attachments missing. In
974 * this case the _ColorDrawBuffers pointer will be NULL.
979 if (!do_single_blorp_clear(brw
, fb
, rb
, buf
, partial_clear
,
984 irb
->need_downsample
= true;
991 brw_blorp_resolve_color(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
992 unsigned level
, unsigned layer
)
994 DBG("%s to mt %p level %u layer %u\n", __FUNCTION__
, mt
, level
, layer
);
996 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
998 struct isl_surf isl_tmp
[2];
999 struct blorp_surf surf
;
1000 blorp_surf_for_miptree(brw
, &surf
, mt
, true,
1001 (1 << ISL_AUX_USAGE_CCS_E
) |
1002 (1 << ISL_AUX_USAGE_CCS_D
),
1003 &level
, layer
, 1 /* num_layers */,
1006 enum blorp_fast_clear_op resolve_op
;
1007 if (brw
->gen
>= 9) {
1008 if (surf
.aux_usage
== ISL_AUX_USAGE_CCS_E
)
1009 resolve_op
= BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1011 resolve_op
= BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
1013 assert(surf
.aux_usage
== ISL_AUX_USAGE_CCS_D
);
1014 /* Broadwell and earlier do not have a partial resolve */
1015 resolve_op
= BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1018 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1020 * "Any transition from any value in {Clear, Render, Resolve} to a
1021 * different value in {Clear, Render, Resolve} requires end of pipe
1024 * In other words, fast clear ops are not properly synchronized with
1025 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1026 * contents of the previous draw hit the render target before we resolve
1027 * and again afterwards to ensure that the resolve is complete before we
1028 * do any more regular drawing.
1030 brw_emit_pipe_control_flush(brw
,
1031 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1032 PIPE_CONTROL_CS_STALL
);
1035 struct blorp_batch batch
;
1036 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1037 blorp_ccs_resolve(&batch
, &surf
, level
, layer
,
1038 brw_blorp_to_isl_format(brw
, format
, true),
1040 blorp_batch_finish(&batch
);
1042 /* See comment above */
1043 brw_emit_pipe_control_flush(brw
,
1044 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1045 PIPE_CONTROL_CS_STALL
);
1049 gen6_blorp_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1050 unsigned int level
, unsigned int layer
, enum blorp_hiz_op op
)
1052 assert(intel_miptree_level_has_hiz(mt
, level
));
1054 struct isl_surf isl_tmp
[2];
1055 struct blorp_surf surf
;
1056 blorp_surf_for_miptree(brw
, &surf
, mt
, true, (1 << ISL_AUX_USAGE_HIZ
),
1057 &level
, layer
, 1, isl_tmp
);
1059 struct blorp_batch batch
;
1060 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1061 blorp_gen6_hiz_op(&batch
, &surf
, level
, layer
, op
);
1062 blorp_batch_finish(&batch
);
1066 * Perform a HiZ or depth resolve operation.
1068 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
1069 * PRM, Volume 1, Part 2:
1070 * - 7.5.3.1 Depth Buffer Clear
1071 * - 7.5.3.2 Depth Buffer Resolve
1072 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1075 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1076 unsigned int level
, unsigned int layer
, enum blorp_hiz_op op
)
1078 const char *opname
= NULL
;
1081 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
1082 opname
= "depth resolve";
1084 case BLORP_HIZ_OP_HIZ_RESOLVE
:
1085 opname
= "hiz ambiguate";
1087 case BLORP_HIZ_OP_DEPTH_CLEAR
:
1088 opname
= "depth clear";
1090 case BLORP_HIZ_OP_NONE
:
1095 DBG("%s %s to mt %p level %d layer %d\n",
1096 __func__
, opname
, mt
, level
, layer
);
1098 if (brw
->gen
>= 8) {
1099 gen8_hiz_exec(brw
, mt
, level
, layer
, op
);
1101 gen6_blorp_hiz_exec(brw
, mt
, level
, layer
, op
);