2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/blend.h"
27 #include "main/bufferobj.h"
28 #include "main/enums.h"
29 #include "main/fbobject.h"
30 #include "main/image.h"
31 #include "main/renderbuffer.h"
32 #include "main/glformats.h"
34 #include "brw_blorp.h"
35 #include "brw_context.h"
36 #include "brw_defines.h"
37 #include "brw_meta_util.h"
38 #include "brw_state.h"
39 #include "intel_buffer_objects.h"
40 #include "intel_fbo.h"
41 #include "dev/gen_debug.h"
43 #define FILE_DEBUG_FLAG DEBUG_BLORP
46 brw_blorp_lookup_shader(struct blorp_batch
*batch
,
47 const void *key
, uint32_t key_size
,
48 uint32_t *kernel_out
, void *prog_data_out
)
50 struct brw_context
*brw
= batch
->driver_batch
;
51 return brw_search_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
, key
, key_size
,
52 kernel_out
, prog_data_out
, true);
56 brw_blorp_upload_shader(struct blorp_batch
*batch
, uint32_t stage
,
57 const void *key
, uint32_t key_size
,
58 const void *kernel
, uint32_t kernel_size
,
59 const struct brw_stage_prog_data
*prog_data
,
60 uint32_t prog_data_size
,
61 uint32_t *kernel_out
, void *prog_data_out
)
63 struct brw_context
*brw
= batch
->driver_batch
;
64 brw_upload_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
, key
, key_size
,
65 kernel
, kernel_size
, prog_data
, prog_data_size
,
66 kernel_out
, prog_data_out
);
71 brw_blorp_init(struct brw_context
*brw
)
73 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
75 blorp_init(&brw
->blorp
, brw
, &brw
->isl_dev
);
77 brw
->blorp
.compiler
= brw
->screen
->compiler
;
79 switch (devinfo
->gen
) {
81 if (devinfo
->is_g4x
) {
82 brw
->blorp
.exec
= gen45_blorp_exec
;
84 brw
->blorp
.exec
= gen4_blorp_exec
;
88 brw
->blorp
.exec
= gen5_blorp_exec
;
91 brw
->blorp
.exec
= gen6_blorp_exec
;
94 if (devinfo
->is_haswell
) {
95 brw
->blorp
.exec
= gen75_blorp_exec
;
97 brw
->blorp
.exec
= gen7_blorp_exec
;
101 brw
->blorp
.exec
= gen8_blorp_exec
;
104 brw
->blorp
.exec
= gen9_blorp_exec
;
107 brw
->blorp
.exec
= gen10_blorp_exec
;
110 brw
->blorp
.exec
= gen11_blorp_exec
;
114 unreachable("Invalid gen");
117 brw
->blorp
.lookup_shader
= brw_blorp_lookup_shader
;
118 brw
->blorp
.upload_shader
= brw_blorp_upload_shader
;
122 blorp_surf_for_miptree(struct brw_context
*brw
,
123 struct blorp_surf
*surf
,
124 const struct intel_mipmap_tree
*mt
,
125 enum isl_aux_usage aux_usage
,
126 bool is_render_target
,
128 unsigned start_layer
, unsigned num_layers
)
130 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
132 if (mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
) {
133 const unsigned num_samples
= mt
->surf
.samples
;
134 for (unsigned i
= 0; i
< num_layers
; i
++) {
135 for (unsigned s
= 0; s
< num_samples
; s
++) {
136 const unsigned phys_layer
= (start_layer
+ i
) * num_samples
+ s
;
137 intel_miptree_check_level_layer(mt
, *level
, phys_layer
);
141 for (unsigned i
= 0; i
< num_layers
; i
++)
142 intel_miptree_check_level_layer(mt
, *level
, start_layer
+ i
);
145 *surf
= (struct blorp_surf
) {
147 .addr
= (struct blorp_address
) {
149 .offset
= mt
->offset
,
150 .reloc_flags
= is_render_target
? EXEC_OBJECT_WRITE
: 0,
151 .mocs
= brw_get_bo_mocs(devinfo
, mt
->bo
),
153 .aux_usage
= aux_usage
,
154 .tile_x_sa
= mt
->level
[*level
].level_x
,
155 .tile_y_sa
= mt
->level
[*level
].level_y
,
158 if (surf
->aux_usage
== ISL_AUX_USAGE_HIZ
&&
159 !intel_miptree_level_has_hiz(mt
, *level
))
160 surf
->aux_usage
= ISL_AUX_USAGE_NONE
;
162 if (surf
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
163 /* We only really need a clear color if we also have an auxiliary
164 * surface. Without one, it does nothing.
167 intel_miptree_get_clear_color(devinfo
, mt
, mt
->surf
.format
,
168 !is_render_target
, (struct brw_bo
**)
169 &surf
->clear_color_addr
.buffer
,
170 &surf
->clear_color_addr
.offset
);
172 surf
->aux_surf
= &mt
->aux_buf
->surf
;
173 surf
->aux_addr
= (struct blorp_address
) {
174 .reloc_flags
= is_render_target
? EXEC_OBJECT_WRITE
: 0,
175 .mocs
= surf
->addr
.mocs
,
178 surf
->aux_addr
.buffer
= mt
->aux_buf
->bo
;
179 surf
->aux_addr
.offset
= mt
->aux_buf
->offset
;
181 surf
->aux_addr
= (struct blorp_address
) {
184 memset(&surf
->clear_color
, 0, sizeof(surf
->clear_color
));
186 assert((surf
->aux_usage
== ISL_AUX_USAGE_NONE
) ==
187 (surf
->aux_addr
.buffer
== NULL
));
189 if (!is_render_target
&& brw
->screen
->devinfo
.gen
== 9)
190 gen9_apply_single_tex_astc5x5_wa(brw
, mt
->format
, surf
->aux_usage
);
192 /* ISL wants real levels, not offset ones. */
193 *level
-= mt
->first_level
;
197 brw_blorp_supports_dst_format(struct brw_context
*brw
, mesa_format format
)
199 /* If it's renderable, it's definitely supported. */
200 if (brw
->mesa_format_supports_render
[format
])
203 /* BLORP can't compress anything */
204 if (_mesa_is_format_compressed(format
))
207 /* No exotic formats such as GL_LUMINANCE_ALPHA */
208 if (_mesa_get_format_bits(format
, GL_RED_BITS
) == 0 &&
209 _mesa_get_format_bits(format
, GL_DEPTH_BITS
) == 0 &&
210 _mesa_get_format_bits(format
, GL_STENCIL_BITS
) == 0)
216 static enum isl_format
217 brw_blorp_to_isl_format(struct brw_context
*brw
, mesa_format format
,
218 bool is_render_target
)
221 case MESA_FORMAT_NONE
:
222 return ISL_FORMAT_UNSUPPORTED
;
223 case MESA_FORMAT_S_UINT8
:
224 return ISL_FORMAT_R8_UINT
;
225 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
226 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
227 return ISL_FORMAT_R24_UNORM_X8_TYPELESS
;
228 case MESA_FORMAT_Z_FLOAT32
:
229 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
230 return ISL_FORMAT_R32_FLOAT
;
231 case MESA_FORMAT_Z_UNORM16
:
232 return ISL_FORMAT_R16_UNORM
;
234 if (is_render_target
) {
235 assert(brw_blorp_supports_dst_format(brw
, format
));
236 if (brw
->mesa_format_supports_render
[format
]) {
237 return brw
->mesa_to_isl_render_format
[format
];
239 return brw_isl_format_for_mesa_format(format
);
242 /* Some destinations (is_render_target == true) are supported by
243 * blorp even though we technically can't render to them.
245 return brw_isl_format_for_mesa_format(format
);
251 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
252 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
254 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
257 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
259 * which is simply adding 4 then modding by 8 (or anding with 7).
261 * We then may need to apply workarounds for textureGather hardware bugs.
263 static enum isl_channel_select
264 swizzle_to_scs(GLenum swizzle
)
266 return (enum isl_channel_select
)((swizzle
+ 4) & 7);
270 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
271 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
272 * the physical layer holding sample 0. So, for example, if
273 * src_mt->surf.samples == 4, then logical layer n corresponds to src_layer ==
277 brw_blorp_blit_miptrees(struct brw_context
*brw
,
278 struct intel_mipmap_tree
*src_mt
,
279 unsigned src_level
, unsigned src_layer
,
280 mesa_format src_format
, int src_swizzle
,
281 struct intel_mipmap_tree
*dst_mt
,
282 unsigned dst_level
, unsigned dst_layer
,
283 mesa_format dst_format
,
284 float src_x0
, float src_y0
,
285 float src_x1
, float src_y1
,
286 float dst_x0
, float dst_y0
,
287 float dst_x1
, float dst_y1
,
288 GLenum gl_filter
, bool mirror_x
, bool mirror_y
,
289 bool decode_srgb
, bool encode_srgb
)
291 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
293 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f) "
294 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
296 src_mt
->surf
.samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
297 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
298 dst_mt
->surf
.samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
299 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
302 if (src_format
== MESA_FORMAT_NONE
)
303 src_format
= src_mt
->format
;
305 if (dst_format
== MESA_FORMAT_NONE
)
306 dst_format
= dst_mt
->format
;
309 src_format
= _mesa_get_srgb_format_linear(src_format
);
312 dst_format
= _mesa_get_srgb_format_linear(dst_format
);
314 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
315 * texture, the above code configures the source format for L32_FLOAT or
316 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
317 * the SAMPLE message appears to handle multisampled L32_FLOAT and
318 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
319 * around the problem by using a source format of R32_FLOAT. This
320 * shouldn't affect rendering correctness, since the destination format is
321 * R32_FLOAT, so only the contents of the red channel matters.
323 if (devinfo
->gen
== 6 &&
324 src_mt
->surf
.samples
> 1 && dst_mt
->surf
.samples
<= 1 &&
325 src_mt
->format
== dst_mt
->format
&&
326 (dst_format
== MESA_FORMAT_L_FLOAT32
||
327 dst_format
== MESA_FORMAT_I_FLOAT32
)) {
328 src_format
= dst_format
= MESA_FORMAT_R_FLOAT32
;
331 enum blorp_filter blorp_filter
;
332 if (fabsf(dst_x1
- dst_x0
) == fabsf(src_x1
- src_x0
) &&
333 fabsf(dst_y1
- dst_y0
) == fabsf(src_y1
- src_y0
)) {
334 if (src_mt
->surf
.samples
> 1 && dst_mt
->surf
.samples
<= 1) {
335 /* From the OpenGL ES 3.2 specification, section 16.2.1:
337 * "If the read framebuffer is multisampled (its effective value
338 * of SAMPLE_BUFFERS is one) and the draw framebuffer is not (its
339 * value of SAMPLE_BUFFERS is zero), the samples corresponding to
340 * each pixel location in the source are converted to a single
341 * sample before being written to the destination. The filter
342 * parameter is ignored. If the source formats are integer types
343 * or stencil values, a single sample’s value is selected for each
344 * pixel. If the source formats are floating-point or normalized
345 * types, the sample values for each pixel are resolved in an
346 * implementation-dependent manner. If the source formats are
347 * depth values, sample values are resolved in an implementation-
348 * dependent manner where the result will be between the minimum
349 * and maximum depth values in the pixel."
351 * For depth and stencil resolves, we choose to always use the value
354 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
355 if (base_format
== GL_DEPTH_COMPONENT
||
356 base_format
== GL_STENCIL_INDEX
||
357 base_format
== GL_DEPTH_STENCIL
||
358 _mesa_is_format_integer(src_mt
->format
)) {
359 /* The OpenGL ES 3.2 spec says:
361 * "If the source formats are integer types or stencil values,
362 * a single sample's value is selected for each pixel."
364 * Just take sample 0 in this case.
366 blorp_filter
= BLORP_FILTER_SAMPLE_0
;
368 blorp_filter
= BLORP_FILTER_AVERAGE
;
371 /* From the OpenGL 4.6 specification, section 18.3.1:
373 * "If the source and destination dimensions are identical, no
374 * filtering is applied."
376 * Using BLORP_FILTER_NONE will also handle the upsample case by
377 * replicating the one value in the source to all values in the
380 blorp_filter
= BLORP_FILTER_NONE
;
382 } else if (gl_filter
== GL_LINEAR
||
383 gl_filter
== GL_SCALED_RESOLVE_FASTEST_EXT
||
384 gl_filter
== GL_SCALED_RESOLVE_NICEST_EXT
) {
385 blorp_filter
= BLORP_FILTER_BILINEAR
;
387 blorp_filter
= BLORP_FILTER_NEAREST
;
390 enum isl_format src_isl_format
=
391 brw_blorp_to_isl_format(brw
, src_format
, false);
392 enum isl_aux_usage src_aux_usage
=
393 intel_miptree_texture_aux_usage(brw
, src_mt
, src_isl_format
,
394 0 /* The astc5x5 WA isn't needed */);
395 /* We do format workarounds for some depth formats so we can't reliably
396 * sample with HiZ. One of these days, we should fix that.
398 if (src_aux_usage
== ISL_AUX_USAGE_HIZ
&& src_mt
->format
!= src_format
)
399 src_aux_usage
= ISL_AUX_USAGE_NONE
;
400 const bool src_clear_supported
=
401 src_aux_usage
!= ISL_AUX_USAGE_NONE
&& src_mt
->format
== src_format
;
402 intel_miptree_prepare_access(brw
, src_mt
, src_level
, 1, src_layer
, 1,
403 src_aux_usage
, src_clear_supported
);
405 enum isl_format dst_isl_format
=
406 brw_blorp_to_isl_format(brw
, dst_format
, true);
407 enum isl_aux_usage dst_aux_usage
=
408 intel_miptree_render_aux_usage(brw
, dst_mt
, dst_isl_format
,
410 const bool dst_clear_supported
= dst_aux_usage
!= ISL_AUX_USAGE_NONE
;
411 intel_miptree_prepare_access(brw
, dst_mt
, dst_level
, 1, dst_layer
, 1,
412 dst_aux_usage
, dst_clear_supported
);
414 struct blorp_surf src_surf
, dst_surf
;
415 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, src_aux_usage
, false,
416 &src_level
, src_layer
, 1);
417 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, dst_aux_usage
, true,
418 &dst_level
, dst_layer
, 1);
420 struct isl_swizzle src_isl_swizzle
= {
421 .r
= swizzle_to_scs(GET_SWZ(src_swizzle
, 0)),
422 .g
= swizzle_to_scs(GET_SWZ(src_swizzle
, 1)),
423 .b
= swizzle_to_scs(GET_SWZ(src_swizzle
, 2)),
424 .a
= swizzle_to_scs(GET_SWZ(src_swizzle
, 3)),
427 struct blorp_batch batch
;
428 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
429 blorp_blit(&batch
, &src_surf
, src_level
, src_layer
,
430 src_isl_format
, src_isl_swizzle
,
431 &dst_surf
, dst_level
, dst_layer
,
432 dst_isl_format
, ISL_SWIZZLE_IDENTITY
,
433 src_x0
, src_y0
, src_x1
, src_y1
,
434 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
435 blorp_filter
, mirror_x
, mirror_y
);
436 blorp_batch_finish(&batch
);
438 intel_miptree_finish_write(brw
, dst_mt
, dst_level
, dst_layer
, 1,
443 brw_blorp_copy_miptrees(struct brw_context
*brw
,
444 struct intel_mipmap_tree
*src_mt
,
445 unsigned src_level
, unsigned src_layer
,
446 struct intel_mipmap_tree
*dst_mt
,
447 unsigned dst_level
, unsigned dst_layer
,
448 unsigned src_x
, unsigned src_y
,
449 unsigned dst_x
, unsigned dst_y
,
450 unsigned src_width
, unsigned src_height
)
452 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
454 DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
455 "to %dx %s mt %p %d %d (%d,%d)\n",
457 src_mt
->surf
.samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
458 src_level
, src_layer
, src_x
, src_y
, src_width
, src_height
,
459 dst_mt
->surf
.samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
460 dst_level
, dst_layer
, dst_x
, dst_y
);
462 enum isl_aux_usage src_aux_usage
, dst_aux_usage
;
463 bool src_clear_supported
, dst_clear_supported
;
465 switch (src_mt
->aux_usage
) {
466 case ISL_AUX_USAGE_HIZ
:
467 if (intel_miptree_sample_with_hiz(brw
, src_mt
)) {
468 src_aux_usage
= src_mt
->aux_usage
;
469 src_clear_supported
= true;
471 src_aux_usage
= ISL_AUX_USAGE_NONE
;
472 src_clear_supported
= false;
475 case ISL_AUX_USAGE_MCS
:
476 case ISL_AUX_USAGE_CCS_E
:
477 src_aux_usage
= src_mt
->aux_usage
;
478 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
479 * we're going to re-interpret the format as an integer format possibly
480 * with a different number of components, we can't handle clear colors
483 src_clear_supported
= devinfo
->gen
>= 9;
486 src_aux_usage
= ISL_AUX_USAGE_NONE
;
487 src_clear_supported
= false;
491 switch (dst_mt
->aux_usage
) {
492 case ISL_AUX_USAGE_MCS
:
493 case ISL_AUX_USAGE_CCS_E
:
494 dst_aux_usage
= dst_mt
->aux_usage
;
495 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
496 * we're going to re-interpret the format as an integer format possibly
497 * with a different number of components, we can't handle clear colors
500 dst_clear_supported
= devinfo
->gen
>= 9;
503 dst_aux_usage
= ISL_AUX_USAGE_NONE
;
504 dst_clear_supported
= false;
508 intel_miptree_prepare_access(brw
, src_mt
, src_level
, 1, src_layer
, 1,
509 src_aux_usage
, src_clear_supported
);
510 intel_miptree_prepare_access(brw
, dst_mt
, dst_level
, 1, dst_layer
, 1,
511 dst_aux_usage
, dst_clear_supported
);
513 struct blorp_surf src_surf
, dst_surf
;
514 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, src_aux_usage
, false,
515 &src_level
, src_layer
, 1);
516 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, dst_aux_usage
, true,
517 &dst_level
, dst_layer
, 1);
519 /* The hardware seems to have issues with having a two different format
520 * views of the same texture in the sampler cache at the same time. It's
521 * unclear exactly what the issue is but it hurts glCopyImageSubData
522 * particularly badly because it does a lot of format reinterprets. We
523 * badly need better understanding of the issue and a better fix but this
524 * works for now and fixes CTS tests.
526 * TODO: Remove this hack!
528 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
|
529 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
531 struct blorp_batch batch
;
532 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
533 blorp_copy(&batch
, &src_surf
, src_level
, src_layer
,
534 &dst_surf
, dst_level
, dst_layer
,
535 src_x
, src_y
, dst_x
, dst_y
, src_width
, src_height
);
536 blorp_batch_finish(&batch
);
538 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
|
539 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
541 intel_miptree_finish_write(brw
, dst_mt
, dst_level
, dst_layer
, 1,
546 brw_blorp_copy_buffers(struct brw_context
*brw
,
547 struct brw_bo
*src_bo
,
549 struct brw_bo
*dst_bo
,
553 DBG("%s %d bytes from %p[%d] to %p[%d]",
554 __func__
, size
, src_bo
, src_offset
, dst_bo
, dst_offset
);
556 struct blorp_batch batch
;
557 struct blorp_address src
= { .buffer
= src_bo
, .offset
= src_offset
};
558 struct blorp_address dst
= { .buffer
= dst_bo
, .offset
= dst_offset
};
560 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
561 blorp_buffer_copy(&batch
, src
, dst
, size
);
562 blorp_batch_finish(&batch
);
566 static struct intel_mipmap_tree
*
567 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
569 struct intel_mipmap_tree
*mt
= irb
->mt
;
570 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
576 blorp_get_texture_swizzle(const struct intel_renderbuffer
*irb
)
578 return irb
->Base
.Base
._BaseFormat
== GL_RGB
?
579 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ONE
) :
584 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
585 struct intel_renderbuffer
*src_irb
, mesa_format src_format
,
586 struct intel_renderbuffer
*dst_irb
, mesa_format dst_format
,
587 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
588 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
589 GLenum filter
, bool mirror_x
, bool mirror_y
)
591 const struct gl_context
*ctx
= &brw
->ctx
;
593 /* Find source/dst miptrees */
594 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
595 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
597 const bool do_srgb
= ctx
->Color
.sRGBEnabled
;
600 brw_blorp_blit_miptrees(brw
,
601 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
602 src_format
, blorp_get_texture_swizzle(src_irb
),
603 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
605 srcX0
, srcY0
, srcX1
, srcY1
,
606 dstX0
, dstY0
, dstX1
, dstY1
,
607 filter
, mirror_x
, mirror_y
,
610 dst_irb
->need_downsample
= true;
614 try_blorp_blit(struct brw_context
*brw
,
615 const struct gl_framebuffer
*read_fb
,
616 const struct gl_framebuffer
*draw_fb
,
617 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
618 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
619 GLenum filter
, GLbitfield buffer_bit
)
621 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
622 struct gl_context
*ctx
= &brw
->ctx
;
624 /* Sync up the state of window system buffers. We need to do this before
625 * we go looking for the buffers.
627 intel_prepare_render(brw
);
629 bool mirror_x
, mirror_y
;
630 if (brw_meta_mirror_clip_and_scissor(ctx
, read_fb
, draw_fb
,
631 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
632 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
633 &mirror_x
, &mirror_y
))
637 struct intel_renderbuffer
*src_irb
;
638 struct intel_renderbuffer
*dst_irb
;
639 struct intel_mipmap_tree
*src_mt
;
640 struct intel_mipmap_tree
*dst_mt
;
641 switch (buffer_bit
) {
642 case GL_COLOR_BUFFER_BIT
:
643 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
644 for (unsigned i
= 0; i
< draw_fb
->_NumColorDrawBuffers
; ++i
) {
645 dst_irb
= intel_renderbuffer(draw_fb
->_ColorDrawBuffers
[i
]);
647 do_blorp_blit(brw
, buffer_bit
,
648 src_irb
, src_irb
->Base
.Base
.Format
,
649 dst_irb
, dst_irb
->Base
.Base
.Format
,
650 srcX0
, srcY0
, srcX1
, srcY1
,
651 dstX0
, dstY0
, dstX1
, dstY1
,
652 filter
, mirror_x
, mirror_y
);
655 case GL_DEPTH_BUFFER_BIT
:
657 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
659 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
660 src_mt
= find_miptree(buffer_bit
, src_irb
);
661 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
663 /* We also can't handle any combined depth-stencil formats because we
664 * have to reinterpret as a color format.
666 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
667 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
670 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
671 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
672 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
673 filter
, mirror_x
, mirror_y
);
675 case GL_STENCIL_BUFFER_BIT
:
676 /* Blorp doesn't support combined depth stencil which is all we have
679 if (devinfo
->gen
< 6)
683 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
685 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
686 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
687 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
688 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
689 filter
, mirror_x
, mirror_y
);
692 unreachable("not reached");
699 apply_y_flip(int *y0
, int *y1
, int height
)
701 int tmp
= height
- *y0
;
707 brw_blorp_copytexsubimage(struct brw_context
*brw
,
708 struct gl_renderbuffer
*src_rb
,
709 struct gl_texture_image
*dst_image
,
711 int srcX0
, int srcY0
,
712 int dstX0
, int dstY0
,
713 int width
, int height
)
715 struct gl_context
*ctx
= &brw
->ctx
;
716 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
717 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
719 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
720 if (brw
->ctx
._ImageTransferState
)
723 /* Sync up the state of window system buffers. We need to do this before
724 * we go looking at the src renderbuffer's miptree.
726 intel_prepare_render(brw
);
728 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
729 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
731 /* We can't handle any combined depth-stencil formats because we have to
732 * reinterpret as a color format.
734 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
735 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
738 if (!brw_blorp_supports_dst_format(brw
, dst_image
->TexFormat
))
741 /* Source clipping shouldn't be necessary, since copytexsubimage (in
742 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
745 * Destination clipping shouldn't be necessary since the restrictions on
746 * glCopyTexSubImage prevent the user from specifying a destination rectangle
747 * that falls outside the bounds of the destination texture.
748 * See error_check_subtexture_dimensions().
751 int srcY1
= srcY0
+ height
;
752 int srcX1
= srcX0
+ width
;
753 int dstX1
= dstX0
+ width
;
754 int dstY1
= dstY0
+ height
;
756 /* Account for the fact that in the system framebuffer, the origin is at
759 bool mirror_y
= ctx
->ReadBuffer
->FlipY
;
761 apply_y_flip(&srcY0
, &srcY1
, src_rb
->Height
);
763 /* Account for face selection and texture view MinLayer */
764 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
765 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
767 brw_blorp_blit_miptrees(brw
,
768 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
769 src_rb
->Format
, blorp_get_texture_swizzle(src_irb
),
770 dst_mt
, dst_level
, dst_slice
,
771 dst_image
->TexFormat
,
772 srcX0
, srcY0
, srcX1
, srcY1
,
773 dstX0
, dstY0
, dstX1
, dstY1
,
774 GL_NEAREST
, false, mirror_y
,
777 /* If we're copying to a packed depth stencil texture and the source
778 * framebuffer has separate stencil, we need to also copy the stencil data
781 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
782 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
784 src_irb
= intel_renderbuffer(src_rb
);
785 src_mt
= src_irb
->mt
;
787 if (src_mt
->stencil_mt
)
788 src_mt
= src_mt
->stencil_mt
;
789 if (dst_mt
->stencil_mt
)
790 dst_mt
= dst_mt
->stencil_mt
;
792 if (src_mt
!= dst_mt
) {
793 brw_blorp_blit_miptrees(brw
,
794 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
796 blorp_get_texture_swizzle(src_irb
),
797 dst_mt
, dst_level
, dst_slice
,
799 srcX0
, srcY0
, srcX1
, srcY1
,
800 dstX0
, dstY0
, dstX1
, dstY1
,
801 GL_NEAREST
, false, mirror_y
,
811 brw_blorp_framebuffer(struct brw_context
*brw
,
812 struct gl_framebuffer
*readFb
,
813 struct gl_framebuffer
*drawFb
,
814 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
815 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
816 GLbitfield mask
, GLenum filter
)
818 static GLbitfield buffer_bits
[] = {
821 GL_STENCIL_BUFFER_BIT
,
824 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
825 if ((mask
& buffer_bits
[i
]) &&
826 try_blorp_blit(brw
, readFb
, drawFb
,
827 srcX0
, srcY0
, srcX1
, srcY1
,
828 dstX0
, dstY0
, dstX1
, dstY1
,
829 filter
, buffer_bits
[i
])) {
830 mask
&= ~buffer_bits
[i
];
837 static struct brw_bo
*
838 blorp_get_client_bo(struct brw_context
*brw
,
839 unsigned w
, unsigned h
, unsigned d
,
840 GLenum target
, GLenum format
, GLenum type
,
842 const struct gl_pixelstore_attrib
*packing
,
843 uint32_t *offset_out
, uint32_t *row_stride_out
,
844 uint32_t *image_stride_out
, bool read_only
)
846 /* Account for SKIP_PIXELS, SKIP_ROWS, ALIGNMENT, and SKIP_IMAGES */
847 const GLuint dims
= _mesa_get_texture_dimensions(target
);
848 const uint32_t first_pixel
= _mesa_image_offset(dims
, packing
, w
, h
,
849 format
, type
, 0, 0, 0);
850 const uint32_t last_pixel
= _mesa_image_offset(dims
, packing
, w
, h
,
853 const uint32_t stride
= _mesa_image_row_stride(packing
, w
, format
, type
);
854 const uint32_t cpp
= _mesa_bytes_per_pixel(format
, type
);
855 const uint32_t size
= last_pixel
- first_pixel
;
857 *row_stride_out
= stride
;
858 *image_stride_out
= _mesa_image_image_stride(packing
, w
, h
, format
, type
);
860 if (_mesa_is_bufferobj(packing
->BufferObj
)) {
861 const uint32_t offset
= first_pixel
+ (intptr_t)pixels
;
862 if (!read_only
&& ((offset
% cpp
) || (stride
% cpp
))) {
863 perf_debug("Bad PBO alignment; fallback to CPU mapping\n");
867 /* This is a user-provided PBO. We just need to get the BO out */
868 struct intel_buffer_object
*intel_pbo
=
869 intel_buffer_object(packing
->BufferObj
);
871 intel_bufferobj_buffer(brw
, intel_pbo
, offset
, size
, !read_only
);
873 /* We take a reference to the BO so that the caller can just always
874 * unref without having to worry about whether it's a user PBO or one
877 brw_bo_reference(bo
);
879 *offset_out
= offset
;
882 /* Someone should have already checked that there is data to upload. */
885 /* Creating a temp buffer currently only works for upload */
888 /* This is not a user-provided PBO. Instead, pixels is a pointer to CPU
889 * data which we need to copy into a BO.
892 brw_bo_alloc(brw
->bufmgr
, "tmp_tex_subimage_src", size
,
895 perf_debug("intel_texsubimage: temp bo creation failed: size = %u\n",
900 if (brw_bo_subdata(bo
, 0, size
, pixels
+ first_pixel
)) {
901 perf_debug("intel_texsubimage: temp bo upload failed\n");
902 brw_bo_unreference(bo
);
911 /* Consider all the restrictions and determine the format of the source. */
913 blorp_get_client_format(struct brw_context
*brw
,
914 GLenum format
, GLenum type
,
915 const struct gl_pixelstore_attrib
*packing
)
917 if (brw
->ctx
._ImageTransferState
)
918 return MESA_FORMAT_NONE
;
920 if (packing
->SwapBytes
|| packing
->LsbFirst
|| packing
->Invert
) {
921 perf_debug("intel_texsubimage_blorp: unsupported gl_pixelstore_attrib\n");
922 return MESA_FORMAT_NONE
;
925 if (format
!= GL_RED
&&
931 format
!= GL_ALPHA
&&
932 format
!= GL_RED_INTEGER
&&
933 format
!= GL_RG_INTEGER
&&
934 format
!= GL_RGB_INTEGER
&&
935 format
!= GL_BGR_INTEGER
&&
936 format
!= GL_RGBA_INTEGER
&&
937 format
!= GL_BGRA_INTEGER
) {
938 perf_debug("intel_texsubimage_blorp: %s not supported",
939 _mesa_enum_to_string(format
));
940 return MESA_FORMAT_NONE
;
943 return _mesa_tex_format_from_format_and_type(&brw
->ctx
, format
, type
);
947 brw_blorp_upload_miptree(struct brw_context
*brw
,
948 struct intel_mipmap_tree
*dst_mt
,
949 mesa_format dst_format
,
950 uint32_t level
, uint32_t x
, uint32_t y
, uint32_t z
,
951 uint32_t width
, uint32_t height
, uint32_t depth
,
952 GLenum target
, GLenum format
, GLenum type
,
954 const struct gl_pixelstore_attrib
*packing
)
956 const mesa_format src_format
=
957 blorp_get_client_format(brw
, format
, type
, packing
);
958 if (src_format
== MESA_FORMAT_NONE
)
961 if (!brw
->mesa_format_supports_render
[dst_format
]) {
962 perf_debug("intel_texsubimage: can't use %s as render target\n",
963 _mesa_get_format_name(dst_format
));
967 uint32_t src_offset
, src_row_stride
, src_image_stride
;
968 struct brw_bo
*src_bo
=
969 blorp_get_client_bo(brw
, width
, height
, depth
,
970 target
, format
, type
, pixels
, packing
,
971 &src_offset
, &src_row_stride
,
972 &src_image_stride
, true);
976 /* Now that source is offset to correct starting point, adjust the
977 * given dimensions to treat 1D arrays as 2D.
979 if (target
== GL_TEXTURE_1D_ARRAY
) {
986 src_image_stride
= src_row_stride
;
989 intel_miptree_check_level_layer(dst_mt
, level
, z
+ depth
- 1);
993 /* Blit slice-by-slice creating a single-slice miptree for each layer. Even
994 * in case of linear buffers hardware wants image arrays to be aligned by
995 * four rows. This way hardware only gets one image at a time and any
996 * source alignment will do.
998 for (unsigned i
= 0; i
< depth
; ++i
) {
999 struct intel_mipmap_tree
*src_mt
= intel_miptree_create_for_bo(
1000 brw
, src_bo
, src_format
,
1001 src_offset
+ i
* src_image_stride
,
1004 ISL_TILING_LINEAR
, 0);
1007 perf_debug("intel_texsubimage: miptree creation for src failed\n");
1011 /* In case exact match is needed, copy using equivalent UINT formats
1012 * preventing hardware from changing presentation for SNORM -1.
1014 if (src_mt
->format
== dst_format
) {
1015 brw_blorp_copy_miptrees(brw
, src_mt
, 0, 0,
1016 dst_mt
, level
, z
+ i
,
1017 0, 0, x
, y
, width
, height
);
1019 brw_blorp_blit_miptrees(brw
, src_mt
, 0, 0,
1020 src_format
, SWIZZLE_XYZW
,
1021 dst_mt
, level
, z
+ i
,
1023 0, 0, width
, height
,
1024 x
, y
, x
+ width
, y
+ height
,
1025 GL_NEAREST
, false, false, false, false);
1028 intel_miptree_release(&src_mt
);
1034 brw_bo_unreference(src_bo
);
1040 brw_blorp_download_miptree(struct brw_context
*brw
,
1041 struct intel_mipmap_tree
*src_mt
,
1042 mesa_format src_format
, uint32_t src_swizzle
,
1043 uint32_t level
, uint32_t x
, uint32_t y
, uint32_t z
,
1044 uint32_t width
, uint32_t height
, uint32_t depth
,
1045 GLenum target
, GLenum format
, GLenum type
,
1046 bool y_flip
, const void *pixels
,
1047 const struct gl_pixelstore_attrib
*packing
)
1049 const mesa_format dst_format
=
1050 blorp_get_client_format(brw
, format
, type
, packing
);
1051 if (dst_format
== MESA_FORMAT_NONE
)
1054 if (!brw
->mesa_format_supports_render
[dst_format
]) {
1055 perf_debug("intel_texsubimage: can't use %s as render target\n",
1056 _mesa_get_format_name(dst_format
));
1060 /* We can't fetch from LUMINANCE or intensity as that would require a
1061 * non-trivial swizzle.
1063 switch (_mesa_get_format_base_format(src_format
)) {
1065 case GL_LUMINANCE_ALPHA
:
1072 /* This pass only works for PBOs */
1073 assert(_mesa_is_bufferobj(packing
->BufferObj
));
1075 uint32_t dst_offset
, dst_row_stride
, dst_image_stride
;
1076 struct brw_bo
*dst_bo
=
1077 blorp_get_client_bo(brw
, width
, height
, depth
,
1078 target
, format
, type
, pixels
, packing
,
1079 &dst_offset
, &dst_row_stride
,
1080 &dst_image_stride
, false);
1084 /* Now that source is offset to correct starting point, adjust the
1085 * given dimensions to treat 1D arrays as 2D.
1087 if (target
== GL_TEXTURE_1D_ARRAY
) {
1094 dst_image_stride
= dst_row_stride
;
1097 intel_miptree_check_level_layer(src_mt
, level
, z
+ depth
- 1);
1100 int y1
= y
+ height
;
1102 apply_y_flip(&y0
, &y1
, minify(src_mt
->surf
.phys_level0_sa
.height
,
1103 level
- src_mt
->first_level
));
1106 bool result
= false;
1108 /* Blit slice-by-slice creating a single-slice miptree for each layer. Even
1109 * in case of linear buffers hardware wants image arrays to be aligned by
1110 * four rows. This way hardware only gets one image at a time and any
1111 * source alignment will do.
1113 for (unsigned i
= 0; i
< depth
; ++i
) {
1114 struct intel_mipmap_tree
*dst_mt
= intel_miptree_create_for_bo(
1115 brw
, dst_bo
, dst_format
,
1116 dst_offset
+ i
* dst_image_stride
,
1119 ISL_TILING_LINEAR
, 0);
1122 perf_debug("intel_texsubimage: miptree creation for src failed\n");
1126 /* In case exact match is needed, copy using equivalent UINT formats
1127 * preventing hardware from changing presentation for SNORM -1.
1129 if (dst_mt
->format
== src_format
&& !y_flip
&&
1130 src_swizzle
== SWIZZLE_XYZW
) {
1131 brw_blorp_copy_miptrees(brw
, src_mt
, level
, z
+ i
,
1133 x
, y
, 0, 0, width
, height
);
1135 brw_blorp_blit_miptrees(brw
, src_mt
, level
, z
+ i
,
1136 src_format
, src_swizzle
,
1137 dst_mt
, 0, 0, dst_format
,
1138 x
, y0
, x
+ width
, y1
,
1139 0, 0, width
, height
,
1140 GL_NEAREST
, false, y_flip
, false, false);
1143 intel_miptree_release(&dst_mt
);
1148 /* As we implement PBO transfers by binding the user-provided BO as a
1149 * fake framebuffer and rendering to it. This breaks the invariant of the
1150 * GL that nothing is able to render to a BO, causing nondeterministic
1151 * corruption issues because the render cache is not coherent with a
1152 * number of other caches that the BO could potentially be bound to
1155 * This could be solved in the same way that we guarantee texture
1156 * coherency after a texture is attached to a framebuffer and
1157 * rendered to, but that would involve checking *all* BOs bound to
1158 * the pipeline for the case we need to emit a cache flush due to
1159 * previous rendering to any of them -- Including vertex, index,
1160 * uniform, atomic counter, shader image, transform feedback,
1161 * indirect draw buffers, etc.
1163 * That would increase the per-draw call overhead even though it's
1164 * very unlikely that any of the BOs bound to the pipeline has been
1165 * rendered to via a PBO at any point, so it seems better to just
1166 * flush here unconditionally.
1168 brw_emit_mi_flush(brw
);
1171 brw_bo_unreference(dst_bo
);
1177 set_write_disables(const struct intel_renderbuffer
*irb
,
1178 const unsigned color_mask
, bool *color_write_disable
)
1180 /* Format information in the renderbuffer represents the requirements
1181 * given by the client. There are cases where the backing miptree uses,
1182 * for example, RGBA to represent RGBX. Since the client is only expecting
1183 * RGB we can treat alpha as not used and write whatever we like into it.
1185 const GLenum base_format
= irb
->Base
.Base
._BaseFormat
;
1186 const int components
= _mesa_components_in_format(base_format
);
1187 bool disables
= false;
1189 assert(components
> 0);
1191 for (int i
= 0; i
< components
; i
++) {
1192 color_write_disable
[i
] = !(color_mask
& (1 << i
));
1193 disables
= disables
|| color_write_disable
[i
];
1200 do_single_blorp_clear(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
1201 struct gl_renderbuffer
*rb
, unsigned buf
,
1202 bool partial_clear
, bool encode_srgb
)
1204 struct gl_context
*ctx
= &brw
->ctx
;
1205 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
1206 uint32_t x0
, x1
, y0
, y1
;
1208 mesa_format format
= irb
->Base
.Base
.Format
;
1210 format
= _mesa_get_srgb_format_linear(format
);
1211 enum isl_format isl_format
= brw
->mesa_to_isl_render_format
[format
];
1216 y0
= rb
->Height
- fb
->_Ymax
;
1217 y1
= rb
->Height
- fb
->_Ymin
;
1223 /* If the clear region is empty, just return. */
1224 if (x0
== x1
|| y0
== y1
)
1227 bool can_fast_clear
= !partial_clear
;
1229 if (INTEL_DEBUG
& DEBUG_NO_FAST_CLEAR
)
1230 can_fast_clear
= false;
1232 bool color_write_disable
[4] = { false, false, false, false };
1233 if (set_write_disables(irb
, GET_COLORMASK(ctx
->Color
.ColorMask
, buf
),
1234 color_write_disable
))
1235 can_fast_clear
= false;
1237 /* We store clear colors as floats or uints as needed. If there are
1238 * texture views in play, the formats will not properly be respected
1239 * during resolves because the resolve operations only know about the
1240 * miptree and not the renderbuffer.
1242 if (irb
->Base
.Base
.Format
!= irb
->mt
->format
)
1243 can_fast_clear
= false;
1245 if (!irb
->mt
->supports_fast_clear
||
1246 !brw_is_color_fast_clear_compatible(brw
, irb
->mt
, &ctx
->Color
.ClearColor
))
1247 can_fast_clear
= false;
1249 /* Surface state can only record one fast clear color value. Therefore
1250 * unless different levels/layers agree on the color it can be used to
1251 * represent only single level/layer. Here it will be reserved for the
1252 * first slice (level 0, layer 0).
1254 if (irb
->layer_count
> 1 || irb
->mt_level
|| irb
->mt_layer
)
1255 can_fast_clear
= false;
1257 unsigned level
= irb
->mt_level
;
1258 const unsigned num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1260 /* If the MCS buffer hasn't been allocated yet, we need to allocate it now.
1262 if (can_fast_clear
&& !irb
->mt
->aux_buf
) {
1263 assert(irb
->mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1264 if (!intel_miptree_alloc_aux(brw
, irb
->mt
)) {
1265 /* We're out of memory. Fall back to a non-fast clear. */
1266 can_fast_clear
= false;
1270 if (can_fast_clear
) {
1271 const enum isl_aux_state aux_state
=
1272 intel_miptree_get_aux_state(irb
->mt
, irb
->mt_level
, irb
->mt_layer
);
1273 union isl_color_value clear_color
=
1274 brw_meta_convert_fast_clear_color(brw
, irb
->mt
,
1275 &ctx
->Color
.ClearColor
);
1277 /* If the buffer is already in ISL_AUX_STATE_CLEAR and the clear color
1278 * hasn't changed, the clear is redundant and can be skipped.
1280 if (!intel_miptree_set_clear_color(brw
, irb
->mt
, clear_color
) &&
1281 aux_state
== ISL_AUX_STATE_CLEAR
) {
1285 DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__
,
1286 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
1288 /* We can't setup the blorp_surf until we've allocated the MCS above */
1289 struct blorp_surf surf
;
1290 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, irb
->mt
->aux_usage
, true,
1291 &level
, irb
->mt_layer
, num_layers
);
1293 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1295 * "Any transition from any value in {Clear, Render, Resolve} to a
1296 * different value in {Clear, Render, Resolve} requires end of pipe
1299 * In other words, fast clear ops are not properly synchronized with
1300 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1301 * contents of the previous draw hit the render target before we resolve
1302 * and again afterwards to ensure that the resolve is complete before we
1303 * do any more regular drawing.
1305 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1307 struct blorp_batch batch
;
1308 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1309 blorp_fast_clear(&batch
, &surf
, isl_format_srgb_to_linear(isl_format
),
1310 level
, irb
->mt_layer
, num_layers
, x0
, y0
, x1
, y1
);
1311 blorp_batch_finish(&batch
);
1313 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1315 /* Now that the fast clear has occurred, put the buffer in
1316 * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
1319 intel_miptree_set_aux_state(brw
, irb
->mt
, irb
->mt_level
,
1320 irb
->mt_layer
, num_layers
,
1321 ISL_AUX_STATE_CLEAR
);
1323 DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__
,
1324 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
1326 enum isl_aux_usage aux_usage
=
1327 intel_miptree_render_aux_usage(brw
, irb
->mt
, isl_format
,
1329 intel_miptree_prepare_render(brw
, irb
->mt
, level
, irb
->mt_layer
,
1330 num_layers
, aux_usage
);
1332 struct blorp_surf surf
;
1333 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, aux_usage
, true,
1334 &level
, irb
->mt_layer
, num_layers
);
1336 union isl_color_value clear_color
;
1337 memcpy(clear_color
.f32
, ctx
->Color
.ClearColor
.f
, sizeof(float) * 4);
1339 struct blorp_batch batch
;
1340 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1341 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
1342 level
, irb
->mt_layer
, num_layers
,
1344 clear_color
, color_write_disable
);
1345 blorp_batch_finish(&batch
);
1347 intel_miptree_finish_render(brw
, irb
->mt
, level
, irb
->mt_layer
,
1348 num_layers
, aux_usage
);
1355 brw_blorp_clear_color(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
1356 GLbitfield mask
, bool partial_clear
, bool encode_srgb
)
1358 for (unsigned buf
= 0; buf
< fb
->_NumColorDrawBuffers
; buf
++) {
1359 struct gl_renderbuffer
*rb
= fb
->_ColorDrawBuffers
[buf
];
1360 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
1362 /* Only clear the buffers present in the provided mask */
1363 if (((1 << fb
->_ColorDrawBufferIndexes
[buf
]) & mask
) == 0)
1366 /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
1367 * the framebuffer can be complete with some attachments missing. In
1368 * this case the _ColorDrawBuffers pointer will be NULL.
1373 do_single_blorp_clear(brw
, fb
, rb
, buf
, partial_clear
, encode_srgb
);
1374 irb
->need_downsample
= true;
1381 brw_blorp_clear_depth_stencil(struct brw_context
*brw
,
1382 struct gl_framebuffer
*fb
,
1383 GLbitfield mask
, bool partial_clear
)
1385 const struct gl_context
*ctx
= &brw
->ctx
;
1386 struct gl_renderbuffer
*depth_rb
=
1387 fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
;
1388 struct gl_renderbuffer
*stencil_rb
=
1389 fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
1391 if (!depth_rb
|| ctx
->Depth
.Mask
== GL_FALSE
)
1392 mask
&= ~BUFFER_BIT_DEPTH
;
1394 if (!stencil_rb
|| (ctx
->Stencil
.WriteMask
[0] & 0xff) == 0)
1395 mask
&= ~BUFFER_BIT_STENCIL
;
1397 if (!(mask
& (BUFFER_BITS_DEPTH_STENCIL
)))
1400 uint32_t x0
, x1
, y0
, y1
, rb_height
;
1402 rb_height
= depth_rb
->Height
;
1404 assert(depth_rb
->Width
== stencil_rb
->Width
);
1405 assert(depth_rb
->Height
== stencil_rb
->Height
);
1409 rb_height
= stencil_rb
->Height
;
1415 y0
= rb_height
- fb
->_Ymax
;
1416 y1
= rb_height
- fb
->_Ymin
;
1422 /* If the clear region is empty, just return. */
1423 if (x0
== x1
|| y0
== y1
)
1426 uint32_t level
= 0, start_layer
= 0, num_layers
;
1427 struct blorp_surf depth_surf
, stencil_surf
;
1429 struct intel_mipmap_tree
*depth_mt
= NULL
;
1430 if (mask
& BUFFER_BIT_DEPTH
) {
1431 struct intel_renderbuffer
*irb
= intel_renderbuffer(depth_rb
);
1432 depth_mt
= find_miptree(GL_DEPTH_BUFFER_BIT
, irb
);
1434 level
= irb
->mt_level
;
1435 start_layer
= irb
->mt_layer
;
1436 num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1438 intel_miptree_prepare_depth(brw
, depth_mt
, level
,
1439 start_layer
, num_layers
);
1441 unsigned depth_level
= level
;
1442 blorp_surf_for_miptree(brw
, &depth_surf
, depth_mt
, depth_mt
->aux_usage
,
1443 true, &depth_level
, start_layer
, num_layers
);
1444 assert(depth_level
== level
);
1447 uint8_t stencil_mask
= 0;
1448 struct intel_mipmap_tree
*stencil_mt
= NULL
;
1449 if (mask
& BUFFER_BIT_STENCIL
) {
1450 struct intel_renderbuffer
*irb
= intel_renderbuffer(stencil_rb
);
1451 stencil_mt
= find_miptree(GL_STENCIL_BUFFER_BIT
, irb
);
1453 if (mask
& BUFFER_BIT_DEPTH
) {
1454 assert(level
== irb
->mt_level
);
1455 assert(start_layer
== irb
->mt_layer
);
1456 assert(num_layers
== fb
->MaxNumLayers
? irb
->layer_count
: 1);
1459 level
= irb
->mt_level
;
1460 start_layer
= irb
->mt_layer
;
1461 num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1463 stencil_mask
= ctx
->Stencil
.WriteMask
[0] & 0xff;
1465 intel_miptree_prepare_access(brw
, stencil_mt
, level
, 1,
1466 start_layer
, num_layers
,
1467 ISL_AUX_USAGE_NONE
, false);
1469 unsigned stencil_level
= level
;
1470 blorp_surf_for_miptree(brw
, &stencil_surf
, stencil_mt
,
1471 ISL_AUX_USAGE_NONE
, true,
1472 &stencil_level
, start_layer
, num_layers
);
1475 assert((mask
& BUFFER_BIT_DEPTH
) || stencil_mask
);
1477 struct blorp_batch batch
;
1478 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1479 blorp_clear_depth_stencil(&batch
, &depth_surf
, &stencil_surf
,
1480 level
, start_layer
, num_layers
,
1482 (mask
& BUFFER_BIT_DEPTH
), ctx
->Depth
.Clear
,
1483 stencil_mask
, ctx
->Stencil
.Clear
);
1484 blorp_batch_finish(&batch
);
1486 if (mask
& BUFFER_BIT_DEPTH
) {
1487 intel_miptree_finish_depth(brw
, depth_mt
, level
,
1488 start_layer
, num_layers
, true);
1492 intel_miptree_finish_write(brw
, stencil_mt
, level
,
1493 start_layer
, num_layers
,
1494 ISL_AUX_USAGE_NONE
);
1499 brw_blorp_resolve_color(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1500 unsigned level
, unsigned layer
,
1501 enum isl_aux_op resolve_op
)
1503 DBG("%s to mt %p level %u layer %u\n", __FUNCTION__
, mt
, level
, layer
);
1505 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
1507 struct blorp_surf surf
;
1508 blorp_surf_for_miptree(brw
, &surf
, mt
, mt
->aux_usage
, true,
1509 &level
, layer
, 1 /* num_layers */);
1511 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1513 * "Any transition from any value in {Clear, Render, Resolve} to a
1514 * different value in {Clear, Render, Resolve} requires end of pipe
1517 * In other words, fast clear ops are not properly synchronized with
1518 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1519 * contents of the previous draw hit the render target before we resolve
1520 * and again afterwards to ensure that the resolve is complete before we
1521 * do any more regular drawing.
1523 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1526 struct blorp_batch batch
;
1527 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1528 blorp_ccs_resolve(&batch
, &surf
, level
, layer
, 1,
1529 brw_blorp_to_isl_format(brw
, format
, true),
1531 blorp_batch_finish(&batch
);
1533 /* See comment above */
1534 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1538 brw_blorp_mcs_partial_resolve(struct brw_context
*brw
,
1539 struct intel_mipmap_tree
*mt
,
1540 uint32_t start_layer
, uint32_t num_layers
)
1542 DBG("%s to mt %p layers %u-%u\n", __FUNCTION__
, mt
,
1543 start_layer
, start_layer
+ num_layers
- 1);
1545 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1547 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
1548 enum isl_format isl_format
= brw_blorp_to_isl_format(brw
, format
, true);
1550 struct blorp_surf surf
;
1552 blorp_surf_for_miptree(brw
, &surf
, mt
, ISL_AUX_USAGE_MCS
, true,
1553 &level
, start_layer
, num_layers
);
1555 struct blorp_batch batch
;
1556 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1557 blorp_mcs_partial_resolve(&batch
, &surf
, isl_format
,
1558 start_layer
, num_layers
);
1559 blorp_batch_finish(&batch
);
1563 * Perform a HiZ or depth resolve operation.
1565 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
1566 * PRM, Volume 1, Part 2:
1567 * - 7.5.3.1 Depth Buffer Clear
1568 * - 7.5.3.2 Depth Buffer Resolve
1569 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1572 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1573 unsigned int level
, unsigned int start_layer
,
1574 unsigned int num_layers
, enum isl_aux_op op
)
1576 assert(intel_miptree_level_has_hiz(mt
, level
));
1577 assert(op
!= ISL_AUX_OP_NONE
);
1578 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1579 const char *opname
= NULL
;
1582 case ISL_AUX_OP_FULL_RESOLVE
:
1583 opname
= "depth resolve";
1585 case ISL_AUX_OP_AMBIGUATE
:
1586 opname
= "hiz ambiguate";
1588 case ISL_AUX_OP_FAST_CLEAR
:
1589 opname
= "depth clear";
1591 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1592 case ISL_AUX_OP_NONE
:
1593 unreachable("Invalid HiZ op");
1596 DBG("%s %s to mt %p level %d layers %d-%d\n",
1597 __func__
, opname
, mt
, level
, start_layer
, start_layer
+ num_layers
- 1);
1599 /* The following stalls and flushes are only documented to be required for
1600 * HiZ clear operations. However, they also seem to be required for
1601 * resolve operations.
1603 if (devinfo
->gen
== 6) {
1604 /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
1606 * "If other rendering operations have preceded this clear, a
1607 * PIPE_CONTROL with write cache flush enabled and Z-inhibit
1608 * disabled must be issued before the rectangle primitive used for
1609 * the depth buffer clear operation.
1611 brw_emit_pipe_control_flush(brw
,
1612 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1613 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1614 PIPE_CONTROL_CS_STALL
);
1615 } else if (devinfo
->gen
>= 7) {
1617 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
1619 * If other rendering operations have preceded this clear, a
1620 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
1621 * enabled must be issued before the rectangle primitive used for
1622 * the depth buffer clear operation.
1624 * Same applies for Gen8 and Gen9.
1626 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
1627 * PIPE_CONTROL, Depth Cache Flush Enable:
1629 * This bit must not be set when Depth Stall Enable bit is set in
1632 * This is confirmed to hold for real, HSW gets immediate gpu hangs.
1634 * Therefore issue two pipe control flushes, one for cache flush and
1635 * another for depth stall.
1637 brw_emit_pipe_control_flush(brw
,
1638 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1639 PIPE_CONTROL_CS_STALL
);
1641 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
1644 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
&& mt
->aux_buf
);
1646 struct blorp_surf surf
;
1647 blorp_surf_for_miptree(brw
, &surf
, mt
, ISL_AUX_USAGE_HIZ
, true,
1648 &level
, start_layer
, num_layers
);
1650 struct blorp_batch batch
;
1651 blorp_batch_init(&brw
->blorp
, &batch
, brw
,
1652 BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
);
1653 blorp_hiz_op(&batch
, &surf
, level
, start_layer
, num_layers
, op
);
1654 blorp_batch_finish(&batch
);
1656 /* The following stalls and flushes are only documented to be required for
1657 * HiZ clear operations. However, they also seem to be required for
1658 * resolve operations.
1660 if (devinfo
->gen
== 6) {
1661 /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
1663 * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be
1664 * followed by a PIPE_CONTROL command with DEPTH_STALL bit set
1665 * and Then followed by Depth FLUSH'
1667 brw_emit_pipe_control_flush(brw
,
1668 PIPE_CONTROL_DEPTH_STALL
);
1670 brw_emit_pipe_control_flush(brw
,
1671 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1672 PIPE_CONTROL_CS_STALL
);
1673 } else if (devinfo
->gen
>= 8) {
1675 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
1677 * "Depth buffer clear pass using any of the methods (WM_STATE,
1678 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
1679 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
1680 * "set" before starting to render. DepthStall and DepthFlush are
1681 * not needed between consecutive depth clear passes nor is it
1682 * required if the depth clear pass was done with
1683 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
1685 * TODO: Such as the spec says, this could be conditional.
1687 brw_emit_pipe_control_flush(brw
,
1688 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1689 PIPE_CONTROL_DEPTH_STALL
);