src/mesa/drivers/dri/i965/brw_blorp.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/context.h"
  25 #include "main/teximage.h"
  26 #include "main/blend.h"
  27 #include "main/fbobject.h"
  28 #include "main/renderbuffer.h"
  29 #include "main/glformats.h"
  30
  31 #include "brw_blorp.h"
  32 #include "brw_context.h"
  33 #include "brw_defines.h"
  34 #include "brw_meta_util.h"
  35 #include "brw_state.h"
  36 #include "intel_fbo.h"
  37 #include "intel_debug.h"
  38
  39 #define FILE_DEBUG_FLAG DEBUG_BLORP
  40
  41 static bool
  42 brw_blorp_lookup_shader(struct blorp_context *blorp,
  43                         const void *key, uint32_t key_size,
  44                         uint32_t *kernel_out, void *prog_data_out)
  45 {
  46    struct brw_context *brw = blorp->driver_ctx;
  47    return brw_search_cache(&brw->cache, BRW_CACHE_BLORP_PROG,
  48                            key, key_size, kernel_out, prog_data_out);
  49 }
  50
  51 static void
  52 brw_blorp_upload_shader(struct blorp_context *blorp,
  53                         const void *key, uint32_t key_size,
  54                         const void *kernel, uint32_t kernel_size,
  55                         const void *prog_data, uint32_t prog_data_size,
  56                         uint32_t *kernel_out, void *prog_data_out)
  57 {
  58    struct brw_context *brw = blorp->driver_ctx;
  59    brw_upload_cache(&brw->cache, BRW_CACHE_BLORP_PROG, key, key_size,
  60                     kernel, kernel_size, prog_data, prog_data_size,
  61                     kernel_out, prog_data_out);
  62 }
  63
  64 void
  65 brw_blorp_init(struct brw_context *brw)
  66 {
  67    blorp_init(&brw->blorp, brw, &brw->isl_dev);
  68
  69    brw->blorp.compiler = brw->intelScreen->compiler;
  70
  71    switch (brw->gen) {
  72    case 6:
  73       brw->blorp.mocs.tex = 0;
  74       brw->blorp.mocs.rb = 0;
  75       brw->blorp.mocs.vb = 0;
  76       brw->blorp.exec = gen6_blorp_exec;
  77       break;
  78    case 7:
  79       brw->blorp.mocs.tex = GEN7_MOCS_L3;
  80       brw->blorp.mocs.rb = GEN7_MOCS_L3;
  81       brw->blorp.mocs.vb = GEN7_MOCS_L3;
  82       if (brw->is_haswell) {
  83          brw->blorp.exec = gen75_blorp_exec;
  84       } else {
  85          brw->blorp.exec = gen7_blorp_exec;
  86       }
  87       break;
  88    case 8:
  89       brw->blorp.mocs.tex = BDW_MOCS_WB;
  90       brw->blorp.mocs.rb = BDW_MOCS_PTE;
  91       brw->blorp.mocs.vb = BDW_MOCS_WB;
  92       brw->blorp.exec = gen8_blorp_exec;
  93       break;
  94    case 9:
  95       brw->blorp.mocs.tex = SKL_MOCS_WB;
  96       brw->blorp.mocs.rb = SKL_MOCS_PTE;
  97       brw->blorp.mocs.vb = SKL_MOCS_WB;
  98       brw->blorp.exec = gen9_blorp_exec;
  99       break;
 100    default:
 101       unreachable("Invalid gen");
 102    }
 103
 104    brw->blorp.lookup_shader = brw_blorp_lookup_shader;
 105    brw->blorp.upload_shader = brw_blorp_upload_shader;
 106 }
 107
 108 static void
 109 apply_gen6_stencil_hiz_offset(struct isl_surf *surf,
 110                               struct intel_mipmap_tree *mt,
 111                               uint32_t lod,
 112                               uint32_t *offset)
 113 {
 114    assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD);
 115
 116    if (mt->format == MESA_FORMAT_S_UINT8) {
 117       /* Note: we can't compute the stencil offset using
 118        * intel_miptree_get_aligned_offset(), because the miptree
 119        * claims that the region is untiled even though it's W tiled.
 120        */
 121       *offset = mt->level[lod].level_y * mt->pitch +
 122                 mt->level[lod].level_x * 64;
 123    } else {
 124       *offset = intel_miptree_get_aligned_offset(mt,
 125                                                  mt->level[lod].level_x,
 126                                                  mt->level[lod].level_y,
 127                                                  false);
 128    }
 129
 130    surf->logical_level0_px.width = minify(surf->logical_level0_px.width, lod);
 131    surf->logical_level0_px.height = minify(surf->logical_level0_px.height, lod);
 132    surf->phys_level0_sa.width = minify(surf->phys_level0_sa.width, lod);
 133    surf->phys_level0_sa.height = minify(surf->phys_level0_sa.height, lod);
 134    surf->levels = 1;
 135    surf->array_pitch_el_rows =
 136       ALIGN(surf->phys_level0_sa.height, surf->image_alignment_el.height);
 137 }
 138
 139 static void
 140 blorp_surf_for_miptree(struct brw_context *brw,
 141                        struct blorp_surf *surf,
 142                        struct intel_mipmap_tree *mt,
 143                        bool is_render_target,
 144                        unsigned *level,
 145                        struct isl_surf tmp_surfs[2])
 146 {
 147    intel_miptree_get_isl_surf(brw, mt, &tmp_surfs[0]);
 148    surf->surf = &tmp_surfs[0];
 149    surf->addr = (struct blorp_address) {
 150       .buffer = mt->bo,
 151       .offset = mt->offset,
 152       .read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
 153                                          I915_GEM_DOMAIN_SAMPLER,
 154       .write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
 155    };
 156
 157    if (brw->gen == 6 && mt->format == MESA_FORMAT_S_UINT8 &&
 158        mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
 159       /* Sandy bridge stencil and HiZ use this ALL_SLICES_AT_EACH_LOD hack in
 160        * order to allow for layered rendering.  The hack makes each LOD of the
 161        * stencil or HiZ buffer a single tightly packed array surface at some
 162        * offset into the surface.  Since ISL doesn't know how to deal with the
 163        * crazy ALL_SLICES_AT_EACH_LOD layout and since we have to do a manual
 164        * offset of it anyway, we might as well do the offset here and keep the
 165        * hacks inside the i965 driver.
 166        *
 167        * See also gen6_depth_stencil_state.c
 168        */
 169       uint32_t offset;
 170       apply_gen6_stencil_hiz_offset(&tmp_surfs[0], mt, *level, &offset);
 171       surf->addr.offset += offset;
 172       *level = 0;
 173    }
 174
 175    struct isl_surf *aux_surf = &tmp_surfs[1];
 176    intel_miptree_get_aux_isl_surf(brw, mt, aux_surf, &surf->aux_usage);
 177
 178    /* For textures that are in the RESOLVED state, we ignore the MCS */
 179    if (mt->mcs_mt && !is_render_target &&
 180        mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED)
 181       surf->aux_usage = ISL_AUX_USAGE_NONE;
 182
 183    if (surf->aux_usage != ISL_AUX_USAGE_NONE) {
 184       /* We only really need a clear color if we also have an auxiliary
 185        * surface.  Without one, it does nothing.
 186        */
 187       surf->clear_color = intel_miptree_get_isl_clear_color(brw, mt);
 188
 189       surf->aux_surf = aux_surf;
 190       surf->aux_addr = (struct blorp_address) {
 191          .read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
 192                                             I915_GEM_DOMAIN_SAMPLER,
 193          .write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
 194       };
 195
 196       if (mt->mcs_mt) {
 197          surf->aux_addr.buffer = mt->mcs_mt->bo;
 198          surf->aux_addr.offset = mt->mcs_mt->offset;
 199       } else {
 200          assert(surf->aux_usage == ISL_AUX_USAGE_HIZ);
 201          struct intel_mipmap_tree *hiz_mt = mt->hiz_buf->mt;
 202          if (hiz_mt) {
 203             surf->aux_addr.buffer = hiz_mt->bo;
 204             if (brw->gen == 6 &&
 205                 hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
 206                /* gen6 requires the HiZ buffer to be manually offset to the
 207                 * right location.  We could fixup the surf but it doesn't
 208                 * matter since most of those fields don't matter.
 209                 */
 210                apply_gen6_stencil_hiz_offset(aux_surf, hiz_mt, *level,
 211                                              &surf->aux_addr.offset);
 212             } else {
 213                surf->aux_addr.offset = 0;
 214             }
 215             assert(hiz_mt->pitch == aux_surf->row_pitch);
 216          } else {
 217             surf->aux_addr.buffer = mt->hiz_buf->bo;
 218             surf->aux_addr.offset = 0;
 219          }
 220       }
 221    } else {
 222       surf->aux_addr = (struct blorp_address) {
 223          .buffer = NULL,
 224       };
 225       memset(&surf->clear_color, 0, sizeof(surf->clear_color));
 226    }
 227    assert((surf->aux_usage == ISL_AUX_USAGE_NONE) ==
 228           (surf->aux_addr.buffer == NULL));
 229 }
 230
 231 static enum isl_format
 232 brw_blorp_to_isl_format(struct brw_context *brw, mesa_format format,
 233                         bool is_render_target)
 234 {
 235    switch (format) {
 236    case MESA_FORMAT_NONE:
 237       return ISL_FORMAT_UNSUPPORTED;
 238    case MESA_FORMAT_S_UINT8:
 239       return ISL_FORMAT_R8_UINT;
 240    case MESA_FORMAT_Z24_UNORM_X8_UINT:
 241       return ISL_FORMAT_R24_UNORM_X8_TYPELESS;
 242    case MESA_FORMAT_Z_FLOAT32:
 243       return ISL_FORMAT_R32_FLOAT;
 244    case MESA_FORMAT_Z_UNORM16:
 245       return ISL_FORMAT_R16_UNORM;
 246    default: {
 247       if (is_render_target) {
 248          assert(brw->format_supported_as_render_target[format]);
 249          return brw->render_target_format[format];
 250       } else {
 251          return brw_format_for_mesa_format(format);
 252       }
 253       break;
 254    }
 255    }
 256 }
 257
 258 /**
 259  * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
 260  * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED).  The mappings are
 261  *
 262  * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
 263  *         0          1          2          3             4            5
 264  *         4          5          6          7             0            1
 265  *   SCS_RED, SCS_GREEN,  SCS_BLUE, SCS_ALPHA,     SCS_ZERO,     SCS_ONE
 266  *
 267  * which is simply adding 4 then modding by 8 (or anding with 7).
 268  *
 269  * We then may need to apply workarounds for textureGather hardware bugs.
 270  */
 271 static enum isl_channel_select
 272 swizzle_to_scs(GLenum swizzle)
 273 {
 274    return (enum isl_channel_select)((swizzle + 4) & 7);
 275 }
 276
 277 /**
 278  * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
 279  * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
 280  * the physical layer holding sample 0.  So, for example, if
 281  * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
 282  * 4*n.
 283  */
 284 void
 285 brw_blorp_blit_miptrees(struct brw_context *brw,
 286                         struct intel_mipmap_tree *src_mt,
 287                         unsigned src_level, unsigned src_layer,
 288                         mesa_format src_format, int src_swizzle,
 289                         struct intel_mipmap_tree *dst_mt,
 290                         unsigned dst_level, unsigned dst_layer,
 291                         mesa_format dst_format,
 292                         float src_x0, float src_y0,
 293                         float src_x1, float src_y1,
 294                         float dst_x0, float dst_y0,
 295                         float dst_x1, float dst_y1,
 296                         GLenum filter, bool mirror_x, bool mirror_y,
 297                         bool decode_srgb, bool encode_srgb)
 298 {
 299    /* Get ready to blit.  This includes depth resolving the src and dst
 300     * buffers if necessary.  Note: it's not necessary to do a color resolve on
 301     * the destination buffer because we use the standard render path to render
 302     * to destination color buffers, and the standard render path is
 303     * fast-color-aware.
 304     */
 305    intel_miptree_resolve_color(brw, src_mt, INTEL_MIPTREE_IGNORE_CCS_E);
 306    intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_layer);
 307    intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_layer);
 308
 309    DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
 310        "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
 311        __func__,
 312        src_mt->num_samples, _mesa_get_format_name(src_mt->format), src_mt,
 313        src_level, src_layer, src_x0, src_y0, src_x1, src_y1,
 314        dst_mt->num_samples, _mesa_get_format_name(dst_mt->format), dst_mt,
 315        dst_level, dst_layer, dst_x0, dst_y0, dst_x1, dst_y1,
 316        mirror_x, mirror_y);
 317
 318    if (!decode_srgb && _mesa_get_format_color_encoding(src_format) == GL_SRGB)
 319       src_format = _mesa_get_srgb_format_linear(src_format);
 320
 321    if (!encode_srgb && _mesa_get_format_color_encoding(dst_format) == GL_SRGB)
 322       dst_format = _mesa_get_srgb_format_linear(dst_format);
 323
 324    /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
 325     * texture, the above code configures the source format for L32_FLOAT or
 326     * I32_FLOAT, and the destination format for R32_FLOAT.  On Sandy Bridge,
 327     * the SAMPLE message appears to handle multisampled L32_FLOAT and
 328     * I32_FLOAT textures incorrectly, resulting in blocky artifacts.  So work
 329     * around the problem by using a source format of R32_FLOAT.  This
 330     * shouldn't affect rendering correctness, since the destination format is
 331     * R32_FLOAT, so only the contents of the red channel matters.
 332     */
 333    if (brw->gen == 6 &&
 334        src_mt->num_samples > 1 && dst_mt->num_samples <= 1 &&
 335        src_mt->format == dst_mt->format &&
 336        (dst_format == MESA_FORMAT_L_FLOAT32 ||
 337         dst_format == MESA_FORMAT_I_FLOAT32)) {
 338       src_format = dst_format = MESA_FORMAT_R_FLOAT32;
 339    }
 340
 341    intel_miptree_check_level_layer(src_mt, src_level, src_layer);
 342    intel_miptree_check_level_layer(dst_mt, dst_level, dst_layer);
 343    intel_miptree_used_for_rendering(dst_mt);
 344
 345    struct isl_surf tmp_surfs[4];
 346    struct blorp_surf src_surf, dst_surf;
 347    blorp_surf_for_miptree(brw, &src_surf, src_mt, false,
 348                           &src_level, &tmp_surfs[0]);
 349    blorp_surf_for_miptree(brw, &dst_surf, dst_mt, true,
 350                           &dst_level, &tmp_surfs[2]);
 351
 352    struct isl_swizzle src_isl_swizzle = {
 353       .r = swizzle_to_scs(GET_SWZ(src_swizzle, 0)),
 354       .g = swizzle_to_scs(GET_SWZ(src_swizzle, 1)),
 355       .b = swizzle_to_scs(GET_SWZ(src_swizzle, 2)),
 356       .a = swizzle_to_scs(GET_SWZ(src_swizzle, 3)),
 357    };
 358
 359    struct blorp_batch batch;
 360    blorp_batch_init(&brw->blorp, &batch, brw);
 361    blorp_blit(&batch, &src_surf, src_level, src_layer,
 362               brw_blorp_to_isl_format(brw, src_format, false), src_isl_swizzle,
 363               &dst_surf, dst_level, dst_layer,
 364               brw_blorp_to_isl_format(brw, dst_format, true),
 365               ISL_SWIZZLE_IDENTITY,
 366               src_x0, src_y0, src_x1, src_y1,
 367               dst_x0, dst_y0, dst_x1, dst_y1,
 368               filter, mirror_x, mirror_y);
 369    blorp_batch_finish(&batch);
 370
 371    intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_layer);
 372
 373    if (intel_miptree_is_lossless_compressed(brw, dst_mt))
 374       dst_mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
 375 }
 376
 377 static struct intel_mipmap_tree *
 378 find_miptree(GLbitfield buffer_bit, struct intel_renderbuffer *irb)
 379 {
 380    struct intel_mipmap_tree *mt = irb->mt;
 381    if (buffer_bit == GL_STENCIL_BUFFER_BIT && mt->stencil_mt)
 382       mt = mt->stencil_mt;
 383    return mt;
 384 }
 385
 386 static int
 387 blorp_get_texture_swizzle(const struct intel_renderbuffer *irb)
 388 {
 389    return irb->Base.Base._BaseFormat == GL_RGB ?
 390       MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE) :
 391       SWIZZLE_XYZW;
 392 }
 393
 394 static void
 395 do_blorp_blit(struct brw_context *brw, GLbitfield buffer_bit,
 396               struct intel_renderbuffer *src_irb, mesa_format src_format,
 397               struct intel_renderbuffer *dst_irb, mesa_format dst_format,
 398               GLfloat srcX0, GLfloat srcY0, GLfloat srcX1, GLfloat srcY1,
 399               GLfloat dstX0, GLfloat dstY0, GLfloat dstX1, GLfloat dstY1,
 400               GLenum filter, bool mirror_x, bool mirror_y)
 401 {
 402    const struct gl_context *ctx = &brw->ctx;
 403
 404    /* Find source/dst miptrees */
 405    struct intel_mipmap_tree *src_mt = find_miptree(buffer_bit, src_irb);
 406    struct intel_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_irb);
 407
 408    const bool do_srgb = ctx->Color.sRGBEnabled;
 409
 410    /* Do the blit */
 411    brw_blorp_blit_miptrees(brw,
 412                            src_mt, src_irb->mt_level, src_irb->mt_layer,
 413                            src_format, blorp_get_texture_swizzle(src_irb),
 414                            dst_mt, dst_irb->mt_level, dst_irb->mt_layer,
 415                            dst_format,
 416                            srcX0, srcY0, srcX1, srcY1,
 417                            dstX0, dstY0, dstX1, dstY1,
 418                            filter, mirror_x, mirror_y,
 419                            do_srgb, do_srgb);
 420
 421    dst_irb->need_downsample = true;
 422 }
 423
 424 static bool
 425 try_blorp_blit(struct brw_context *brw,
 426                const struct gl_framebuffer *read_fb,
 427                const struct gl_framebuffer *draw_fb,
 428                GLfloat srcX0, GLfloat srcY0, GLfloat srcX1, GLfloat srcY1,
 429                GLfloat dstX0, GLfloat dstY0, GLfloat dstX1, GLfloat dstY1,
 430                GLenum filter, GLbitfield buffer_bit)
 431 {
 432    struct gl_context *ctx = &brw->ctx;
 433
 434    /* Sync up the state of window system buffers.  We need to do this before
 435     * we go looking for the buffers.
 436     */
 437    intel_prepare_render(brw);
 438
 439    bool mirror_x, mirror_y;
 440    if (brw_meta_mirror_clip_and_scissor(ctx, read_fb, draw_fb,
 441                                         &srcX0, &srcY0, &srcX1, &srcY1,
 442                                         &dstX0, &dstY0, &dstX1, &dstY1,
 443                                         &mirror_x, &mirror_y))
 444       return true;
 445
 446    /* Find buffers */
 447    struct intel_renderbuffer *src_irb;
 448    struct intel_renderbuffer *dst_irb;
 449    struct intel_mipmap_tree *src_mt;
 450    struct intel_mipmap_tree *dst_mt;
 451    switch (buffer_bit) {
 452    case GL_COLOR_BUFFER_BIT:
 453       src_irb = intel_renderbuffer(read_fb->_ColorReadBuffer);
 454       for (unsigned i = 0; i < draw_fb->_NumColorDrawBuffers; ++i) {
 455          dst_irb = intel_renderbuffer(draw_fb->_ColorDrawBuffers[i]);
 456          if (dst_irb)
 457             do_blorp_blit(brw, buffer_bit,
 458                           src_irb, src_irb->Base.Base.Format,
 459                           dst_irb, dst_irb->Base.Base.Format,
 460                           srcX0, srcY0, srcX1, srcY1,
 461                           dstX0, dstY0, dstX1, dstY1,
 462                           filter, mirror_x, mirror_y);
 463       }
 464       break;
 465    case GL_DEPTH_BUFFER_BIT:
 466       src_irb =
 467          intel_renderbuffer(read_fb->Attachment[BUFFER_DEPTH].Renderbuffer);
 468       dst_irb =
 469          intel_renderbuffer(draw_fb->Attachment[BUFFER_DEPTH].Renderbuffer);
 470       src_mt = find_miptree(buffer_bit, src_irb);
 471       dst_mt = find_miptree(buffer_bit, dst_irb);
 472
 473       /* We can't handle format conversions between Z24 and other formats
 474        * since we have to lie about the surface format. See the comments in
 475        * brw_blorp_surface_info::set().
 476        */
 477       if ((src_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT) !=
 478           (dst_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT))
 479          return false;
 480
 481       do_blorp_blit(brw, buffer_bit, src_irb, MESA_FORMAT_NONE,
 482                     dst_irb, MESA_FORMAT_NONE, srcX0, srcY0,
 483                     srcX1, srcY1, dstX0, dstY0, dstX1, dstY1,
 484                     filter, mirror_x, mirror_y);
 485       break;
 486    case GL_STENCIL_BUFFER_BIT:
 487       src_irb =
 488          intel_renderbuffer(read_fb->Attachment[BUFFER_STENCIL].Renderbuffer);
 489       dst_irb =
 490          intel_renderbuffer(draw_fb->Attachment[BUFFER_STENCIL].Renderbuffer);
 491       do_blorp_blit(brw, buffer_bit, src_irb, MESA_FORMAT_NONE,
 492                     dst_irb, MESA_FORMAT_NONE, srcX0, srcY0,
 493                     srcX1, srcY1, dstX0, dstY0, dstX1, dstY1,
 494                     filter, mirror_x, mirror_y);
 495       break;
 496    default:
 497       unreachable("not reached");
 498    }
 499
 500    return true;
 501 }
 502
 503 bool
 504 brw_blorp_copytexsubimage(struct brw_context *brw,
 505                           struct gl_renderbuffer *src_rb,
 506                           struct gl_texture_image *dst_image,
 507                           int slice,
 508                           int srcX0, int srcY0,
 509                           int dstX0, int dstY0,
 510                           int width, int height)
 511 {
 512    struct gl_context *ctx = &brw->ctx;
 513    struct intel_renderbuffer *src_irb = intel_renderbuffer(src_rb);
 514    struct intel_texture_image *intel_image = intel_texture_image(dst_image);
 515
 516    /* No pixel transfer operations (zoom, bias, mapping), just a blit */
 517    if (brw->ctx._ImageTransferState)
 518       return false;
 519
 520    /* Sync up the state of window system buffers.  We need to do this before
 521     * we go looking at the src renderbuffer's miptree.
 522     */
 523    intel_prepare_render(brw);
 524
 525    struct intel_mipmap_tree *src_mt = src_irb->mt;
 526    struct intel_mipmap_tree *dst_mt = intel_image->mt;
 527
 528    /* There is support for only up to eight samples. */
 529    if (src_mt->num_samples > 8 || dst_mt->num_samples > 8)
 530       return false;
 531
 532    /* BLORP is only supported from Gen6 onwards. */
 533    if (brw->gen < 6)
 534       return false;
 535
 536    if (_mesa_get_format_base_format(src_rb->Format) !=
 537        _mesa_get_format_base_format(dst_image->TexFormat)) {
 538       return false;
 539    }
 540
 541    /* We can't handle format conversions between Z24 and other formats since
 542     * we have to lie about the surface format.  See the comments in
 543     * brw_blorp_surface_info::set().
 544     */
 545    if ((src_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT) !=
 546        (dst_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT)) {
 547       return false;
 548    }
 549
 550    if (!brw->format_supported_as_render_target[dst_image->TexFormat])
 551       return false;
 552
 553    /* Source clipping shouldn't be necessary, since copytexsubimage (in
 554     * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
 555     * takes care of it.
 556     *
 557     * Destination clipping shouldn't be necessary since the restrictions on
 558     * glCopyTexSubImage prevent the user from specifying a destination rectangle
 559     * that falls outside the bounds of the destination texture.
 560     * See error_check_subtexture_dimensions().
 561     */
 562
 563    int srcY1 = srcY0 + height;
 564    int srcX1 = srcX0 + width;
 565    int dstX1 = dstX0 + width;
 566    int dstY1 = dstY0 + height;
 567
 568    /* Account for the fact that in the system framebuffer, the origin is at
 569     * the lower left.
 570     */
 571    bool mirror_y = false;
 572    if (_mesa_is_winsys_fbo(ctx->ReadBuffer)) {
 573       GLint tmp = src_rb->Height - srcY0;
 574       srcY0 = src_rb->Height - srcY1;
 575       srcY1 = tmp;
 576       mirror_y = true;
 577    }
 578
 579    /* Account for face selection and texture view MinLayer */
 580    int dst_slice = slice + dst_image->TexObject->MinLayer + dst_image->Face;
 581    int dst_level = dst_image->Level + dst_image->TexObject->MinLevel;
 582
 583    brw_blorp_blit_miptrees(brw,
 584                            src_mt, src_irb->mt_level, src_irb->mt_layer,
 585                            src_rb->Format, blorp_get_texture_swizzle(src_irb),
 586                            dst_mt, dst_level, dst_slice,
 587                            dst_image->TexFormat,
 588                            srcX0, srcY0, srcX1, srcY1,
 589                            dstX0, dstY0, dstX1, dstY1,
 590                            GL_NEAREST, false, mirror_y,
 591                            false, false);
 592
 593    /* If we're copying to a packed depth stencil texture and the source
 594     * framebuffer has separate stencil, we need to also copy the stencil data
 595     * over.
 596     */
 597    src_rb = ctx->ReadBuffer->Attachment[BUFFER_STENCIL].Renderbuffer;
 598    if (_mesa_get_format_bits(dst_image->TexFormat, GL_STENCIL_BITS) > 0 &&
 599        src_rb != NULL) {
 600       src_irb = intel_renderbuffer(src_rb);
 601       src_mt = src_irb->mt;
 602
 603       if (src_mt->stencil_mt)
 604          src_mt = src_mt->stencil_mt;
 605       if (dst_mt->stencil_mt)
 606          dst_mt = dst_mt->stencil_mt;
 607
 608       if (src_mt != dst_mt) {
 609          brw_blorp_blit_miptrees(brw,
 610                                  src_mt, src_irb->mt_level, src_irb->mt_layer,
 611                                  src_mt->format,
 612                                  blorp_get_texture_swizzle(src_irb),
 613                                  dst_mt, dst_level, dst_slice,
 614                                  dst_mt->format,
 615                                  srcX0, srcY0, srcX1, srcY1,
 616                                  dstX0, dstY0, dstX1, dstY1,
 617                                  GL_NEAREST, false, mirror_y,
 618                                  false, false);
 619       }
 620    }
 621
 622    return true;
 623 }
 624
 625
 626 GLbitfield
 627 brw_blorp_framebuffer(struct brw_context *brw,
 628                       struct gl_framebuffer *readFb,
 629                       struct gl_framebuffer *drawFb,
 630                       GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
 631                       GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
 632                       GLbitfield mask, GLenum filter)
 633 {
 634    /* BLORP is not supported before Gen6. */
 635    if (brw->gen < 6)
 636       return mask;
 637
 638    static GLbitfield buffer_bits[] = {
 639       GL_COLOR_BUFFER_BIT,
 640       GL_DEPTH_BUFFER_BIT,
 641       GL_STENCIL_BUFFER_BIT,
 642    };
 643
 644    for (unsigned int i = 0; i < ARRAY_SIZE(buffer_bits); ++i) {
 645       if ((mask & buffer_bits[i]) &&
 646        try_blorp_blit(brw, readFb, drawFb,
 647                       srcX0, srcY0, srcX1, srcY1,
 648                       dstX0, dstY0, dstX1, dstY1,
 649                       filter, buffer_bits[i])) {
 650          mask &= ~buffer_bits[i];
 651       }
 652    }
 653
 654    return mask;
 655 }
 656
 657 static bool
 658 set_write_disables(const struct intel_renderbuffer *irb,
 659                    const GLubyte *color_mask, bool *color_write_disable)
 660 {
 661    /* Format information in the renderbuffer represents the requirements
 662     * given by the client. There are cases where the backing miptree uses,
 663     * for example, RGBA to represent RGBX. Since the client is only expecting
 664     * RGB we can treat alpha as not used and write whatever we like into it.
 665     */
 666    const GLenum base_format = irb->Base.Base._BaseFormat;
 667    const int components = _mesa_base_format_component_count(base_format);
 668    bool disables = false;
 669
 670    assert(components > 0);
 671
 672    for (int i = 0; i < components; i++) {
 673       color_write_disable[i] = !color_mask[i];
 674       disables = disables || !color_mask[i];
 675    }
 676
 677    return disables;
 678 }
 679
 680 static bool
 681 do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
 682                       struct gl_renderbuffer *rb, unsigned buf,
 683                       bool partial_clear, bool encode_srgb)
 684 {
 685    struct gl_context *ctx = &brw->ctx;
 686    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 687    mesa_format format = irb->mt->format;
 688    uint32_t x0, x1, y0, y1;
 689
 690    if (!encode_srgb && _mesa_get_format_color_encoding(format) == GL_SRGB)
 691       format = _mesa_get_srgb_format_linear(format);
 692
 693    x0 = fb->_Xmin;
 694    x1 = fb->_Xmax;
 695    if (rb->Name != 0) {
 696       y0 = fb->_Ymin;
 697       y1 = fb->_Ymax;
 698    } else {
 699       y0 = rb->Height - fb->_Ymax;
 700       y1 = rb->Height - fb->_Ymin;
 701    }
 702
 703    /* If the clear region is empty, just return. */
 704    if (x0 == x1 || y0 == y1)
 705       return true;
 706
 707    bool can_fast_clear = !partial_clear;
 708
 709    bool color_write_disable[4] = { false, false, false, false };
 710    if (set_write_disables(irb, ctx->Color.ColorMask[buf], color_write_disable))
 711       can_fast_clear = false;
 712
 713    if (irb->mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_NO_MCS ||
 714        !brw_is_color_fast_clear_compatible(brw, irb->mt, &ctx->Color.ClearColor))
 715       can_fast_clear = false;
 716
 717    const bool is_lossless_compressed = intel_miptree_is_lossless_compressed(
 718                                           brw, irb->mt);
 719
 720    if (can_fast_clear) {
 721       /* Record the clear color in the miptree so that it will be
 722        * programmed in SURFACE_STATE by later rendering and resolve
 723        * operations.
 724        */
 725       const bool color_updated = brw_meta_set_fast_clear_color(
 726                                     brw, irb->mt, &ctx->Color.ClearColor);
 727
 728       /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
 729        * is redundant and can be skipped.
 730        */
 731       if (!color_updated &&
 732           irb->mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
 733          return true;
 734
 735       /* If the MCS buffer hasn't been allocated yet, we need to allocate
 736        * it now.
 737        */
 738       if (!irb->mt->mcs_mt) {
 739          assert(!is_lossless_compressed);
 740          if (!intel_miptree_alloc_non_msrt_mcs(brw, irb->mt, false)) {
 741             /* MCS allocation failed--probably this will only happen in
 742              * out-of-memory conditions.  But in any case, try to recover
 743              * by falling back to a non-blorp clear technique.
 744              */
 745             return false;
 746          }
 747       }
 748    }
 749
 750    intel_miptree_used_for_rendering(irb->mt);
 751
 752    /* We can't setup the blorp_surf until we've allocated the MCS above */
 753    struct isl_surf isl_tmp[2];
 754    struct blorp_surf surf;
 755    unsigned level = irb->mt_level;
 756    blorp_surf_for_miptree(brw, &surf, irb->mt, true, &level, isl_tmp);
 757    const unsigned num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
 758
 759    if (can_fast_clear) {
 760       DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__,
 761           irb->mt, irb->mt_level, irb->mt_layer, num_layers);
 762
 763       struct blorp_batch batch;
 764       blorp_batch_init(&brw->blorp, &batch, brw);
 765       blorp_fast_clear(&batch, &surf,
 766                        (enum isl_format)brw->render_target_format[format],
 767                        level, irb->mt_layer, num_layers, x0, y0, x1, y1);
 768       blorp_batch_finish(&batch);
 769
 770       /* Now that the fast clear has occurred, put the buffer in
 771        * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
 772        * redundant clears.
 773        */
 774       irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_CLEAR;
 775    } else {
 776       DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__,
 777           irb->mt, irb->mt_level, irb->mt_layer, num_layers);
 778
 779       union isl_color_value clear_color;
 780       memcpy(clear_color.f32, ctx->Color.ClearColor.f, sizeof(float) * 4);
 781
 782       struct blorp_batch batch;
 783       blorp_batch_init(&brw->blorp, &batch, brw);
 784       blorp_clear(&batch, &surf, level, irb->mt_layer, num_layers,
 785                   x0, y0, x1, y1,
 786                   (enum isl_format)brw->render_target_format[format],
 787                   clear_color, color_write_disable);
 788       blorp_batch_finish(&batch);
 789
 790       if (is_lossless_compressed) {
 791          /* Compressed buffers can be cleared also using normal rep-clear. In
 792           * such case they behave such as if they were drawn using normal 3D
 793           * render pipeline, and we simply mark the mcs as dirty.
 794           */
 795          irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
 796       }
 797    }
 798
 799    return true;
 800 }
 801
 802 bool
 803 brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb,
 804                       GLbitfield mask, bool partial_clear, bool encode_srgb)
 805 {
 806    for (unsigned buf = 0; buf < fb->_NumColorDrawBuffers; buf++) {
 807       struct gl_renderbuffer *rb = fb->_ColorDrawBuffers[buf];
 808       struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 809
 810       /* Only clear the buffers present in the provided mask */
 811       if (((1 << fb->_ColorDrawBufferIndexes[buf]) & mask) == 0)
 812          continue;
 813
 814       /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
 815        * the framebuffer can be complete with some attachments missing.  In
 816        * this case the _ColorDrawBuffers pointer will be NULL.
 817        */
 818       if (rb == NULL)
 819          continue;
 820
 821       const unsigned num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
 822       for (unsigned layer = 0; layer < num_layers; layer++) {
 823          intel_miptree_check_level_layer(irb->mt, irb->mt_level, layer);
 824       }
 825
 826       if (!do_single_blorp_clear(brw, fb, rb, buf, partial_clear,
 827                                  encode_srgb)) {
 828          return false;
 829       }
 830
 831       irb->need_downsample = true;
 832    }
 833
 834    return true;
 835 }
 836
 837 void
 838 brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt)
 839 {
 840    DBG("%s to mt %p\n", __FUNCTION__, mt);
 841
 842    const mesa_format format = _mesa_get_srgb_format_linear(mt->format);
 843
 844    intel_miptree_check_level_layer(mt, 0 /* level */, 0 /* layer */);
 845    intel_miptree_used_for_rendering(mt);
 846
 847    struct isl_surf isl_tmp[2];
 848    struct blorp_surf surf;
 849    unsigned level = 0;
 850    blorp_surf_for_miptree(brw, &surf, mt, true, &level, isl_tmp);
 851
 852    struct blorp_batch batch;
 853    blorp_batch_init(&brw->blorp, &batch, brw);
 854    blorp_ccs_resolve(&batch, &surf,
 855                      brw_blorp_to_isl_format(brw, format, true));
 856    blorp_batch_finish(&batch);
 857
 858    mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
 859 }
 860
 861 static void
 862 gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 863                     unsigned int level, unsigned int layer, enum blorp_hiz_op op)
 864 {
 865    intel_miptree_check_level_layer(mt, level, layer);
 866    intel_miptree_used_for_rendering(mt);
 867
 868    assert(intel_miptree_level_has_hiz(mt, level));
 869
 870    struct isl_surf isl_tmp[2];
 871    struct blorp_surf surf;
 872    blorp_surf_for_miptree(brw, &surf, mt, true, &level, isl_tmp);
 873
 874    struct blorp_batch batch;
 875    blorp_batch_init(&brw->blorp, &batch, brw);
 876    blorp_gen6_hiz_op(&batch, &surf, level, layer, op);
 877    blorp_batch_finish(&batch);
 878 }
 879
 880 /**
 881  * Perform a HiZ or depth resolve operation.
 882  *
 883  * For an overview of HiZ ops, see the following sections of the Sandy Bridge
 884  * PRM, Volume 1, Part 2:
 885  *   - 7.5.3.1 Depth Buffer Clear
 886  *   - 7.5.3.2 Depth Buffer Resolve
 887  *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
 888  */
 889 void
 890 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 891                unsigned int level, unsigned int layer, enum blorp_hiz_op op)
 892 {
 893    const char *opname = NULL;
 894
 895    switch (op) {
 896    case BLORP_HIZ_OP_DEPTH_RESOLVE:
 897       opname = "depth resolve";
 898       break;
 899    case BLORP_HIZ_OP_HIZ_RESOLVE:
 900       opname = "hiz ambiguate";
 901       break;
 902    case BLORP_HIZ_OP_DEPTH_CLEAR:
 903       opname = "depth clear";
 904       break;
 905    case BLORP_HIZ_OP_NONE:
 906       opname = "noop?";
 907       break;
 908    }
 909
 910    DBG("%s %s to mt %p level %d layer %d\n",
 911        __func__, opname, mt, level, layer);
 912
 913    if (brw->gen >= 8) {
 914       gen8_hiz_exec(brw, mt, level, layer, op);
 915    } else {
 916       gen6_blorp_hiz_exec(brw, mt, level, layer, op);
 917    }
 918 }