2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_batchbuffer.h"
26 #include "intel_fbo.h"
28 #include "brw_blorp.h"
29 #include "brw_compiler.h"
31 #include "brw_state.h"
33 #define FILE_DEBUG_FLAG DEBUG_BLORP
36 brw_blorp_surface_info_init(struct brw_context
*brw
,
37 struct brw_blorp_surface_info
*info
,
38 struct intel_mipmap_tree
*mt
,
39 unsigned int level
, unsigned int layer
,
40 mesa_format format
, bool is_render_target
)
42 /* Layer is a physical layer, so if this is a 2D multisample array texture
43 * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it had better
44 * be a multiple of num_samples.
46 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
47 mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
48 assert(mt
->num_samples
<= 1 || layer
% mt
->num_samples
== 0);
51 intel_miptree_check_level_layer(mt
, level
, layer
);
55 intel_miptree_get_isl_surf(brw
, mt
, &info
->surf
);
58 intel_miptree_get_aux_isl_surf(brw
, mt
, &info
->aux_surf
,
61 info
->aux_usage
= ISL_AUX_USAGE_NONE
;
66 info
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
67 info
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
69 intel_miptree_get_image_offset(mt
, level
, layer
,
70 &info
->x_offset
, &info
->y_offset
);
72 info
->array_layout
= mt
->array_layout
;
73 info
->msaa_layout
= mt
->msaa_layout
;
74 info
->swizzle
= SWIZZLE_XYZW
;
76 if (format
== MESA_FORMAT_NONE
)
80 case MESA_FORMAT_S_UINT8
:
81 assert(info
->surf
.tiling
== ISL_TILING_W
);
82 /* Prior to Broadwell, we can't render to R8_UINT */
83 info
->brw_surfaceformat
= brw
->gen
>= 8 ? BRW_SURFACEFORMAT_R8_UINT
:
84 BRW_SURFACEFORMAT_R8_UNORM
;
86 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
87 /* It would make sense to use BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
88 * here, but unfortunately it isn't supported as a render target, which
89 * would prevent us from blitting to 24-bit depth.
91 * The miptree consists of 32 bits per pixel, arranged as 24-bit depth
92 * values interleaved with 8 "don't care" bits. Since depth values don't
93 * require any blending, it doesn't matter how we interpret the bit
94 * pattern as long as we copy the right amount of data, so just map it
97 info
->brw_surfaceformat
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
99 case MESA_FORMAT_Z_FLOAT32
:
100 info
->brw_surfaceformat
= BRW_SURFACEFORMAT_R32_FLOAT
;
102 case MESA_FORMAT_Z_UNORM16
:
103 info
->brw_surfaceformat
= BRW_SURFACEFORMAT_R16_UNORM
;
106 if (is_render_target
) {
107 assert(brw
->format_supported_as_render_target
[format
]);
108 info
->brw_surfaceformat
= brw
->render_target_format
[format
];
110 info
->brw_surfaceformat
= brw_format_for_mesa_format(format
);
119 brw_blorp_params_init(struct brw_blorp_params
*params
)
121 memset(params
, 0, sizeof(*params
));
122 params
->hiz_op
= GEN6_HIZ_OP_NONE
;
123 params
->fast_clear_op
= 0;
124 params
->num_draw_buffers
= 1;
125 params
->num_layers
= 1;
129 brw_blorp_init_wm_prog_key(struct brw_wm_prog_key
*wm_key
)
131 memset(wm_key
, 0, sizeof(*wm_key
));
132 wm_key
->nr_color_regions
= 1;
133 for (int i
= 0; i
< MAX_SAMPLERS
; i
++)
134 wm_key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;
138 nir_uniform_type_size(const struct glsl_type
*type
)
140 /* Only very basic types are allowed */
141 assert(glsl_type_is_vector_or_scalar(type
));
142 assert(glsl_get_bit_size(type
) == 32);
144 return glsl_get_vector_elements(type
) * 4;
148 brw_blorp_compile_nir_shader(struct brw_context
*brw
, struct nir_shader
*nir
,
149 const struct brw_wm_prog_key
*wm_key
,
151 struct brw_blorp_prog_data
*prog_data
,
152 unsigned *program_size
)
154 const struct brw_compiler
*compiler
= brw
->intelScreen
->compiler
;
156 void *mem_ctx
= ralloc_context(NULL
);
158 /* Calling brw_preprocess_nir and friends is destructive and, if cloning is
159 * enabled, may end up completely replacing the nir_shader. Therefore, we
160 * own it and might as well put it in our context for easy cleanup.
162 ralloc_steal(mem_ctx
, nir
);
164 compiler
->glsl_compiler_options
[MESA_SHADER_FRAGMENT
].NirOptions
;
166 struct brw_wm_prog_data wm_prog_data
;
167 memset(&wm_prog_data
, 0, sizeof(wm_prog_data
));
169 wm_prog_data
.base
.nr_params
= 0;
170 wm_prog_data
.base
.param
= NULL
;
172 /* BLORP always just uses the first two binding table entries */
173 wm_prog_data
.binding_table
.render_target_start
= 0;
174 wm_prog_data
.base
.binding_table
.texture_start
= 1;
176 nir
= brw_preprocess_nir(compiler
, nir
);
177 nir_remove_dead_variables(nir
, nir_var_shader_in
);
178 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
)->impl
);
180 /* Uniforms are required to be lowered before going into compile_fs. For
181 * BLORP, we'll assume that whoever builds the shader sets the location
182 * they want so we just need to lower them and figure out how many we have
185 nir
->num_uniforms
= 0;
186 nir_foreach_variable(var
, &nir
->uniforms
) {
187 var
->data
.driver_location
= var
->data
.location
;
188 unsigned end
= var
->data
.location
+ nir_uniform_type_size(var
->type
);
189 nir
->num_uniforms
= MAX2(nir
->num_uniforms
, end
);
191 nir_lower_io(nir
, nir_var_uniform
, nir_uniform_type_size
);
193 const unsigned *program
=
194 brw_compile_fs(compiler
, brw
, mem_ctx
, wm_key
, &wm_prog_data
, nir
,
195 NULL
, -1, -1, false, use_repclear
, program_size
, NULL
);
197 /* Copy the relavent bits of wm_prog_data over into the blorp prog data */
198 prog_data
->dispatch_8
= wm_prog_data
.dispatch_8
;
199 prog_data
->dispatch_16
= wm_prog_data
.dispatch_16
;
200 prog_data
->first_curbe_grf_0
= wm_prog_data
.base
.dispatch_grf_start_reg
;
201 prog_data
->first_curbe_grf_2
= wm_prog_data
.dispatch_grf_start_reg_2
;
202 prog_data
->ksp_offset_2
= wm_prog_data
.prog_offset_2
;
203 prog_data
->persample_msaa_dispatch
= wm_prog_data
.persample_dispatch
;
204 prog_data
->flat_inputs
= wm_prog_data
.flat_inputs
;
205 prog_data
->num_varying_inputs
= wm_prog_data
.num_varying_inputs
;
206 prog_data
->inputs_read
= nir
->info
.inputs_read
;
208 assert(wm_prog_data
.base
.nr_params
== 0);
213 static enum isl_msaa_layout
214 get_isl_msaa_layout(enum intel_msaa_layout layout
)
217 case INTEL_MSAA_LAYOUT_NONE
:
218 return ISL_MSAA_LAYOUT_NONE
;
219 case INTEL_MSAA_LAYOUT_IMS
:
220 return ISL_MSAA_LAYOUT_INTERLEAVED
;
221 case INTEL_MSAA_LAYOUT_UMS
:
222 case INTEL_MSAA_LAYOUT_CMS
:
223 return ISL_MSAA_LAYOUT_ARRAY
;
225 unreachable("Invalid MSAA layout");
229 struct surface_state_info
{
231 unsigned ss_align
; /* Required alignment of RENDER_SURFACE_STATE in bytes */
233 unsigned aux_reloc_dw
;
238 static const struct surface_state_info surface_state_infos
[] = {
240 [7] = {8, 32, 1, 6, GEN7_MOCS_L3
, GEN7_MOCS_L3
},
241 [8] = {13, 64, 8, 10, BDW_MOCS_WB
, BDW_MOCS_PTE
},
242 [9] = {16, 64, 8, 10, SKL_MOCS_WB
, SKL_MOCS_PTE
},
246 brw_blorp_emit_surface_state(struct brw_context
*brw
,
247 const struct brw_blorp_surface_info
*surface
,
248 uint32_t read_domains
, uint32_t write_domain
,
249 bool is_render_target
)
251 const struct surface_state_info ss_info
= surface_state_infos
[brw
->gen
];
253 struct isl_surf surf
= surface
->surf
;
255 /* Stomp surface dimensions and tiling (if needed) with info from blorp */
256 surf
.dim
= ISL_SURF_DIM_2D
;
257 surf
.dim_layout
= ISL_DIM_LAYOUT_GEN4_2D
;
258 surf
.msaa_layout
= get_isl_msaa_layout(surface
->msaa_layout
);
259 surf
.logical_level0_px
.width
= surface
->width
;
260 surf
.logical_level0_px
.height
= surface
->height
;
261 surf
.logical_level0_px
.depth
= 1;
262 surf
.logical_level0_px
.array_len
= 1;
265 /* Alignment doesn't matter since we have 1 miplevel and 1 array slice so
266 * just pick something that works for everybody.
268 surf
.image_alignment_el
= isl_extent3d(4, 4, 1);
270 if (brw
->gen
== 6 && surf
.samples
> 1) {
271 /* Since gen6 uses INTEL_MSAA_LAYOUT_IMS, width and height are measured
272 * in samples. But SURFACE_STATE wants them in pixels, so we need to
273 * divide them each by 2.
275 surf
.logical_level0_px
.width
/= 2;
276 surf
.logical_level0_px
.height
/= 2;
279 if (brw
->gen
== 6 && surf
.image_alignment_el
.height
> 4) {
280 /* This can happen on stencil buffers on Sandy Bridge due to the
281 * single-LOD work-around. It's fairly harmless as long as we don't
282 * pass a bogus value into isl_surf_fill_state().
284 surf
.image_alignment_el
= isl_extent3d(4, 2, 1);
287 union isl_color_value clear_color
= { .u32
= { 0, 0, 0, 0 } };
289 const struct isl_surf
*aux_surf
= NULL
;
290 uint64_t aux_offset
= 0;
291 if (surface
->mt
->mcs_mt
) {
292 aux_surf
= &surface
->aux_surf
;
293 assert(surface
->mt
->mcs_mt
->offset
== 0);
294 aux_offset
= surface
->mt
->mcs_mt
->bo
->offset64
;
296 /* We only really need a clear color if we also have an auxiliary
297 * surface. Without one, it does nothing.
299 clear_color
= intel_miptree_get_isl_clear_color(brw
, surface
->mt
);
302 struct isl_view view
= {
303 .format
= surface
->brw_surfaceformat
,
306 .base_array_layer
= 0,
309 ISL_CHANNEL_SELECT_RED
,
310 ISL_CHANNEL_SELECT_GREEN
,
311 ISL_CHANNEL_SELECT_BLUE
,
312 ISL_CHANNEL_SELECT_ALPHA
,
314 .usage
= is_render_target
? ISL_SURF_USAGE_RENDER_TARGET_BIT
:
315 ISL_SURF_USAGE_TEXTURE_BIT
,
318 uint32_t offset
, tile_x
, tile_y
;
319 isl_tiling_get_intratile_offset_el(&brw
->isl_dev
, surf
.tiling
,
320 isl_format_get_layout(view
.format
)->bpb
/ 8,
322 surface
->x_offset
, surface
->y_offset
,
323 &offset
, &tile_x
, &tile_y
);
325 uint32_t surf_offset
;
326 uint32_t *dw
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
327 ss_info
.num_dwords
* 4, ss_info
.ss_align
,
330 const uint32_t mocs
= is_render_target
? ss_info
.rb_mocs
: ss_info
.tex_mocs
;
332 isl_surf_fill_state(&brw
->isl_dev
, dw
, .surf
= &surf
, .view
= &view
,
333 .address
= surface
->mt
->bo
->offset64
+ offset
,
334 .aux_surf
= aux_surf
, .aux_usage
= surface
->aux_usage
,
335 .aux_address
= aux_offset
,
336 .mocs
= mocs
, .clear_color
= clear_color
,
337 .x_offset_sa
= tile_x
, .y_offset_sa
= tile_y
);
339 /* Emit relocation to surface contents */
340 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
341 surf_offset
+ ss_info
.reloc_dw
* 4,
343 dw
[ss_info
.reloc_dw
] - surface
->mt
->bo
->offset64
,
344 read_domains
, write_domain
);
347 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
348 * used to store other information. This should be ok, however, because
349 * surface buffer addresses are always 4K page alinged.
351 assert((aux_offset
& 0xfff) == 0);
352 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
353 surf_offset
+ ss_info
.aux_reloc_dw
* 4,
354 surface
->mt
->mcs_mt
->bo
,
355 dw
[ss_info
.aux_reloc_dw
] & 0xfff,
356 read_domains
, write_domain
);
363 * Perform a HiZ or depth resolve operation.
365 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
366 * PRM, Volume 1, Part 2:
367 * - 7.5.3.1 Depth Buffer Clear
368 * - 7.5.3.2 Depth Buffer Resolve
369 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
372 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
373 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
)
375 const char *opname
= NULL
;
378 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
379 opname
= "depth resolve";
381 case GEN6_HIZ_OP_HIZ_RESOLVE
:
382 opname
= "hiz ambiguate";
384 case GEN6_HIZ_OP_DEPTH_CLEAR
:
385 opname
= "depth clear";
387 case GEN6_HIZ_OP_NONE
:
392 DBG("%s %s to mt %p level %d layer %d\n",
393 __func__
, opname
, mt
, level
, layer
);
396 gen8_hiz_exec(brw
, mt
, level
, layer
, op
);
398 gen6_blorp_hiz_exec(brw
, mt
, level
, layer
, op
);
403 brw_blorp_exec(struct brw_context
*brw
, const struct brw_blorp_params
*params
)
405 struct gl_context
*ctx
= &brw
->ctx
;
406 const uint32_t estimated_max_batch_usage
= brw
->gen
>= 8 ? 1800 : 1500;
407 bool check_aperture_failed_once
= false;
409 /* Flush the sampler and render caches. We definitely need to flush the
410 * sampler cache so that we get updated contents from the render cache for
411 * the glBlitFramebuffer() source. Also, we are sometimes warned in the
412 * docs to flush the cache between reinterpretations of the same surface
413 * data with different formats, which blorp does for stencil and depth
416 brw_emit_mi_flush(brw
);
418 brw_select_pipeline(brw
, BRW_RENDER_PIPELINE
);
421 intel_batchbuffer_require_space(brw
, estimated_max_batch_usage
, RENDER_RING
);
422 intel_batchbuffer_save_state(brw
);
423 drm_intel_bo
*saved_bo
= brw
->batch
.bo
;
424 uint32_t saved_used
= USED_BATCH(brw
->batch
);
425 uint32_t saved_state_batch_offset
= brw
->batch
.state_batch_offset
;
429 gen6_blorp_exec(brw
, params
);
432 gen7_blorp_exec(brw
, params
);
436 gen8_blorp_exec(brw
, params
);
439 /* BLORP is not supported before Gen6. */
440 unreachable("not reached");
443 /* Make sure we didn't wrap the batch unintentionally, and make sure we
444 * reserved enough space that a wrap will never happen.
446 assert(brw
->batch
.bo
== saved_bo
);
447 assert((USED_BATCH(brw
->batch
) - saved_used
) * 4 +
448 (saved_state_batch_offset
- brw
->batch
.state_batch_offset
) <
449 estimated_max_batch_usage
);
450 /* Shut up compiler warnings on release build */
453 (void)saved_state_batch_offset
;
455 /* Check if the blorp op we just did would make our batch likely to fail to
456 * map all the BOs into the GPU at batch exec time later. If so, flush the
457 * batch and try again with nothing else in the batch.
459 if (dri_bufmgr_check_aperture_space(&brw
->batch
.bo
, 1)) {
460 if (!check_aperture_failed_once
) {
461 check_aperture_failed_once
= true;
462 intel_batchbuffer_reset_to_saved(brw
);
463 intel_batchbuffer_flush(brw
);
466 int ret
= intel_batchbuffer_flush(brw
);
467 WARN_ONCE(ret
== -ENOSPC
,
468 "i965: blorp emit exceeded available aperture space\n");
472 if (unlikely(brw
->always_flush_batch
))
473 intel_batchbuffer_flush(brw
);
475 /* We've smashed all state compared to what the normal 3D pipeline
476 * rendering tracks for GL.
478 brw
->ctx
.NewDriverState
|= BRW_NEW_BLORP
;
479 brw
->no_depth_or_stencil
= false;
482 /* Flush the sampler cache so any texturing from the destination is
485 brw_emit_mi_flush(brw
);
489 gen6_blorp_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
490 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
)
492 struct brw_blorp_params params
;
493 brw_blorp_params_init(¶ms
);
497 brw_blorp_surface_info_init(brw
, ¶ms
.depth
, mt
, level
, layer
,
500 /* Align the rectangle primitive to 8x4 pixels.
502 * During fast depth clears, the emitted rectangle primitive must be
503 * aligned to 8x4 pixels. From the Ivybridge PRM, Vol 2 Part 1 Section
504 * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
506 * If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
507 * aligned to an 8x4 pixel block relative to the upper left corner
508 * of the depth buffer [...]
510 * For hiz resolves, the rectangle must also be 8x4 aligned. Item
511 * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
512 * Ivybridge simulator require the alignment.
514 * To be safe, let's just align the rect for all hiz operations and all
515 * hardware generations.
517 * However, for some miptree slices of a Z24 texture, emitting an 8x4
518 * aligned rectangle that covers the slice may clobber adjacent slices if
519 * we strictly adhered to the texture alignments specified in the PRM. The
520 * Ivybridge PRM, Section "Alignment Unit Size", states that
521 * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
522 * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
523 * prevents the clobbering.
525 params
.dst
.surf
.samples
= MAX2(mt
->num_samples
, 1);
526 if (params
.depth
.surf
.samples
> 1) {
527 params
.depth
.width
= ALIGN(mt
->logical_width0
, 8);
528 params
.depth
.height
= ALIGN(mt
->logical_height0
, 4);
530 params
.depth
.width
= ALIGN(params
.depth
.width
, 8);
531 params
.depth
.height
= ALIGN(params
.depth
.height
, 4);
534 params
.x1
= params
.depth
.width
;
535 params
.y1
= params
.depth
.height
;
537 assert(intel_miptree_level_has_hiz(mt
, level
));
539 switch (mt
->format
) {
540 case MESA_FORMAT_Z_UNORM16
:
541 params
.depth_format
= BRW_DEPTHFORMAT_D16_UNORM
;
543 case MESA_FORMAT_Z_FLOAT32
:
544 params
.depth_format
= BRW_DEPTHFORMAT_D32_FLOAT
;
546 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
547 params
.depth_format
= BRW_DEPTHFORMAT_D24_UNORM_X8_UINT
;
550 unreachable("not reached");
553 brw_blorp_exec(brw
, ¶ms
);