2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/blend.h"
27 #include "main/bufferobj.h"
28 #include "main/enums.h"
29 #include "main/fbobject.h"
30 #include "main/image.h"
31 #include "main/renderbuffer.h"
32 #include "main/glformats.h"
34 #include "brw_blorp.h"
35 #include "brw_context.h"
36 #include "brw_defines.h"
37 #include "brw_meta_util.h"
38 #include "brw_state.h"
39 #include "intel_buffer_objects.h"
40 #include "intel_fbo.h"
41 #include "common/gen_debug.h"
43 #define FILE_DEBUG_FLAG DEBUG_BLORP
46 brw_blorp_lookup_shader(struct blorp_context
*blorp
,
47 const void *key
, uint32_t key_size
,
48 uint32_t *kernel_out
, void *prog_data_out
)
50 struct brw_context
*brw
= blorp
->driver_ctx
;
51 return brw_search_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
,
52 key
, key_size
, kernel_out
, prog_data_out
);
56 brw_blorp_upload_shader(struct blorp_context
*blorp
,
57 const void *key
, uint32_t key_size
,
58 const void *kernel
, uint32_t kernel_size
,
59 const struct brw_stage_prog_data
*prog_data
,
60 uint32_t prog_data_size
,
61 uint32_t *kernel_out
, void *prog_data_out
)
63 struct brw_context
*brw
= blorp
->driver_ctx
;
64 brw_upload_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
, key
, key_size
,
65 kernel
, kernel_size
, prog_data
, prog_data_size
,
66 kernel_out
, prog_data_out
);
71 brw_blorp_init(struct brw_context
*brw
)
73 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
75 blorp_init(&brw
->blorp
, brw
, &brw
->isl_dev
);
77 brw
->blorp
.compiler
= brw
->screen
->compiler
;
79 switch (devinfo
->gen
) {
81 if (devinfo
->is_g4x
) {
82 brw
->blorp
.exec
= gen45_blorp_exec
;
84 brw
->blorp
.exec
= gen4_blorp_exec
;
88 brw
->blorp
.exec
= gen5_blorp_exec
;
91 brw
->blorp
.mocs
.tex
= 0;
92 brw
->blorp
.mocs
.rb
= 0;
93 brw
->blorp
.mocs
.vb
= 0;
94 brw
->blorp
.exec
= gen6_blorp_exec
;
97 brw
->blorp
.mocs
.tex
= GEN7_MOCS_L3
;
98 brw
->blorp
.mocs
.rb
= GEN7_MOCS_L3
;
99 brw
->blorp
.mocs
.vb
= GEN7_MOCS_L3
;
100 if (devinfo
->is_haswell
) {
101 brw
->blorp
.exec
= gen75_blorp_exec
;
103 brw
->blorp
.exec
= gen7_blorp_exec
;
107 brw
->blorp
.mocs
.tex
= BDW_MOCS_WB
;
108 brw
->blorp
.mocs
.rb
= BDW_MOCS_PTE
;
109 brw
->blorp
.mocs
.vb
= BDW_MOCS_WB
;
110 brw
->blorp
.exec
= gen8_blorp_exec
;
113 brw
->blorp
.mocs
.tex
= SKL_MOCS_WB
;
114 brw
->blorp
.mocs
.rb
= SKL_MOCS_PTE
;
115 brw
->blorp
.mocs
.vb
= SKL_MOCS_WB
;
116 brw
->blorp
.exec
= gen9_blorp_exec
;
119 brw
->blorp
.mocs
.tex
= CNL_MOCS_WB
;
120 brw
->blorp
.mocs
.rb
= CNL_MOCS_PTE
;
121 brw
->blorp
.mocs
.vb
= CNL_MOCS_WB
;
122 brw
->blorp
.exec
= gen10_blorp_exec
;
125 unreachable("Invalid gen");
128 brw
->blorp
.lookup_shader
= brw_blorp_lookup_shader
;
129 brw
->blorp
.upload_shader
= brw_blorp_upload_shader
;
133 blorp_surf_for_miptree(struct brw_context
*brw
,
134 struct blorp_surf
*surf
,
135 struct intel_mipmap_tree
*mt
,
136 enum isl_aux_usage aux_usage
,
137 bool is_render_target
,
139 unsigned start_layer
, unsigned num_layers
,
140 struct isl_surf tmp_surfs
[1])
142 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
144 if (mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
) {
145 const unsigned num_samples
= mt
->surf
.samples
;
146 for (unsigned i
= 0; i
< num_layers
; i
++) {
147 for (unsigned s
= 0; s
< num_samples
; s
++) {
148 const unsigned phys_layer
= (start_layer
+ i
) * num_samples
+ s
;
149 intel_miptree_check_level_layer(mt
, *level
, phys_layer
);
153 for (unsigned i
= 0; i
< num_layers
; i
++)
154 intel_miptree_check_level_layer(mt
, *level
, start_layer
+ i
);
157 surf
->surf
= &mt
->surf
;
158 surf
->addr
= (struct blorp_address
) {
160 .offset
= mt
->offset
,
161 .reloc_flags
= is_render_target
? EXEC_OBJECT_WRITE
: 0,
164 surf
->aux_usage
= aux_usage
;
166 struct isl_surf
*aux_surf
= NULL
;
168 aux_surf
= &mt
->mcs_buf
->surf
;
169 else if (mt
->hiz_buf
)
170 aux_surf
= &mt
->hiz_buf
->surf
;
172 if (mt
->format
== MESA_FORMAT_S_UINT8
&& is_render_target
&&
174 mt
->r8stencil_needs_update
= true;
176 if (surf
->aux_usage
== ISL_AUX_USAGE_HIZ
&&
177 !intel_miptree_level_has_hiz(mt
, *level
))
178 surf
->aux_usage
= ISL_AUX_USAGE_NONE
;
180 if (surf
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
181 /* We only really need a clear color if we also have an auxiliary
182 * surface. Without one, it does nothing.
184 surf
->clear_color
= mt
->fast_clear_color
;
186 surf
->aux_surf
= aux_surf
;
187 surf
->aux_addr
= (struct blorp_address
) {
188 .reloc_flags
= is_render_target
? EXEC_OBJECT_WRITE
: 0,
192 surf
->aux_addr
.buffer
= mt
->mcs_buf
->bo
;
193 surf
->aux_addr
.offset
= mt
->mcs_buf
->offset
;
196 assert(surf
->aux_usage
== ISL_AUX_USAGE_HIZ
);
198 surf
->aux_addr
.buffer
= mt
->hiz_buf
->bo
;
199 surf
->aux_addr
.offset
= mt
->hiz_buf
->offset
;
202 surf
->aux_addr
= (struct blorp_address
) {
205 memset(&surf
->clear_color
, 0, sizeof(surf
->clear_color
));
207 assert((surf
->aux_usage
== ISL_AUX_USAGE_NONE
) ==
208 (surf
->aux_addr
.buffer
== NULL
));
210 /* ISL wants real levels, not offset ones. */
211 *level
-= mt
->first_level
;
214 static enum isl_format
215 brw_blorp_to_isl_format(struct brw_context
*brw
, mesa_format format
,
216 bool is_render_target
)
219 case MESA_FORMAT_NONE
:
220 return ISL_FORMAT_UNSUPPORTED
;
221 case MESA_FORMAT_S_UINT8
:
222 return ISL_FORMAT_R8_UINT
;
223 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
224 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
225 return ISL_FORMAT_R24_UNORM_X8_TYPELESS
;
226 case MESA_FORMAT_Z_FLOAT32
:
227 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
228 return ISL_FORMAT_R32_FLOAT
;
229 case MESA_FORMAT_Z_UNORM16
:
230 return ISL_FORMAT_R16_UNORM
;
232 if (is_render_target
) {
233 assert(brw
->mesa_format_supports_render
[format
]);
234 return brw
->mesa_to_isl_render_format
[format
];
236 return brw_isl_format_for_mesa_format(format
);
244 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
245 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
247 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
250 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
252 * which is simply adding 4 then modding by 8 (or anding with 7).
254 * We then may need to apply workarounds for textureGather hardware bugs.
256 static enum isl_channel_select
257 swizzle_to_scs(GLenum swizzle
)
259 return (enum isl_channel_select
)((swizzle
+ 4) & 7);
263 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
264 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
265 * the physical layer holding sample 0. So, for example, if
266 * src_mt->surf.samples == 4, then logical layer n corresponds to src_layer ==
270 brw_blorp_blit_miptrees(struct brw_context
*brw
,
271 struct intel_mipmap_tree
*src_mt
,
272 unsigned src_level
, unsigned src_layer
,
273 mesa_format src_format
, int src_swizzle
,
274 struct intel_mipmap_tree
*dst_mt
,
275 unsigned dst_level
, unsigned dst_layer
,
276 mesa_format dst_format
,
277 float src_x0
, float src_y0
,
278 float src_x1
, float src_y1
,
279 float dst_x0
, float dst_y0
,
280 float dst_x1
, float dst_y1
,
281 GLenum filter
, bool mirror_x
, bool mirror_y
,
282 bool decode_srgb
, bool encode_srgb
)
284 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
286 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
287 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
289 src_mt
->surf
.samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
290 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
291 dst_mt
->surf
.samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
292 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
295 if (!decode_srgb
&& _mesa_get_format_color_encoding(src_format
) == GL_SRGB
)
296 src_format
= _mesa_get_srgb_format_linear(src_format
);
298 if (!encode_srgb
&& _mesa_get_format_color_encoding(dst_format
) == GL_SRGB
)
299 dst_format
= _mesa_get_srgb_format_linear(dst_format
);
301 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
302 * texture, the above code configures the source format for L32_FLOAT or
303 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
304 * the SAMPLE message appears to handle multisampled L32_FLOAT and
305 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
306 * around the problem by using a source format of R32_FLOAT. This
307 * shouldn't affect rendering correctness, since the destination format is
308 * R32_FLOAT, so only the contents of the red channel matters.
310 if (devinfo
->gen
== 6 &&
311 src_mt
->surf
.samples
> 1 && dst_mt
->surf
.samples
<= 1 &&
312 src_mt
->format
== dst_mt
->format
&&
313 (dst_format
== MESA_FORMAT_L_FLOAT32
||
314 dst_format
== MESA_FORMAT_I_FLOAT32
)) {
315 src_format
= dst_format
= MESA_FORMAT_R_FLOAT32
;
318 enum isl_format src_isl_format
=
319 brw_blorp_to_isl_format(brw
, src_format
, false);
320 enum isl_aux_usage src_aux_usage
=
321 intel_miptree_texture_aux_usage(brw
, src_mt
, src_isl_format
);
322 /* We do format workarounds for some depth formats so we can't reliably
323 * sample with HiZ. One of these days, we should fix that.
325 if (src_aux_usage
== ISL_AUX_USAGE_HIZ
)
326 src_aux_usage
= ISL_AUX_USAGE_NONE
;
327 const bool src_clear_supported
=
328 src_aux_usage
!= ISL_AUX_USAGE_NONE
&& src_mt
->format
== src_format
;
329 intel_miptree_prepare_access(brw
, src_mt
, src_level
, 1, src_layer
, 1,
330 src_aux_usage
, src_clear_supported
);
332 enum isl_format dst_isl_format
=
333 brw_blorp_to_isl_format(brw
, dst_format
, true);
334 enum isl_aux_usage dst_aux_usage
=
335 intel_miptree_render_aux_usage(brw
, dst_mt
, dst_isl_format
, false);
336 const bool dst_clear_supported
= dst_aux_usage
!= ISL_AUX_USAGE_NONE
;
337 intel_miptree_prepare_access(brw
, dst_mt
, dst_level
, 1, dst_layer
, 1,
338 dst_aux_usage
, dst_clear_supported
);
340 struct isl_surf tmp_surfs
[2];
341 struct blorp_surf src_surf
, dst_surf
;
342 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, src_aux_usage
, false,
343 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
344 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, dst_aux_usage
, true,
345 &dst_level
, dst_layer
, 1, &tmp_surfs
[1]);
347 struct isl_swizzle src_isl_swizzle
= {
348 .r
= swizzle_to_scs(GET_SWZ(src_swizzle
, 0)),
349 .g
= swizzle_to_scs(GET_SWZ(src_swizzle
, 1)),
350 .b
= swizzle_to_scs(GET_SWZ(src_swizzle
, 2)),
351 .a
= swizzle_to_scs(GET_SWZ(src_swizzle
, 3)),
354 struct blorp_batch batch
;
355 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
356 blorp_blit(&batch
, &src_surf
, src_level
, src_layer
,
357 src_isl_format
, src_isl_swizzle
,
358 &dst_surf
, dst_level
, dst_layer
,
359 dst_isl_format
, ISL_SWIZZLE_IDENTITY
,
360 src_x0
, src_y0
, src_x1
, src_y1
,
361 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
362 filter
, mirror_x
, mirror_y
);
363 blorp_batch_finish(&batch
);
365 intel_miptree_finish_write(brw
, dst_mt
, dst_level
, dst_layer
, 1,
370 brw_blorp_copy_miptrees(struct brw_context
*brw
,
371 struct intel_mipmap_tree
*src_mt
,
372 unsigned src_level
, unsigned src_layer
,
373 struct intel_mipmap_tree
*dst_mt
,
374 unsigned dst_level
, unsigned dst_layer
,
375 unsigned src_x
, unsigned src_y
,
376 unsigned dst_x
, unsigned dst_y
,
377 unsigned src_width
, unsigned src_height
)
379 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
381 DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
382 "to %dx %s mt %p %d %d (%d,%d)\n",
384 src_mt
->surf
.samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
385 src_level
, src_layer
, src_x
, src_y
, src_width
, src_height
,
386 dst_mt
->surf
.samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
387 dst_level
, dst_layer
, dst_x
, dst_y
);
389 enum isl_aux_usage src_aux_usage
, dst_aux_usage
;
390 bool src_clear_supported
, dst_clear_supported
;
392 switch (src_mt
->aux_usage
) {
393 case ISL_AUX_USAGE_MCS
:
394 case ISL_AUX_USAGE_CCS_E
:
395 src_aux_usage
= src_mt
->aux_usage
;
396 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
397 * we're going to re-interpret the format as an integer format possibly
398 * with a different number of components, we can't handle clear colors
401 src_clear_supported
= devinfo
->gen
>= 9;
404 src_aux_usage
= ISL_AUX_USAGE_NONE
;
405 src_clear_supported
= false;
409 switch (dst_mt
->aux_usage
) {
410 case ISL_AUX_USAGE_MCS
:
411 case ISL_AUX_USAGE_CCS_E
:
412 dst_aux_usage
= dst_mt
->aux_usage
;
413 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
414 * we're going to re-interpret the format as an integer format possibly
415 * with a different number of components, we can't handle clear colors
418 dst_clear_supported
= devinfo
->gen
>= 9;
421 dst_aux_usage
= ISL_AUX_USAGE_NONE
;
422 dst_clear_supported
= false;
426 intel_miptree_prepare_access(brw
, src_mt
, src_level
, 1, src_layer
, 1,
427 src_aux_usage
, src_clear_supported
);
428 intel_miptree_prepare_access(brw
, dst_mt
, dst_level
, 1, dst_layer
, 1,
429 dst_aux_usage
, dst_clear_supported
);
431 struct isl_surf tmp_surfs
[2];
432 struct blorp_surf src_surf
, dst_surf
;
433 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, src_aux_usage
, false,
434 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
435 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, dst_aux_usage
, true,
436 &dst_level
, dst_layer
, 1, &tmp_surfs
[1]);
438 struct blorp_batch batch
;
439 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
440 blorp_copy(&batch
, &src_surf
, src_level
, src_layer
,
441 &dst_surf
, dst_level
, dst_layer
,
442 src_x
, src_y
, dst_x
, dst_y
, src_width
, src_height
);
443 blorp_batch_finish(&batch
);
445 intel_miptree_finish_write(brw
, dst_mt
, dst_level
, dst_layer
, 1,
450 brw_blorp_copy_buffers(struct brw_context
*brw
,
451 struct brw_bo
*src_bo
,
453 struct brw_bo
*dst_bo
,
457 DBG("%s %d bytes from %p[%d] to %p[%d]",
458 __func__
, size
, src_bo
, src_offset
, dst_bo
, dst_offset
);
460 struct blorp_batch batch
;
461 struct blorp_address src
= { .buffer
= src_bo
, .offset
= src_offset
};
462 struct blorp_address dst
= { .buffer
= dst_bo
, .offset
= dst_offset
};
464 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
465 blorp_buffer_copy(&batch
, src
, dst
, size
);
466 blorp_batch_finish(&batch
);
470 static struct intel_mipmap_tree
*
471 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
473 struct intel_mipmap_tree
*mt
= irb
->mt
;
474 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
480 blorp_get_texture_swizzle(const struct intel_renderbuffer
*irb
)
482 return irb
->Base
.Base
._BaseFormat
== GL_RGB
?
483 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ONE
) :
488 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
489 struct intel_renderbuffer
*src_irb
, mesa_format src_format
,
490 struct intel_renderbuffer
*dst_irb
, mesa_format dst_format
,
491 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
492 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
493 GLenum filter
, bool mirror_x
, bool mirror_y
)
495 const struct gl_context
*ctx
= &brw
->ctx
;
497 /* Find source/dst miptrees */
498 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
499 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
501 const bool do_srgb
= ctx
->Color
.sRGBEnabled
;
504 brw_blorp_blit_miptrees(brw
,
505 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
506 src_format
, blorp_get_texture_swizzle(src_irb
),
507 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
509 srcX0
, srcY0
, srcX1
, srcY1
,
510 dstX0
, dstY0
, dstX1
, dstY1
,
511 filter
, mirror_x
, mirror_y
,
514 dst_irb
->need_downsample
= true;
518 try_blorp_blit(struct brw_context
*brw
,
519 const struct gl_framebuffer
*read_fb
,
520 const struct gl_framebuffer
*draw_fb
,
521 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
522 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
523 GLenum filter
, GLbitfield buffer_bit
)
525 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
526 struct gl_context
*ctx
= &brw
->ctx
;
528 /* Sync up the state of window system buffers. We need to do this before
529 * we go looking for the buffers.
531 intel_prepare_render(brw
);
533 bool mirror_x
, mirror_y
;
534 if (brw_meta_mirror_clip_and_scissor(ctx
, read_fb
, draw_fb
,
535 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
536 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
537 &mirror_x
, &mirror_y
))
541 struct intel_renderbuffer
*src_irb
;
542 struct intel_renderbuffer
*dst_irb
;
543 struct intel_mipmap_tree
*src_mt
;
544 struct intel_mipmap_tree
*dst_mt
;
545 switch (buffer_bit
) {
546 case GL_COLOR_BUFFER_BIT
:
547 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
548 for (unsigned i
= 0; i
< draw_fb
->_NumColorDrawBuffers
; ++i
) {
549 dst_irb
= intel_renderbuffer(draw_fb
->_ColorDrawBuffers
[i
]);
551 do_blorp_blit(brw
, buffer_bit
,
552 src_irb
, src_irb
->Base
.Base
.Format
,
553 dst_irb
, dst_irb
->Base
.Base
.Format
,
554 srcX0
, srcY0
, srcX1
, srcY1
,
555 dstX0
, dstY0
, dstX1
, dstY1
,
556 filter
, mirror_x
, mirror_y
);
559 case GL_DEPTH_BUFFER_BIT
:
561 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
563 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
564 src_mt
= find_miptree(buffer_bit
, src_irb
);
565 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
567 /* We can't handle format conversions between Z24 and other formats
568 * since we have to lie about the surface format. See the comments in
569 * brw_blorp_surface_info::set().
571 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
572 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
))
575 /* We also can't handle any combined depth-stencil formats because we
576 * have to reinterpret as a color format.
578 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
579 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
582 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
583 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
584 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
585 filter
, mirror_x
, mirror_y
);
587 case GL_STENCIL_BUFFER_BIT
:
588 /* Blorp doesn't support combined depth stencil which is all we have
591 if (devinfo
->gen
< 6)
595 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
597 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
598 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
599 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
600 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
601 filter
, mirror_x
, mirror_y
);
604 unreachable("not reached");
611 apply_y_flip(int *y0
, int *y1
, int height
)
613 int tmp
= height
- *y0
;
619 brw_blorp_copytexsubimage(struct brw_context
*brw
,
620 struct gl_renderbuffer
*src_rb
,
621 struct gl_texture_image
*dst_image
,
623 int srcX0
, int srcY0
,
624 int dstX0
, int dstY0
,
625 int width
, int height
)
627 struct gl_context
*ctx
= &brw
->ctx
;
628 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
629 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
631 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
632 if (brw
->ctx
._ImageTransferState
)
635 /* Sync up the state of window system buffers. We need to do this before
636 * we go looking at the src renderbuffer's miptree.
638 intel_prepare_render(brw
);
640 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
641 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
643 /* There is support for only up to eight samples. */
644 if (src_mt
->surf
.samples
> 8 || dst_mt
->surf
.samples
> 8)
647 if (_mesa_get_format_base_format(src_rb
->Format
) !=
648 _mesa_get_format_base_format(dst_image
->TexFormat
)) {
652 /* We can't handle format conversions between Z24 and other formats since
653 * we have to lie about the surface format. See the comments in
654 * brw_blorp_surface_info::set().
656 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
657 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
)) {
661 /* We also can't handle any combined depth-stencil formats because we
662 * have to reinterpret as a color format.
664 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
665 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
668 if (!brw
->mesa_format_supports_render
[dst_image
->TexFormat
])
671 /* Source clipping shouldn't be necessary, since copytexsubimage (in
672 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
675 * Destination clipping shouldn't be necessary since the restrictions on
676 * glCopyTexSubImage prevent the user from specifying a destination rectangle
677 * that falls outside the bounds of the destination texture.
678 * See error_check_subtexture_dimensions().
681 int srcY1
= srcY0
+ height
;
682 int srcX1
= srcX0
+ width
;
683 int dstX1
= dstX0
+ width
;
684 int dstY1
= dstY0
+ height
;
686 /* Account for the fact that in the system framebuffer, the origin is at
689 bool mirror_y
= _mesa_is_winsys_fbo(ctx
->ReadBuffer
);
691 apply_y_flip(&srcY0
, &srcY1
, src_rb
->Height
);
693 /* Account for face selection and texture view MinLayer */
694 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
695 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
697 brw_blorp_blit_miptrees(brw
,
698 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
699 src_rb
->Format
, blorp_get_texture_swizzle(src_irb
),
700 dst_mt
, dst_level
, dst_slice
,
701 dst_image
->TexFormat
,
702 srcX0
, srcY0
, srcX1
, srcY1
,
703 dstX0
, dstY0
, dstX1
, dstY1
,
704 GL_NEAREST
, false, mirror_y
,
707 /* If we're copying to a packed depth stencil texture and the source
708 * framebuffer has separate stencil, we need to also copy the stencil data
711 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
712 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
714 src_irb
= intel_renderbuffer(src_rb
);
715 src_mt
= src_irb
->mt
;
717 if (src_mt
->stencil_mt
)
718 src_mt
= src_mt
->stencil_mt
;
719 if (dst_mt
->stencil_mt
)
720 dst_mt
= dst_mt
->stencil_mt
;
722 if (src_mt
!= dst_mt
) {
723 brw_blorp_blit_miptrees(brw
,
724 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
726 blorp_get_texture_swizzle(src_irb
),
727 dst_mt
, dst_level
, dst_slice
,
729 srcX0
, srcY0
, srcX1
, srcY1
,
730 dstX0
, dstY0
, dstX1
, dstY1
,
731 GL_NEAREST
, false, mirror_y
,
741 brw_blorp_framebuffer(struct brw_context
*brw
,
742 struct gl_framebuffer
*readFb
,
743 struct gl_framebuffer
*drawFb
,
744 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
745 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
746 GLbitfield mask
, GLenum filter
)
748 static GLbitfield buffer_bits
[] = {
751 GL_STENCIL_BUFFER_BIT
,
754 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
755 if ((mask
& buffer_bits
[i
]) &&
756 try_blorp_blit(brw
, readFb
, drawFb
,
757 srcX0
, srcY0
, srcX1
, srcY1
,
758 dstX0
, dstY0
, dstX1
, dstY1
,
759 filter
, buffer_bits
[i
])) {
760 mask
&= ~buffer_bits
[i
];
767 static struct brw_bo
*
768 blorp_get_client_bo(struct brw_context
*brw
,
769 unsigned w
, unsigned h
, unsigned d
,
770 GLenum target
, GLenum format
, GLenum type
,
772 const struct gl_pixelstore_attrib
*packing
,
773 uint32_t *offset_out
, uint32_t *row_stride_out
,
774 uint32_t *image_stride_out
, bool read_only
)
776 /* Account for SKIP_PIXELS, SKIP_ROWS, ALIGNMENT, and SKIP_IMAGES */
777 const GLuint dims
= _mesa_get_texture_dimensions(target
);
778 const uint32_t first_pixel
= _mesa_image_offset(dims
, packing
, w
, h
,
779 format
, type
, 0, 0, 0);
780 const uint32_t last_pixel
= _mesa_image_offset(dims
, packing
, w
, h
,
783 const uint32_t stride
= _mesa_image_row_stride(packing
, w
, format
, type
);
784 const uint32_t cpp
= _mesa_bytes_per_pixel(format
, type
);
785 const uint32_t size
= last_pixel
- first_pixel
;
787 *row_stride_out
= stride
;
788 *image_stride_out
= _mesa_image_image_stride(packing
, w
, h
, format
, type
);
790 if (_mesa_is_bufferobj(packing
->BufferObj
)) {
791 const uint32_t offset
= first_pixel
+ (intptr_t)pixels
;
792 if (!read_only
&& ((offset
% cpp
) || (stride
% cpp
))) {
793 perf_debug("Bad PBO alignment; fallback to CPU mapping\n");
797 /* This is a user-provided PBO. We just need to get the BO out */
798 struct intel_buffer_object
*intel_pbo
=
799 intel_buffer_object(packing
->BufferObj
);
801 intel_bufferobj_buffer(brw
, intel_pbo
, offset
, size
, !read_only
);
803 /* We take a reference to the BO so that the caller can just always
804 * unref without having to worry about whether it's a user PBO or one
807 brw_bo_reference(bo
);
809 *offset_out
= offset
;
812 /* Someone should have already checked that there is data to upload. */
815 /* Creating a temp buffer currently only works for upload */
818 /* This is not a user-provided PBO. Instead, pixels is a pointer to CPU
819 * data which we need to copy into a BO.
822 brw_bo_alloc(brw
->bufmgr
, "tmp_tex_subimage_src", size
, 64);
824 perf_debug("intel_texsubimage: temp bo creation failed: size = %u\n",
829 if (brw_bo_subdata(bo
, 0, size
, pixels
+ first_pixel
)) {
830 perf_debug("intel_texsubimage: temp bo upload failed\n");
831 brw_bo_unreference(bo
);
840 /* Consider all the restrictions and determine the format of the source. */
842 blorp_get_client_format(struct brw_context
*brw
,
843 GLenum format
, GLenum type
,
844 const struct gl_pixelstore_attrib
*packing
)
846 if (brw
->ctx
._ImageTransferState
)
847 return MESA_FORMAT_NONE
;
849 if (packing
->SwapBytes
|| packing
->LsbFirst
|| packing
->Invert
) {
850 perf_debug("intel_texsubimage_blorp: unsupported gl_pixelstore_attrib\n");
851 return MESA_FORMAT_NONE
;
854 if (format
!= GL_RED
&&
860 format
!= GL_ALPHA
&&
861 format
!= GL_RED_INTEGER
&&
862 format
!= GL_RG_INTEGER
&&
863 format
!= GL_RGB_INTEGER
&&
864 format
!= GL_BGR_INTEGER
&&
865 format
!= GL_RGBA_INTEGER
&&
866 format
!= GL_BGRA_INTEGER
) {
867 perf_debug("intel_texsubimage_blorp: %s not supported",
868 _mesa_enum_to_string(format
));
869 return MESA_FORMAT_NONE
;
872 return _mesa_tex_format_from_format_and_type(&brw
->ctx
, format
, type
);
876 need_signed_unsigned_int_conversion(mesa_format src_format
,
877 mesa_format dst_format
)
879 const GLenum src_type
= _mesa_get_format_datatype(src_format
);
880 const GLenum dst_type
= _mesa_get_format_datatype(dst_format
);
881 return (src_type
== GL_INT
&& dst_type
== GL_UNSIGNED_INT
) ||
882 (src_type
== GL_UNSIGNED_INT
&& dst_type
== GL_INT
);
886 brw_blorp_upload_miptree(struct brw_context
*brw
,
887 struct intel_mipmap_tree
*dst_mt
,
888 mesa_format dst_format
,
889 uint32_t level
, uint32_t x
, uint32_t y
, uint32_t z
,
890 uint32_t width
, uint32_t height
, uint32_t depth
,
891 GLenum target
, GLenum format
, GLenum type
,
893 const struct gl_pixelstore_attrib
*packing
)
895 const mesa_format src_format
=
896 blorp_get_client_format(brw
, format
, type
, packing
);
897 if (src_format
== MESA_FORMAT_NONE
)
900 if (!brw
->mesa_format_supports_render
[dst_format
]) {
901 perf_debug("intel_texsubimage: can't use %s as render target\n",
902 _mesa_get_format_name(dst_format
));
906 /* This function relies on blorp_blit to upload the pixel data to the
907 * miptree. But, blorp_blit doesn't support signed to unsigned or
908 * unsigned to signed integer conversions.
910 if (need_signed_unsigned_int_conversion(src_format
, dst_format
))
913 uint32_t src_offset
, src_row_stride
, src_image_stride
;
914 struct brw_bo
*src_bo
=
915 blorp_get_client_bo(brw
, width
, height
, depth
,
916 target
, format
, type
, pixels
, packing
,
917 &src_offset
, &src_row_stride
,
918 &src_image_stride
, true);
922 /* Now that source is offset to correct starting point, adjust the
923 * given dimensions to treat 1D arrays as 2D.
925 if (target
== GL_TEXTURE_1D_ARRAY
) {
932 src_image_stride
= src_row_stride
;
935 intel_miptree_check_level_layer(dst_mt
, level
, z
+ depth
- 1);
939 /* Blit slice-by-slice creating a single-slice miptree for each layer. Even
940 * in case of linear buffers hardware wants image arrays to be aligned by
941 * four rows. This way hardware only gets one image at a time and any
942 * source alignment will do.
944 for (unsigned i
= 0; i
< depth
; ++i
) {
945 struct intel_mipmap_tree
*src_mt
= intel_miptree_create_for_bo(
946 brw
, src_bo
, src_format
,
947 src_offset
+ i
* src_image_stride
,
952 perf_debug("intel_texsubimage: miptree creation for src failed\n");
956 /* In case exact match is needed, copy using equivalent UINT formats
957 * preventing hardware from changing presentation for SNORM -1.
959 if (src_mt
->format
== dst_format
) {
960 brw_blorp_copy_miptrees(brw
, src_mt
, 0, 0,
961 dst_mt
, level
, z
+ i
,
962 0, 0, x
, y
, width
, height
);
964 brw_blorp_blit_miptrees(brw
, src_mt
, 0, 0,
965 src_format
, SWIZZLE_XYZW
,
966 dst_mt
, level
, z
+ i
,
969 x
, y
, x
+ width
, y
+ height
,
970 GL_NEAREST
, false, false, false, false);
973 intel_miptree_release(&src_mt
);
979 brw_bo_unreference(src_bo
);
985 brw_blorp_download_miptree(struct brw_context
*brw
,
986 struct intel_mipmap_tree
*src_mt
,
987 mesa_format src_format
, uint32_t src_swizzle
,
988 uint32_t level
, uint32_t x
, uint32_t y
, uint32_t z
,
989 uint32_t width
, uint32_t height
, uint32_t depth
,
990 GLenum target
, GLenum format
, GLenum type
,
991 bool y_flip
, const void *pixels
,
992 const struct gl_pixelstore_attrib
*packing
)
994 const mesa_format dst_format
=
995 blorp_get_client_format(brw
, format
, type
, packing
);
996 if (dst_format
== MESA_FORMAT_NONE
)
999 if (!brw
->mesa_format_supports_render
[dst_format
]) {
1000 perf_debug("intel_texsubimage: can't use %s as render target\n",
1001 _mesa_get_format_name(dst_format
));
1005 /* This function relies on blorp_blit to download the pixel data from the
1006 * miptree. But, blorp_blit doesn't support signed to unsigned or unsigned
1007 * to signed integer conversions.
1009 if (need_signed_unsigned_int_conversion(src_format
, dst_format
))
1012 /* We can't fetch from LUMINANCE or intensity as that would require a
1013 * non-trivial swizzle.
1015 switch (_mesa_get_format_base_format(src_format
)) {
1017 case GL_LUMINANCE_ALPHA
:
1024 /* This pass only works for PBOs */
1025 assert(_mesa_is_bufferobj(packing
->BufferObj
));
1027 uint32_t dst_offset
, dst_row_stride
, dst_image_stride
;
1028 struct brw_bo
*dst_bo
=
1029 blorp_get_client_bo(brw
, width
, height
, depth
,
1030 target
, format
, type
, pixels
, packing
,
1031 &dst_offset
, &dst_row_stride
,
1032 &dst_image_stride
, false);
1036 /* Now that source is offset to correct starting point, adjust the
1037 * given dimensions to treat 1D arrays as 2D.
1039 if (target
== GL_TEXTURE_1D_ARRAY
) {
1046 dst_image_stride
= dst_row_stride
;
1049 intel_miptree_check_level_layer(src_mt
, level
, z
+ depth
- 1);
1052 int y1
= y
+ height
;
1054 apply_y_flip(&y0
, &y1
, minify(src_mt
->surf
.phys_level0_sa
.height
,
1055 level
- src_mt
->first_level
));
1058 bool result
= false;
1060 /* Blit slice-by-slice creating a single-slice miptree for each layer. Even
1061 * in case of linear buffers hardware wants image arrays to be aligned by
1062 * four rows. This way hardware only gets one image at a time and any
1063 * source alignment will do.
1065 for (unsigned i
= 0; i
< depth
; ++i
) {
1066 struct intel_mipmap_tree
*dst_mt
= intel_miptree_create_for_bo(
1067 brw
, dst_bo
, dst_format
,
1068 dst_offset
+ i
* dst_image_stride
,
1073 perf_debug("intel_texsubimage: miptree creation for src failed\n");
1077 /* In case exact match is needed, copy using equivalent UINT formats
1078 * preventing hardware from changing presentation for SNORM -1.
1080 if (dst_mt
->format
== src_format
&& !y_flip
&&
1081 src_swizzle
== SWIZZLE_XYZW
) {
1082 brw_blorp_copy_miptrees(brw
, src_mt
, level
, z
+ i
,
1084 x
, y
, 0, 0, width
, height
);
1086 brw_blorp_blit_miptrees(brw
, src_mt
, level
, z
+ i
,
1087 src_format
, src_swizzle
,
1088 dst_mt
, 0, 0, dst_format
,
1089 x
, y0
, x
+ width
, y1
,
1090 0, 0, width
, height
,
1091 GL_NEAREST
, false, y_flip
, false, false);
1094 intel_miptree_release(&dst_mt
);
1099 /* As we implement PBO transfers by binding the user-provided BO as a
1100 * fake framebuffer and rendering to it. This breaks the invariant of the
1101 * GL that nothing is able to render to a BO, causing nondeterministic
1102 * corruption issues because the render cache is not coherent with a
1103 * number of other caches that the BO could potentially be bound to
1106 * This could be solved in the same way that we guarantee texture
1107 * coherency after a texture is attached to a framebuffer and
1108 * rendered to, but that would involve checking *all* BOs bound to
1109 * the pipeline for the case we need to emit a cache flush due to
1110 * previous rendering to any of them -- Including vertex, index,
1111 * uniform, atomic counter, shader image, transform feedback,
1112 * indirect draw buffers, etc.
1114 * That would increase the per-draw call overhead even though it's
1115 * very unlikely that any of the BOs bound to the pipeline has been
1116 * rendered to via a PBO at any point, so it seems better to just
1117 * flush here unconditionally.
1119 brw_emit_mi_flush(brw
);
1122 brw_bo_unreference(dst_bo
);
1128 set_write_disables(const struct intel_renderbuffer
*irb
,
1129 const GLubyte
*color_mask
, bool *color_write_disable
)
1131 /* Format information in the renderbuffer represents the requirements
1132 * given by the client. There are cases where the backing miptree uses,
1133 * for example, RGBA to represent RGBX. Since the client is only expecting
1134 * RGB we can treat alpha as not used and write whatever we like into it.
1136 const GLenum base_format
= irb
->Base
.Base
._BaseFormat
;
1137 const int components
= _mesa_base_format_component_count(base_format
);
1138 bool disables
= false;
1140 assert(components
> 0);
1142 for (int i
= 0; i
< components
; i
++) {
1143 color_write_disable
[i
] = !color_mask
[i
];
1144 disables
= disables
|| !color_mask
[i
];
1151 do_single_blorp_clear(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
1152 struct gl_renderbuffer
*rb
, unsigned buf
,
1153 bool partial_clear
, bool encode_srgb
)
1155 struct gl_context
*ctx
= &brw
->ctx
;
1156 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
1157 uint32_t x0
, x1
, y0
, y1
;
1159 mesa_format format
= irb
->Base
.Base
.Format
;
1160 if (!encode_srgb
&& _mesa_get_format_color_encoding(format
) == GL_SRGB
)
1161 format
= _mesa_get_srgb_format_linear(format
);
1162 enum isl_format isl_format
= brw
->mesa_to_isl_render_format
[format
];
1166 if (rb
->Name
!= 0) {
1170 y0
= rb
->Height
- fb
->_Ymax
;
1171 y1
= rb
->Height
- fb
->_Ymin
;
1174 /* If the clear region is empty, just return. */
1175 if (x0
== x1
|| y0
== y1
)
1178 bool can_fast_clear
= !partial_clear
;
1180 bool color_write_disable
[4] = { false, false, false, false };
1181 if (set_write_disables(irb
, ctx
->Color
.ColorMask
[buf
], color_write_disable
))
1182 can_fast_clear
= false;
1184 /* We store clear colors as floats or uints as needed. If there are
1185 * texture views in play, the formats will not properly be respected
1186 * during resolves because the resolve operations only know about the
1187 * miptree and not the renderbuffer.
1189 if (irb
->Base
.Base
.Format
!= irb
->mt
->format
)
1190 can_fast_clear
= false;
1192 if (!irb
->mt
->supports_fast_clear
||
1193 !brw_is_color_fast_clear_compatible(brw
, irb
->mt
, &ctx
->Color
.ClearColor
))
1194 can_fast_clear
= false;
1196 /* Surface state can only record one fast clear color value. Therefore
1197 * unless different levels/layers agree on the color it can be used to
1198 * represent only single level/layer. Here it will be reserved for the
1199 * first slice (level 0, layer 0).
1201 if (irb
->layer_count
> 1 || irb
->mt_level
|| irb
->mt_layer
)
1202 can_fast_clear
= false;
1204 unsigned level
= irb
->mt_level
;
1205 const unsigned num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1207 /* If the MCS buffer hasn't been allocated yet, we need to allocate it now.
1209 if (can_fast_clear
&& !irb
->mt
->mcs_buf
) {
1210 assert(irb
->mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1211 if (!intel_miptree_alloc_ccs(brw
, irb
->mt
)) {
1212 /* There are a few reasons in addition to out-of-memory, that can
1213 * cause intel_miptree_alloc_non_msrt_mcs to fail. Try to recover by
1214 * falling back to non-fast clear.
1216 can_fast_clear
= false;
1220 if (can_fast_clear
) {
1221 const enum isl_aux_state aux_state
=
1222 intel_miptree_get_aux_state(irb
->mt
, irb
->mt_level
, irb
->mt_layer
);
1223 union isl_color_value clear_color
=
1224 brw_meta_convert_fast_clear_color(brw
, irb
->mt
,
1225 &ctx
->Color
.ClearColor
);
1227 bool same_clear_color
=
1228 !intel_miptree_set_clear_color(ctx
, irb
->mt
, clear_color
);
1230 /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
1231 * is redundant and can be skipped.
1233 if (aux_state
== ISL_AUX_STATE_CLEAR
&& same_clear_color
)
1236 DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__
,
1237 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
1239 /* We can't setup the blorp_surf until we've allocated the MCS above */
1240 struct isl_surf isl_tmp
[2];
1241 struct blorp_surf surf
;
1242 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, irb
->mt
->aux_usage
, true,
1243 &level
, irb
->mt_layer
, num_layers
, isl_tmp
);
1245 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1247 * "Any transition from any value in {Clear, Render, Resolve} to a
1248 * different value in {Clear, Render, Resolve} requires end of pipe
1251 * In other words, fast clear ops are not properly synchronized with
1252 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1253 * contents of the previous draw hit the render target before we resolve
1254 * and again afterwards to ensure that the resolve is complete before we
1255 * do any more regular drawing.
1257 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1259 struct blorp_batch batch
;
1260 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1261 blorp_fast_clear(&batch
, &surf
, isl_format
,
1262 level
, irb
->mt_layer
, num_layers
,
1264 blorp_batch_finish(&batch
);
1266 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1268 /* Now that the fast clear has occurred, put the buffer in
1269 * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
1272 intel_miptree_set_aux_state(brw
, irb
->mt
, irb
->mt_level
,
1273 irb
->mt_layer
, num_layers
,
1274 ISL_AUX_STATE_CLEAR
);
1276 DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__
,
1277 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
1279 enum isl_aux_usage aux_usage
=
1280 intel_miptree_render_aux_usage(brw
, irb
->mt
, isl_format
, false);
1281 intel_miptree_prepare_render(brw
, irb
->mt
, level
, irb
->mt_layer
,
1282 num_layers
, isl_format
, false);
1284 struct isl_surf isl_tmp
[2];
1285 struct blorp_surf surf
;
1286 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, aux_usage
, true,
1287 &level
, irb
->mt_layer
, num_layers
, isl_tmp
);
1289 union isl_color_value clear_color
;
1290 memcpy(clear_color
.f32
, ctx
->Color
.ClearColor
.f
, sizeof(float) * 4);
1292 struct blorp_batch batch
;
1293 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1294 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
1295 level
, irb
->mt_layer
, num_layers
,
1297 clear_color
, color_write_disable
);
1298 blorp_batch_finish(&batch
);
1300 intel_miptree_finish_render(brw
, irb
->mt
, level
, irb
->mt_layer
,
1301 num_layers
, isl_format
, false);
1308 brw_blorp_clear_color(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
1309 GLbitfield mask
, bool partial_clear
, bool encode_srgb
)
1311 for (unsigned buf
= 0; buf
< fb
->_NumColorDrawBuffers
; buf
++) {
1312 struct gl_renderbuffer
*rb
= fb
->_ColorDrawBuffers
[buf
];
1313 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
1315 /* Only clear the buffers present in the provided mask */
1316 if (((1 << fb
->_ColorDrawBufferIndexes
[buf
]) & mask
) == 0)
1319 /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
1320 * the framebuffer can be complete with some attachments missing. In
1321 * this case the _ColorDrawBuffers pointer will be NULL.
1326 do_single_blorp_clear(brw
, fb
, rb
, buf
, partial_clear
, encode_srgb
);
1327 irb
->need_downsample
= true;
1334 brw_blorp_clear_depth_stencil(struct brw_context
*brw
,
1335 struct gl_framebuffer
*fb
,
1336 GLbitfield mask
, bool partial_clear
)
1338 const struct gl_context
*ctx
= &brw
->ctx
;
1339 struct gl_renderbuffer
*depth_rb
=
1340 fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
;
1341 struct gl_renderbuffer
*stencil_rb
=
1342 fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
1344 if (!depth_rb
|| ctx
->Depth
.Mask
== GL_FALSE
)
1345 mask
&= ~BUFFER_BIT_DEPTH
;
1347 if (!stencil_rb
|| (ctx
->Stencil
.WriteMask
[0] & 0xff) == 0)
1348 mask
&= ~BUFFER_BIT_STENCIL
;
1350 if (!(mask
& (BUFFER_BITS_DEPTH_STENCIL
)))
1353 uint32_t x0
, x1
, y0
, y1
, rb_name
, rb_height
;
1355 rb_name
= depth_rb
->Name
;
1356 rb_height
= depth_rb
->Height
;
1358 assert(depth_rb
->Width
== stencil_rb
->Width
);
1359 assert(depth_rb
->Height
== stencil_rb
->Height
);
1363 rb_name
= stencil_rb
->Name
;
1364 rb_height
= stencil_rb
->Height
;
1373 y0
= rb_height
- fb
->_Ymax
;
1374 y1
= rb_height
- fb
->_Ymin
;
1377 /* If the clear region is empty, just return. */
1378 if (x0
== x1
|| y0
== y1
)
1381 uint32_t level
, start_layer
, num_layers
;
1382 struct isl_surf isl_tmp
[4];
1383 struct blorp_surf depth_surf
, stencil_surf
;
1385 struct intel_mipmap_tree
*depth_mt
= NULL
;
1386 if (mask
& BUFFER_BIT_DEPTH
) {
1387 struct intel_renderbuffer
*irb
= intel_renderbuffer(depth_rb
);
1388 depth_mt
= find_miptree(GL_DEPTH_BUFFER_BIT
, irb
);
1390 level
= irb
->mt_level
;
1391 start_layer
= irb
->mt_layer
;
1392 num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1394 intel_miptree_prepare_depth(brw
, depth_mt
, level
,
1395 start_layer
, num_layers
);
1397 unsigned depth_level
= level
;
1398 blorp_surf_for_miptree(brw
, &depth_surf
, depth_mt
, depth_mt
->aux_usage
,
1399 true, &depth_level
, start_layer
, num_layers
,
1401 assert(depth_level
== level
);
1404 uint8_t stencil_mask
= 0;
1405 struct intel_mipmap_tree
*stencil_mt
= NULL
;
1406 if (mask
& BUFFER_BIT_STENCIL
) {
1407 struct intel_renderbuffer
*irb
= intel_renderbuffer(stencil_rb
);
1408 stencil_mt
= find_miptree(GL_STENCIL_BUFFER_BIT
, irb
);
1410 if (mask
& BUFFER_BIT_DEPTH
) {
1411 assert(level
== irb
->mt_level
);
1412 assert(start_layer
== irb
->mt_layer
);
1413 assert(num_layers
== fb
->MaxNumLayers
? irb
->layer_count
: 1);
1415 level
= irb
->mt_level
;
1416 start_layer
= irb
->mt_layer
;
1417 num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1420 stencil_mask
= ctx
->Stencil
.WriteMask
[0] & 0xff;
1422 intel_miptree_prepare_access(brw
, stencil_mt
, level
, 1,
1423 start_layer
, num_layers
,
1424 ISL_AUX_USAGE_NONE
, false);
1426 unsigned stencil_level
= level
;
1427 blorp_surf_for_miptree(brw
, &stencil_surf
, stencil_mt
,
1428 ISL_AUX_USAGE_NONE
, true,
1429 &stencil_level
, start_layer
, num_layers
,
1433 assert((mask
& BUFFER_BIT_DEPTH
) || stencil_mask
);
1435 struct blorp_batch batch
;
1436 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1437 blorp_clear_depth_stencil(&batch
, &depth_surf
, &stencil_surf
,
1438 level
, start_layer
, num_layers
,
1440 (mask
& BUFFER_BIT_DEPTH
), ctx
->Depth
.Clear
,
1441 stencil_mask
, ctx
->Stencil
.Clear
);
1442 blorp_batch_finish(&batch
);
1444 if (mask
& BUFFER_BIT_DEPTH
) {
1445 intel_miptree_finish_depth(brw
, depth_mt
, level
,
1446 start_layer
, num_layers
, true);
1450 intel_miptree_finish_write(brw
, stencil_mt
, level
,
1451 start_layer
, num_layers
,
1452 ISL_AUX_USAGE_NONE
);
1457 brw_blorp_resolve_color(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1458 unsigned level
, unsigned layer
,
1459 enum blorp_fast_clear_op resolve_op
)
1461 DBG("%s to mt %p level %u layer %u\n", __FUNCTION__
, mt
, level
, layer
);
1463 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
1465 struct isl_surf isl_tmp
[1];
1466 struct blorp_surf surf
;
1467 blorp_surf_for_miptree(brw
, &surf
, mt
, mt
->aux_usage
, true,
1468 &level
, layer
, 1 /* num_layers */,
1471 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1473 * "Any transition from any value in {Clear, Render, Resolve} to a
1474 * different value in {Clear, Render, Resolve} requires end of pipe
1477 * In other words, fast clear ops are not properly synchronized with
1478 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1479 * contents of the previous draw hit the render target before we resolve
1480 * and again afterwards to ensure that the resolve is complete before we
1481 * do any more regular drawing.
1483 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1486 struct blorp_batch batch
;
1487 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1488 blorp_ccs_resolve(&batch
, &surf
, level
, layer
,
1489 brw_blorp_to_isl_format(brw
, format
, true),
1491 blorp_batch_finish(&batch
);
1493 /* See comment above */
1494 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1498 brw_blorp_mcs_partial_resolve(struct brw_context
*brw
,
1499 struct intel_mipmap_tree
*mt
,
1500 uint32_t start_layer
, uint32_t num_layers
)
1502 DBG("%s to mt %p layers %u-%u\n", __FUNCTION__
, mt
,
1503 start_layer
, start_layer
+ num_layers
- 1);
1505 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1507 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
1508 enum isl_format isl_format
= brw_blorp_to_isl_format(brw
, format
, true);
1510 struct isl_surf isl_tmp
[1];
1511 struct blorp_surf surf
;
1513 blorp_surf_for_miptree(brw
, &surf
, mt
, ISL_AUX_USAGE_MCS
, true,
1514 &level
, start_layer
, num_layers
, isl_tmp
);
1516 struct blorp_batch batch
;
1517 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1518 blorp_mcs_partial_resolve(&batch
, &surf
, isl_format
,
1519 start_layer
, num_layers
);
1520 blorp_batch_finish(&batch
);
1524 * Perform a HiZ or depth resolve operation.
1526 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
1527 * PRM, Volume 1, Part 2:
1528 * - 7.5.3.1 Depth Buffer Clear
1529 * - 7.5.3.2 Depth Buffer Resolve
1530 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1533 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1534 unsigned int level
, unsigned int start_layer
,
1535 unsigned int num_layers
, enum blorp_hiz_op op
)
1537 assert(intel_miptree_level_has_hiz(mt
, level
));
1538 assert(op
!= BLORP_HIZ_OP_NONE
);
1539 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1540 const char *opname
= NULL
;
1543 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
1544 opname
= "depth resolve";
1546 case BLORP_HIZ_OP_HIZ_RESOLVE
:
1547 opname
= "hiz ambiguate";
1549 case BLORP_HIZ_OP_DEPTH_CLEAR
:
1550 opname
= "depth clear";
1552 case BLORP_HIZ_OP_NONE
:
1557 DBG("%s %s to mt %p level %d layers %d-%d\n",
1558 __func__
, opname
, mt
, level
, start_layer
, start_layer
+ num_layers
- 1);
1560 /* The following stalls and flushes are only documented to be required for
1561 * HiZ clear operations. However, they also seem to be required for
1562 * resolve operations.
1564 if (devinfo
->gen
== 6) {
1565 /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
1567 * "If other rendering operations have preceded this clear, a
1568 * PIPE_CONTROL with write cache flush enabled and Z-inhibit
1569 * disabled must be issued before the rectangle primitive used for
1570 * the depth buffer clear operation.
1572 brw_emit_pipe_control_flush(brw
,
1573 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1574 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1575 PIPE_CONTROL_CS_STALL
);
1576 } else if (devinfo
->gen
>= 7) {
1578 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
1580 * If other rendering operations have preceded this clear, a
1581 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
1582 * enabled must be issued before the rectangle primitive used for
1583 * the depth buffer clear operation.
1585 * Same applies for Gen8 and Gen9.
1587 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
1588 * PIPE_CONTROL, Depth Cache Flush Enable:
1590 * This bit must not be set when Depth Stall Enable bit is set in
1593 * This is confirmed to hold for real, HSW gets immediate gpu hangs.
1595 * Therefore issue two pipe control flushes, one for cache flush and
1596 * another for depth stall.
1598 brw_emit_pipe_control_flush(brw
,
1599 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1600 PIPE_CONTROL_CS_STALL
);
1602 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
1605 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
&& mt
->hiz_buf
);
1607 struct isl_surf isl_tmp
[2];
1608 struct blorp_surf surf
;
1609 blorp_surf_for_miptree(brw
, &surf
, mt
, ISL_AUX_USAGE_HIZ
, true,
1610 &level
, start_layer
, num_layers
, isl_tmp
);
1612 struct blorp_batch batch
;
1613 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1614 blorp_hiz_op(&batch
, &surf
, level
, start_layer
, num_layers
, op
);
1615 blorp_batch_finish(&batch
);
1617 /* The following stalls and flushes are only documented to be required for
1618 * HiZ clear operations. However, they also seem to be required for
1619 * resolve operations.
1621 if (devinfo
->gen
== 6) {
1622 /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
1624 * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be
1625 * followed by a PIPE_CONTROL command with DEPTH_STALL bit set
1626 * and Then followed by Depth FLUSH'
1628 brw_emit_pipe_control_flush(brw
,
1629 PIPE_CONTROL_DEPTH_STALL
);
1631 brw_emit_pipe_control_flush(brw
,
1632 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1633 PIPE_CONTROL_CS_STALL
);
1634 } else if (devinfo
->gen
>= 8) {
1636 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
1638 * "Depth buffer clear pass using any of the methods (WM_STATE,
1639 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
1640 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
1641 * "set" before starting to render. DepthStall and DepthFlush are
1642 * not needed between consecutive depth clear passes nor is it
1643 * required if the depth clear pass was done with
1644 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
1646 * TODO: Such as the spec says, this could be conditional.
1648 brw_emit_pipe_control_flush(brw
,
1649 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1650 PIPE_CONTROL_DEPTH_STALL
);