2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/blend.h"
27 #include "main/fbobject.h"
28 #include "main/renderbuffer.h"
29 #include "main/glformats.h"
31 #include "brw_blorp.h"
32 #include "brw_context.h"
33 #include "brw_defines.h"
34 #include "brw_meta_util.h"
35 #include "brw_state.h"
36 #include "intel_fbo.h"
37 #include "common/gen_debug.h"
39 #define FILE_DEBUG_FLAG DEBUG_BLORP
42 brw_blorp_lookup_shader(struct blorp_context
*blorp
,
43 const void *key
, uint32_t key_size
,
44 uint32_t *kernel_out
, void *prog_data_out
)
46 struct brw_context
*brw
= blorp
->driver_ctx
;
47 return brw_search_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
,
48 key
, key_size
, kernel_out
, prog_data_out
);
52 brw_blorp_upload_shader(struct blorp_context
*blorp
,
53 const void *key
, uint32_t key_size
,
54 const void *kernel
, uint32_t kernel_size
,
55 const struct brw_stage_prog_data
*prog_data
,
56 uint32_t prog_data_size
,
57 uint32_t *kernel_out
, void *prog_data_out
)
59 struct brw_context
*brw
= blorp
->driver_ctx
;
60 brw_upload_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
, key
, key_size
,
61 kernel
, kernel_size
, prog_data
, prog_data_size
,
62 kernel_out
, prog_data_out
);
67 brw_blorp_init(struct brw_context
*brw
)
69 blorp_init(&brw
->blorp
, brw
, &brw
->isl_dev
);
71 brw
->blorp
.compiler
= brw
->screen
->compiler
;
76 brw
->blorp
.exec
= gen45_blorp_exec
;
78 brw
->blorp
.exec
= gen4_blorp_exec
;
82 brw
->blorp
.exec
= gen5_blorp_exec
;
85 brw
->blorp
.mocs
.tex
= 0;
86 brw
->blorp
.mocs
.rb
= 0;
87 brw
->blorp
.mocs
.vb
= 0;
88 brw
->blorp
.exec
= gen6_blorp_exec
;
91 brw
->blorp
.mocs
.tex
= GEN7_MOCS_L3
;
92 brw
->blorp
.mocs
.rb
= GEN7_MOCS_L3
;
93 brw
->blorp
.mocs
.vb
= GEN7_MOCS_L3
;
94 if (brw
->is_haswell
) {
95 brw
->blorp
.exec
= gen75_blorp_exec
;
97 brw
->blorp
.exec
= gen7_blorp_exec
;
101 brw
->blorp
.mocs
.tex
= BDW_MOCS_WB
;
102 brw
->blorp
.mocs
.rb
= BDW_MOCS_PTE
;
103 brw
->blorp
.mocs
.vb
= BDW_MOCS_WB
;
104 brw
->blorp
.exec
= gen8_blorp_exec
;
107 brw
->blorp
.mocs
.tex
= SKL_MOCS_WB
;
108 brw
->blorp
.mocs
.rb
= SKL_MOCS_PTE
;
109 brw
->blorp
.mocs
.vb
= SKL_MOCS_WB
;
110 brw
->blorp
.exec
= gen9_blorp_exec
;
113 unreachable("Invalid gen");
116 brw
->blorp
.lookup_shader
= brw_blorp_lookup_shader
;
117 brw
->blorp
.upload_shader
= brw_blorp_upload_shader
;
121 blorp_surf_for_miptree(struct brw_context
*brw
,
122 struct blorp_surf
*surf
,
123 struct intel_mipmap_tree
*mt
,
124 bool is_render_target
,
125 uint32_t safe_aux_usage
,
127 unsigned start_layer
, unsigned num_layers
,
128 struct isl_surf tmp_surfs
[2])
130 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
131 mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
132 const unsigned num_samples
= MAX2(1, mt
->num_samples
);
133 for (unsigned i
= 0; i
< num_layers
; i
++) {
134 for (unsigned s
= 0; s
< num_samples
; s
++) {
135 const unsigned phys_layer
= (start_layer
+ i
) * num_samples
+ s
;
136 intel_miptree_check_level_layer(mt
, *level
, phys_layer
);
140 for (unsigned i
= 0; i
< num_layers
; i
++)
141 intel_miptree_check_level_layer(mt
, *level
, start_layer
+ i
);
144 intel_miptree_get_isl_surf(brw
, mt
, &tmp_surfs
[0]);
145 surf
->surf
= &tmp_surfs
[0];
146 surf
->addr
= (struct blorp_address
) {
148 .offset
= mt
->offset
,
149 .read_domains
= is_render_target
? I915_GEM_DOMAIN_RENDER
:
150 I915_GEM_DOMAIN_SAMPLER
,
151 .write_domain
= is_render_target
? I915_GEM_DOMAIN_RENDER
: 0,
154 struct isl_surf
*aux_surf
= &tmp_surfs
[1];
155 intel_miptree_get_aux_isl_surf(brw
, mt
, aux_surf
, &surf
->aux_usage
);
157 if (surf
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
158 if (surf
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
159 /* If we're not going to use it as a depth buffer, resolve HiZ */
160 if (!(safe_aux_usage
& (1 << ISL_AUX_USAGE_HIZ
))) {
161 for (unsigned i
= 0; i
< num_layers
; i
++) {
162 intel_miptree_slice_resolve_depth(brw
, mt
, *level
,
165 /* If we're rendering to it then we'll need a HiZ resolve once
166 * we're done before we can use it with HiZ again.
168 if (is_render_target
)
169 intel_miptree_slice_set_needs_hiz_resolve(mt
, *level
,
172 surf
->aux_usage
= ISL_AUX_USAGE_NONE
;
174 } else if (!(safe_aux_usage
& (1 << surf
->aux_usage
))) {
176 if (safe_aux_usage
& (1 << ISL_AUX_USAGE_CCS_E
))
177 flags
|= INTEL_MIPTREE_IGNORE_CCS_E
;
179 intel_miptree_resolve_color(brw
, mt
,
181 start_layer
, num_layers
, flags
);
183 assert(!intel_miptree_has_color_unresolved(mt
, *level
, 1,
184 start_layer
, num_layers
));
185 surf
->aux_usage
= ISL_AUX_USAGE_NONE
;
189 if (is_render_target
)
190 intel_miptree_used_for_rendering(brw
, mt
, *level
,
191 start_layer
, num_layers
);
193 if (surf
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
194 /* We only really need a clear color if we also have an auxiliary
195 * surface. Without one, it does nothing.
197 surf
->clear_color
= mt
->fast_clear_color
;
199 surf
->aux_surf
= aux_surf
;
200 surf
->aux_addr
= (struct blorp_address
) {
201 .read_domains
= is_render_target
? I915_GEM_DOMAIN_RENDER
:
202 I915_GEM_DOMAIN_SAMPLER
,
203 .write_domain
= is_render_target
? I915_GEM_DOMAIN_RENDER
: 0,
207 surf
->aux_addr
.buffer
= mt
->mcs_buf
->bo
;
208 surf
->aux_addr
.offset
= mt
->mcs_buf
->offset
;
210 assert(surf
->aux_usage
== ISL_AUX_USAGE_HIZ
);
212 surf
->aux_addr
.buffer
= mt
->hiz_buf
->aux_base
.bo
;
213 surf
->aux_addr
.offset
= mt
->hiz_buf
->aux_base
.offset
;
216 surf
->aux_addr
= (struct blorp_address
) {
219 memset(&surf
->clear_color
, 0, sizeof(surf
->clear_color
));
221 assert((surf
->aux_usage
== ISL_AUX_USAGE_NONE
) ==
222 (surf
->aux_addr
.buffer
== NULL
));
224 /* ISL wants real levels, not offset ones. */
225 *level
-= mt
->first_level
;
228 static enum isl_format
229 brw_blorp_to_isl_format(struct brw_context
*brw
, mesa_format format
,
230 bool is_render_target
)
233 case MESA_FORMAT_NONE
:
234 return ISL_FORMAT_UNSUPPORTED
;
235 case MESA_FORMAT_S_UINT8
:
236 return ISL_FORMAT_R8_UINT
;
237 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
238 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
239 return ISL_FORMAT_R24_UNORM_X8_TYPELESS
;
240 case MESA_FORMAT_Z_FLOAT32
:
241 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
242 return ISL_FORMAT_R32_FLOAT
;
243 case MESA_FORMAT_Z_UNORM16
:
244 return ISL_FORMAT_R16_UNORM
;
246 if (is_render_target
) {
247 assert(brw
->format_supported_as_render_target
[format
]);
248 return brw
->render_target_format
[format
];
250 return brw_isl_format_for_mesa_format(format
);
258 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
259 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
261 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
264 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
266 * which is simply adding 4 then modding by 8 (or anding with 7).
268 * We then may need to apply workarounds for textureGather hardware bugs.
270 static enum isl_channel_select
271 swizzle_to_scs(GLenum swizzle
)
273 return (enum isl_channel_select
)((swizzle
+ 4) & 7);
277 physical_to_logical_layer(struct intel_mipmap_tree
*mt
,
278 unsigned physical_layer
)
280 if (mt
->num_samples
> 1 &&
281 (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
282 mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
)) {
283 assert(physical_layer
% mt
->num_samples
== 0);
284 return physical_layer
/ mt
->num_samples
;
286 return physical_layer
;
291 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
292 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
293 * the physical layer holding sample 0. So, for example, if
294 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
298 brw_blorp_blit_miptrees(struct brw_context
*brw
,
299 struct intel_mipmap_tree
*src_mt
,
300 unsigned src_level
, unsigned src_layer
,
301 mesa_format src_format
, int src_swizzle
,
302 struct intel_mipmap_tree
*dst_mt
,
303 unsigned dst_level
, unsigned dst_layer
,
304 mesa_format dst_format
,
305 float src_x0
, float src_y0
,
306 float src_x1
, float src_y1
,
307 float dst_x0
, float dst_y0
,
308 float dst_x1
, float dst_y1
,
309 GLenum filter
, bool mirror_x
, bool mirror_y
,
310 bool decode_srgb
, bool encode_srgb
)
312 /* Blorp operates in logical layers */
313 src_layer
= physical_to_logical_layer(src_mt
, src_layer
);
314 dst_layer
= physical_to_logical_layer(dst_mt
, dst_layer
);
316 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
317 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
319 src_mt
->num_samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
320 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
321 dst_mt
->num_samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
322 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
325 if (!decode_srgb
&& _mesa_get_format_color_encoding(src_format
) == GL_SRGB
)
326 src_format
= _mesa_get_srgb_format_linear(src_format
);
328 if (!encode_srgb
&& _mesa_get_format_color_encoding(dst_format
) == GL_SRGB
)
329 dst_format
= _mesa_get_srgb_format_linear(dst_format
);
331 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
332 * texture, the above code configures the source format for L32_FLOAT or
333 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
334 * the SAMPLE message appears to handle multisampled L32_FLOAT and
335 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
336 * around the problem by using a source format of R32_FLOAT. This
337 * shouldn't affect rendering correctness, since the destination format is
338 * R32_FLOAT, so only the contents of the red channel matters.
341 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1 &&
342 src_mt
->format
== dst_mt
->format
&&
343 (dst_format
== MESA_FORMAT_L_FLOAT32
||
344 dst_format
== MESA_FORMAT_I_FLOAT32
)) {
345 src_format
= dst_format
= MESA_FORMAT_R_FLOAT32
;
348 uint32_t src_usage_flags
= (1 << ISL_AUX_USAGE_MCS
);
349 if (src_format
== src_mt
->format
)
350 src_usage_flags
|= (1 << ISL_AUX_USAGE_CCS_E
);
352 uint32_t dst_usage_flags
= (1 << ISL_AUX_USAGE_MCS
);
353 if (dst_format
== dst_mt
->format
) {
354 dst_usage_flags
|= (1 << ISL_AUX_USAGE_CCS_E
) |
355 (1 << ISL_AUX_USAGE_CCS_D
);
358 struct isl_surf tmp_surfs
[4];
359 struct blorp_surf src_surf
, dst_surf
;
360 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, false, src_usage_flags
,
361 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
362 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, true, dst_usage_flags
,
363 &dst_level
, dst_layer
, 1, &tmp_surfs
[2]);
365 struct isl_swizzle src_isl_swizzle
= {
366 .r
= swizzle_to_scs(GET_SWZ(src_swizzle
, 0)),
367 .g
= swizzle_to_scs(GET_SWZ(src_swizzle
, 1)),
368 .b
= swizzle_to_scs(GET_SWZ(src_swizzle
, 2)),
369 .a
= swizzle_to_scs(GET_SWZ(src_swizzle
, 3)),
372 struct blorp_batch batch
;
373 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
374 blorp_blit(&batch
, &src_surf
, src_level
, src_layer
,
375 brw_blorp_to_isl_format(brw
, src_format
, false), src_isl_swizzle
,
376 &dst_surf
, dst_level
, dst_layer
,
377 brw_blorp_to_isl_format(brw
, dst_format
, true),
378 ISL_SWIZZLE_IDENTITY
,
379 src_x0
, src_y0
, src_x1
, src_y1
,
380 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
381 filter
, mirror_x
, mirror_y
);
382 blorp_batch_finish(&batch
);
386 brw_blorp_copy_miptrees(struct brw_context
*brw
,
387 struct intel_mipmap_tree
*src_mt
,
388 unsigned src_level
, unsigned src_layer
,
389 struct intel_mipmap_tree
*dst_mt
,
390 unsigned dst_level
, unsigned dst_layer
,
391 unsigned src_x
, unsigned src_y
,
392 unsigned dst_x
, unsigned dst_y
,
393 unsigned src_width
, unsigned src_height
)
395 DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
396 "to %dx %s mt %p %d %d (%d,%d)\n",
398 src_mt
->num_samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
399 src_level
, src_layer
, src_x
, src_y
, src_width
, src_height
,
400 dst_mt
->num_samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
401 dst_level
, dst_layer
, dst_x
, dst_y
);
403 struct isl_surf tmp_surfs
[4];
404 struct blorp_surf src_surf
, dst_surf
;
405 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, false,
406 (1 << ISL_AUX_USAGE_MCS
) |
407 (1 << ISL_AUX_USAGE_CCS_E
),
408 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
409 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, true,
410 (1 << ISL_AUX_USAGE_MCS
) |
411 (1 << ISL_AUX_USAGE_CCS_E
),
412 &dst_level
, dst_layer
, 1, &tmp_surfs
[2]);
414 struct blorp_batch batch
;
415 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
416 blorp_copy(&batch
, &src_surf
, src_level
, src_layer
,
417 &dst_surf
, dst_level
, dst_layer
,
418 src_x
, src_y
, dst_x
, dst_y
, src_width
, src_height
);
419 blorp_batch_finish(&batch
);
422 static struct intel_mipmap_tree
*
423 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
425 struct intel_mipmap_tree
*mt
= irb
->mt
;
426 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
432 blorp_get_texture_swizzle(const struct intel_renderbuffer
*irb
)
434 return irb
->Base
.Base
._BaseFormat
== GL_RGB
?
435 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ONE
) :
440 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
441 struct intel_renderbuffer
*src_irb
, mesa_format src_format
,
442 struct intel_renderbuffer
*dst_irb
, mesa_format dst_format
,
443 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
444 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
445 GLenum filter
, bool mirror_x
, bool mirror_y
)
447 const struct gl_context
*ctx
= &brw
->ctx
;
449 /* Find source/dst miptrees */
450 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
451 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
453 const bool do_srgb
= ctx
->Color
.sRGBEnabled
;
456 brw_blorp_blit_miptrees(brw
,
457 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
458 src_format
, blorp_get_texture_swizzle(src_irb
),
459 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
461 srcX0
, srcY0
, srcX1
, srcY1
,
462 dstX0
, dstY0
, dstX1
, dstY1
,
463 filter
, mirror_x
, mirror_y
,
466 dst_irb
->need_downsample
= true;
470 try_blorp_blit(struct brw_context
*brw
,
471 const struct gl_framebuffer
*read_fb
,
472 const struct gl_framebuffer
*draw_fb
,
473 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
474 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
475 GLenum filter
, GLbitfield buffer_bit
)
477 struct gl_context
*ctx
= &brw
->ctx
;
479 /* Sync up the state of window system buffers. We need to do this before
480 * we go looking for the buffers.
482 intel_prepare_render(brw
);
484 bool mirror_x
, mirror_y
;
485 if (brw_meta_mirror_clip_and_scissor(ctx
, read_fb
, draw_fb
,
486 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
487 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
488 &mirror_x
, &mirror_y
))
492 struct intel_renderbuffer
*src_irb
;
493 struct intel_renderbuffer
*dst_irb
;
494 struct intel_mipmap_tree
*src_mt
;
495 struct intel_mipmap_tree
*dst_mt
;
496 switch (buffer_bit
) {
497 case GL_COLOR_BUFFER_BIT
:
498 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
499 for (unsigned i
= 0; i
< draw_fb
->_NumColorDrawBuffers
; ++i
) {
500 dst_irb
= intel_renderbuffer(draw_fb
->_ColorDrawBuffers
[i
]);
502 do_blorp_blit(brw
, buffer_bit
,
503 src_irb
, src_irb
->Base
.Base
.Format
,
504 dst_irb
, dst_irb
->Base
.Base
.Format
,
505 srcX0
, srcY0
, srcX1
, srcY1
,
506 dstX0
, dstY0
, dstX1
, dstY1
,
507 filter
, mirror_x
, mirror_y
);
510 case GL_DEPTH_BUFFER_BIT
:
512 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
514 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
515 src_mt
= find_miptree(buffer_bit
, src_irb
);
516 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
518 /* We can't handle format conversions between Z24 and other formats
519 * since we have to lie about the surface format. See the comments in
520 * brw_blorp_surface_info::set().
522 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
523 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
))
526 /* We also can't handle any combined depth-stencil formats because we
527 * have to reinterpret as a color format.
529 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
530 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
533 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
534 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
535 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
536 filter
, mirror_x
, mirror_y
);
538 case GL_STENCIL_BUFFER_BIT
:
539 /* Blorp doesn't support combined depth stencil which is all we have
546 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
548 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
549 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
550 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
551 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
552 filter
, mirror_x
, mirror_y
);
555 unreachable("not reached");
562 brw_blorp_copytexsubimage(struct brw_context
*brw
,
563 struct gl_renderbuffer
*src_rb
,
564 struct gl_texture_image
*dst_image
,
566 int srcX0
, int srcY0
,
567 int dstX0
, int dstY0
,
568 int width
, int height
)
570 struct gl_context
*ctx
= &brw
->ctx
;
571 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
572 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
574 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
575 if (brw
->ctx
._ImageTransferState
)
578 /* Sync up the state of window system buffers. We need to do this before
579 * we go looking at the src renderbuffer's miptree.
581 intel_prepare_render(brw
);
583 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
584 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
586 /* There is support for only up to eight samples. */
587 if (src_mt
->num_samples
> 8 || dst_mt
->num_samples
> 8)
590 if (_mesa_get_format_base_format(src_rb
->Format
) !=
591 _mesa_get_format_base_format(dst_image
->TexFormat
)) {
595 /* We can't handle format conversions between Z24 and other formats since
596 * we have to lie about the surface format. See the comments in
597 * brw_blorp_surface_info::set().
599 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
600 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
)) {
604 /* We also can't handle any combined depth-stencil formats because we
605 * have to reinterpret as a color format.
607 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
608 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
611 if (!brw
->format_supported_as_render_target
[dst_image
->TexFormat
])
614 /* Source clipping shouldn't be necessary, since copytexsubimage (in
615 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
618 * Destination clipping shouldn't be necessary since the restrictions on
619 * glCopyTexSubImage prevent the user from specifying a destination rectangle
620 * that falls outside the bounds of the destination texture.
621 * See error_check_subtexture_dimensions().
624 int srcY1
= srcY0
+ height
;
625 int srcX1
= srcX0
+ width
;
626 int dstX1
= dstX0
+ width
;
627 int dstY1
= dstY0
+ height
;
629 /* Account for the fact that in the system framebuffer, the origin is at
632 bool mirror_y
= false;
633 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
634 GLint tmp
= src_rb
->Height
- srcY0
;
635 srcY0
= src_rb
->Height
- srcY1
;
640 /* Account for face selection and texture view MinLayer */
641 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
642 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
644 brw_blorp_blit_miptrees(brw
,
645 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
646 src_rb
->Format
, blorp_get_texture_swizzle(src_irb
),
647 dst_mt
, dst_level
, dst_slice
,
648 dst_image
->TexFormat
,
649 srcX0
, srcY0
, srcX1
, srcY1
,
650 dstX0
, dstY0
, dstX1
, dstY1
,
651 GL_NEAREST
, false, mirror_y
,
654 /* If we're copying to a packed depth stencil texture and the source
655 * framebuffer has separate stencil, we need to also copy the stencil data
658 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
659 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
661 src_irb
= intel_renderbuffer(src_rb
);
662 src_mt
= src_irb
->mt
;
664 if (src_mt
->stencil_mt
)
665 src_mt
= src_mt
->stencil_mt
;
666 if (dst_mt
->stencil_mt
)
667 dst_mt
= dst_mt
->stencil_mt
;
669 if (src_mt
!= dst_mt
) {
670 brw_blorp_blit_miptrees(brw
,
671 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
673 blorp_get_texture_swizzle(src_irb
),
674 dst_mt
, dst_level
, dst_slice
,
676 srcX0
, srcY0
, srcX1
, srcY1
,
677 dstX0
, dstY0
, dstX1
, dstY1
,
678 GL_NEAREST
, false, mirror_y
,
688 brw_blorp_framebuffer(struct brw_context
*brw
,
689 struct gl_framebuffer
*readFb
,
690 struct gl_framebuffer
*drawFb
,
691 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
692 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
693 GLbitfield mask
, GLenum filter
)
695 static GLbitfield buffer_bits
[] = {
698 GL_STENCIL_BUFFER_BIT
,
701 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
702 if ((mask
& buffer_bits
[i
]) &&
703 try_blorp_blit(brw
, readFb
, drawFb
,
704 srcX0
, srcY0
, srcX1
, srcY1
,
705 dstX0
, dstY0
, dstX1
, dstY1
,
706 filter
, buffer_bits
[i
])) {
707 mask
&= ~buffer_bits
[i
];
715 set_write_disables(const struct intel_renderbuffer
*irb
,
716 const GLubyte
*color_mask
, bool *color_write_disable
)
718 /* Format information in the renderbuffer represents the requirements
719 * given by the client. There are cases where the backing miptree uses,
720 * for example, RGBA to represent RGBX. Since the client is only expecting
721 * RGB we can treat alpha as not used and write whatever we like into it.
723 const GLenum base_format
= irb
->Base
.Base
._BaseFormat
;
724 const int components
= _mesa_base_format_component_count(base_format
);
725 bool disables
= false;
727 assert(components
> 0);
729 for (int i
= 0; i
< components
; i
++) {
730 color_write_disable
[i
] = !color_mask
[i
];
731 disables
= disables
|| !color_mask
[i
];
738 irb_logical_mt_layer(struct intel_renderbuffer
*irb
)
740 return physical_to_logical_layer(irb
->mt
, irb
->mt_layer
);
744 do_single_blorp_clear(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
745 struct gl_renderbuffer
*rb
, unsigned buf
,
746 bool partial_clear
, bool encode_srgb
)
748 struct gl_context
*ctx
= &brw
->ctx
;
749 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
750 mesa_format format
= irb
->mt
->format
;
751 uint32_t x0
, x1
, y0
, y1
;
753 if (!encode_srgb
&& _mesa_get_format_color_encoding(format
) == GL_SRGB
)
754 format
= _mesa_get_srgb_format_linear(format
);
762 y0
= rb
->Height
- fb
->_Ymax
;
763 y1
= rb
->Height
- fb
->_Ymin
;
766 /* If the clear region is empty, just return. */
767 if (x0
== x1
|| y0
== y1
)
770 bool can_fast_clear
= !partial_clear
;
772 bool color_write_disable
[4] = { false, false, false, false };
773 if (set_write_disables(irb
, ctx
->Color
.ColorMask
[buf
], color_write_disable
))
774 can_fast_clear
= false;
776 if (irb
->mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
||
777 !brw_is_color_fast_clear_compatible(brw
, irb
->mt
, &ctx
->Color
.ClearColor
))
778 can_fast_clear
= false;
780 const unsigned logical_layer
= irb_logical_mt_layer(irb
);
781 const enum intel_fast_clear_state fast_clear_state
=
782 intel_miptree_get_fast_clear_state(irb
->mt
, irb
->mt_level
,
785 /* Surface state can only record one fast clear color value. Therefore
786 * unless different levels/layers agree on the color it can be used to
787 * represent only single level/layer. Here it will be reserved for the
788 * first slice (level 0, layer 0).
790 if (irb
->layer_count
> 1 || irb
->mt_level
|| irb
->mt_layer
)
791 can_fast_clear
= false;
793 if (can_fast_clear
) {
794 union isl_color_value clear_color
=
795 brw_meta_convert_fast_clear_color(brw
, irb
->mt
,
796 &ctx
->Color
.ClearColor
);
798 /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
799 * is redundant and can be skipped.
801 if (fast_clear_state
== INTEL_FAST_CLEAR_STATE_CLEAR
&&
802 memcmp(&irb
->mt
->fast_clear_color
,
803 &clear_color
, sizeof(clear_color
)) == 0)
806 irb
->mt
->fast_clear_color
= clear_color
;
808 /* If the MCS buffer hasn't been allocated yet, we need to allocate
811 if (!irb
->mt
->mcs_buf
) {
812 assert(!intel_miptree_is_lossless_compressed(brw
, irb
->mt
));
813 if (!intel_miptree_alloc_non_msrt_mcs(brw
, irb
->mt
, false)) {
814 /* MCS allocation failed--probably this will only happen in
815 * out-of-memory conditions. But in any case, try to recover
816 * by falling back to a non-blorp clear technique.
823 const unsigned num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
825 /* We can't setup the blorp_surf until we've allocated the MCS above */
826 struct isl_surf isl_tmp
[2];
827 struct blorp_surf surf
;
828 unsigned level
= irb
->mt_level
;
829 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, true,
830 (1 << ISL_AUX_USAGE_MCS
) |
831 (1 << ISL_AUX_USAGE_CCS_E
) |
832 (1 << ISL_AUX_USAGE_CCS_D
),
833 &level
, logical_layer
, num_layers
, isl_tmp
);
835 if (can_fast_clear
) {
836 DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__
,
837 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
839 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
841 * "Any transition from any value in {Clear, Render, Resolve} to a
842 * different value in {Clear, Render, Resolve} requires end of pipe
845 * In other words, fast clear ops are not properly synchronized with
846 * other drawing. We need to use a PIPE_CONTROL to ensure that the
847 * contents of the previous draw hit the render target before we resolve
848 * and again afterwards to ensure that the resolve is complete before we
849 * do any more regular drawing.
851 brw_emit_pipe_control_flush(brw
,
852 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
853 PIPE_CONTROL_CS_STALL
);
855 struct blorp_batch batch
;
856 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
857 blorp_fast_clear(&batch
, &surf
,
858 brw
->render_target_format
[format
],
859 level
, logical_layer
, num_layers
,
861 blorp_batch_finish(&batch
);
863 brw_emit_pipe_control_flush(brw
,
864 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
865 PIPE_CONTROL_CS_STALL
);
867 /* Now that the fast clear has occurred, put the buffer in
868 * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
871 intel_miptree_set_fast_clear_state(brw
, irb
->mt
, irb
->mt_level
,
872 logical_layer
, num_layers
,
873 INTEL_FAST_CLEAR_STATE_CLEAR
);
875 DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__
,
876 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
878 union isl_color_value clear_color
;
879 memcpy(clear_color
.f32
, ctx
->Color
.ClearColor
.f
, sizeof(float) * 4);
881 struct blorp_batch batch
;
882 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
883 blorp_clear(&batch
, &surf
,
884 brw
->render_target_format
[format
],
885 ISL_SWIZZLE_IDENTITY
,
886 level
, irb_logical_mt_layer(irb
), num_layers
,
888 clear_color
, color_write_disable
);
889 blorp_batch_finish(&batch
);
896 brw_blorp_clear_color(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
897 GLbitfield mask
, bool partial_clear
, bool encode_srgb
)
899 for (unsigned buf
= 0; buf
< fb
->_NumColorDrawBuffers
; buf
++) {
900 struct gl_renderbuffer
*rb
= fb
->_ColorDrawBuffers
[buf
];
901 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
903 /* Only clear the buffers present in the provided mask */
904 if (((1 << fb
->_ColorDrawBufferIndexes
[buf
]) & mask
) == 0)
907 /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
908 * the framebuffer can be complete with some attachments missing. In
909 * this case the _ColorDrawBuffers pointer will be NULL.
914 if (!do_single_blorp_clear(brw
, fb
, rb
, buf
, partial_clear
,
919 irb
->need_downsample
= true;
926 brw_blorp_resolve_color(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
927 unsigned level
, unsigned layer
,
928 enum blorp_fast_clear_op resolve_op
)
930 DBG("%s to mt %p level %u layer %u\n", __FUNCTION__
, mt
, level
, layer
);
932 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
934 struct isl_surf isl_tmp
[2];
935 struct blorp_surf surf
;
936 blorp_surf_for_miptree(brw
, &surf
, mt
, true,
937 (1 << ISL_AUX_USAGE_CCS_E
) |
938 (1 << ISL_AUX_USAGE_CCS_D
),
939 &level
, layer
, 1 /* num_layers */,
942 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
944 * "Any transition from any value in {Clear, Render, Resolve} to a
945 * different value in {Clear, Render, Resolve} requires end of pipe
948 * In other words, fast clear ops are not properly synchronized with
949 * other drawing. We need to use a PIPE_CONTROL to ensure that the
950 * contents of the previous draw hit the render target before we resolve
951 * and again afterwards to ensure that the resolve is complete before we
952 * do any more regular drawing.
954 brw_emit_pipe_control_flush(brw
,
955 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
956 PIPE_CONTROL_CS_STALL
);
959 struct blorp_batch batch
;
960 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
961 blorp_ccs_resolve(&batch
, &surf
, level
, layer
,
962 brw_blorp_to_isl_format(brw
, format
, true),
964 blorp_batch_finish(&batch
);
966 /* See comment above */
967 brw_emit_pipe_control_flush(brw
,
968 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
969 PIPE_CONTROL_CS_STALL
);
973 * Perform a HiZ or depth resolve operation.
975 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
976 * PRM, Volume 1, Part 2:
977 * - 7.5.3.1 Depth Buffer Clear
978 * - 7.5.3.2 Depth Buffer Resolve
979 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
982 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
983 unsigned int level
, unsigned int start_layer
,
984 unsigned int num_layers
, enum blorp_hiz_op op
)
986 assert(intel_miptree_level_has_hiz(mt
, level
));
987 assert(op
!= BLORP_HIZ_OP_NONE
);
988 const char *opname
= NULL
;
991 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
992 opname
= "depth resolve";
994 case BLORP_HIZ_OP_HIZ_RESOLVE
:
995 opname
= "hiz ambiguate";
997 case BLORP_HIZ_OP_DEPTH_CLEAR
:
998 opname
= "depth clear";
1000 case BLORP_HIZ_OP_NONE
:
1005 DBG("%s %s to mt %p level %d layers %d-%d\n",
1006 __func__
, opname
, mt
, level
, start_layer
, start_layer
+ num_layers
- 1);
1008 /* The following stalls and flushes are only documented to be required for
1009 * HiZ clear operations. However, they also seem to be required for the
1010 * HiZ resolve operation which is basically the same as a fast clear only a
1011 * different value is written into the HiZ surface.
1013 if (op
== BLORP_HIZ_OP_DEPTH_CLEAR
|| op
== BLORP_HIZ_OP_HIZ_RESOLVE
) {
1014 if (brw
->gen
== 6) {
1015 /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
1017 * "If other rendering operations have preceded this clear, a
1018 * PIPE_CONTROL with write cache flush enabled and Z-inhibit
1019 * disabled must be issued before the rectangle primitive used for
1020 * the depth buffer clear operation.
1022 brw_emit_pipe_control_flush(brw
,
1023 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1024 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1025 PIPE_CONTROL_CS_STALL
);
1026 } else if (brw
->gen
>= 7) {
1028 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
1030 * If other rendering operations have preceded this clear, a
1031 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
1032 * enabled must be issued before the rectangle primitive used for
1033 * the depth buffer clear operation.
1035 * Same applies for Gen8 and Gen9.
1037 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
1038 * PIPE_CONTROL, Depth Cache Flush Enable:
1040 * This bit must not be set when Depth Stall Enable bit is set in
1043 * This is confirmed to hold for real, HSW gets immediate gpu hangs.
1045 * Therefore issue two pipe control flushes, one for cache flush and
1046 * another for depth stall.
1048 brw_emit_pipe_control_flush(brw
,
1049 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1050 PIPE_CONTROL_CS_STALL
);
1052 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
1057 struct isl_surf isl_tmp
[2];
1058 struct blorp_surf surf
;
1059 blorp_surf_for_miptree(brw
, &surf
, mt
, true, (1 << ISL_AUX_USAGE_HIZ
),
1060 &level
, start_layer
, num_layers
, isl_tmp
);
1062 struct blorp_batch batch
;
1063 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1064 blorp_hiz_op(&batch
, &surf
, level
, start_layer
, num_layers
, op
);
1065 blorp_batch_finish(&batch
);
1067 /* The following stalls and flushes are only documented to be required for
1068 * HiZ clear operations. However, they also seem to be required for the
1069 * HiZ resolve operation which is basically the same as a fast clear only a
1070 * different value is written into the HiZ surface.
1072 if (op
== BLORP_HIZ_OP_DEPTH_CLEAR
|| op
== BLORP_HIZ_OP_HIZ_RESOLVE
) {
1073 if (brw
->gen
== 6) {
1074 /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
1076 * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be
1077 * followed by a PIPE_CONTROL command with DEPTH_STALL bit set
1078 * and Then followed by Depth FLUSH'
1080 brw_emit_pipe_control_flush(brw
,
1081 PIPE_CONTROL_DEPTH_STALL
);
1083 brw_emit_pipe_control_flush(brw
,
1084 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1085 PIPE_CONTROL_CS_STALL
);
1086 } else if (brw
->gen
>= 8) {
1088 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
1090 * "Depth buffer clear pass using any of the methods (WM_STATE,
1091 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
1092 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
1093 * "set" before starting to render. DepthStall and DepthFlush are
1094 * not needed between consecutive depth clear passes nor is it
1095 * required if the depth clear pass was done with
1096 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
1098 * TODO: Such as the spec says, this could be conditional.
1100 brw_emit_pipe_control_flush(brw
,
1101 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1102 PIPE_CONTROL_DEPTH_STALL
);