2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_batchbuffer.h"
26 #include "intel_fbo.h"
28 #include "brw_blorp.h"
29 #include "brw_compiler.h"
31 #include "brw_state.h"
33 #define FILE_DEBUG_FLAG DEBUG_BLORP
36 brw_blorp_surface_info_init(struct brw_context
*brw
,
37 struct brw_blorp_surface_info
*info
,
38 struct intel_mipmap_tree
*mt
,
39 unsigned int level
, unsigned int layer
,
40 mesa_format format
, bool is_render_target
)
42 /* Layer is a physical layer, so if this is a 2D multisample array texture
43 * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it had better
44 * be a multiple of num_samples.
46 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
47 mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
48 assert(mt
->num_samples
<= 1 || layer
% mt
->num_samples
== 0);
51 intel_miptree_check_level_layer(mt
, level
, layer
);
55 intel_miptree_get_isl_surf(brw
, mt
, &info
->surf
);
58 intel_miptree_get_aux_isl_surf(brw
, mt
, &info
->aux_surf
,
61 info
->aux_usage
= ISL_AUX_USAGE_NONE
;
66 info
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
67 info
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
69 intel_miptree_get_image_offset(mt
, level
, layer
,
70 &info
->x_offset
, &info
->y_offset
);
72 info
->num_samples
= mt
->num_samples
;
73 info
->array_layout
= mt
->array_layout
;
74 info
->map_stencil_as_y_tiled
= false;
75 info
->msaa_layout
= mt
->msaa_layout
;
76 info
->swizzle
= SWIZZLE_XYZW
;
78 if (format
== MESA_FORMAT_NONE
)
82 case MESA_FORMAT_S_UINT8
:
83 /* The miptree is a W-tiled stencil buffer. Surface states can't be set
84 * up for W tiling, so we'll need to use Y tiling and have the WM
85 * program swizzle the coordinates.
87 info
->map_stencil_as_y_tiled
= true;
88 info
->brw_surfaceformat
= brw
->gen
>= 8 ? BRW_SURFACEFORMAT_R8_UINT
:
89 BRW_SURFACEFORMAT_R8_UNORM
;
91 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
92 /* It would make sense to use BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
93 * here, but unfortunately it isn't supported as a render target, which
94 * would prevent us from blitting to 24-bit depth.
96 * The miptree consists of 32 bits per pixel, arranged as 24-bit depth
97 * values interleaved with 8 "don't care" bits. Since depth values don't
98 * require any blending, it doesn't matter how we interpret the bit
99 * pattern as long as we copy the right amount of data, so just map it
102 info
->brw_surfaceformat
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
104 case MESA_FORMAT_Z_FLOAT32
:
105 info
->brw_surfaceformat
= BRW_SURFACEFORMAT_R32_FLOAT
;
107 case MESA_FORMAT_Z_UNORM16
:
108 info
->brw_surfaceformat
= BRW_SURFACEFORMAT_R16_UNORM
;
111 if (is_render_target
) {
112 assert(brw
->format_supported_as_render_target
[format
]);
113 info
->brw_surfaceformat
= brw
->render_target_format
[format
];
115 info
->brw_surfaceformat
= brw_format_for_mesa_format(format
);
124 brw_blorp_params_init(struct brw_blorp_params
*params
)
126 memset(params
, 0, sizeof(*params
));
127 params
->hiz_op
= GEN6_HIZ_OP_NONE
;
128 params
->fast_clear_op
= 0;
129 params
->num_draw_buffers
= 1;
130 params
->num_layers
= 1;
134 brw_blorp_init_wm_prog_key(struct brw_wm_prog_key
*wm_key
)
136 memset(wm_key
, 0, sizeof(*wm_key
));
137 wm_key
->nr_color_regions
= 1;
138 for (int i
= 0; i
< MAX_SAMPLERS
; i
++)
139 wm_key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;
143 nir_uniform_type_size(const struct glsl_type
*type
)
145 /* Only very basic types are allowed */
146 assert(glsl_type_is_vector_or_scalar(type
));
147 assert(glsl_get_bit_size(type
) == 32);
149 return glsl_get_vector_elements(type
) * 4;
153 brw_blorp_compile_nir_shader(struct brw_context
*brw
, struct nir_shader
*nir
,
154 const struct brw_wm_prog_key
*wm_key
,
156 struct brw_blorp_prog_data
*prog_data
,
157 unsigned *program_size
)
159 const struct brw_compiler
*compiler
= brw
->intelScreen
->compiler
;
161 void *mem_ctx
= ralloc_context(NULL
);
163 /* Calling brw_preprocess_nir and friends is destructive and, if cloning is
164 * enabled, may end up completely replacing the nir_shader. Therefore, we
165 * own it and might as well put it in our context for easy cleanup.
167 ralloc_steal(mem_ctx
, nir
);
169 compiler
->glsl_compiler_options
[MESA_SHADER_FRAGMENT
].NirOptions
;
171 struct brw_wm_prog_data wm_prog_data
;
172 memset(&wm_prog_data
, 0, sizeof(wm_prog_data
));
174 wm_prog_data
.base
.nr_params
= 0;
175 wm_prog_data
.base
.param
= NULL
;
177 /* BLORP always just uses the first two binding table entries */
178 wm_prog_data
.binding_table
.render_target_start
= 0;
179 wm_prog_data
.base
.binding_table
.texture_start
= 1;
181 nir
= brw_preprocess_nir(compiler
, nir
);
182 nir_remove_dead_variables(nir
, nir_var_shader_in
);
183 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
)->impl
);
185 /* Uniforms are required to be lowered before going into compile_fs. For
186 * BLORP, we'll assume that whoever builds the shader sets the location
187 * they want so we just need to lower them and figure out how many we have
190 nir
->num_uniforms
= 0;
191 nir_foreach_variable(var
, &nir
->uniforms
) {
192 var
->data
.driver_location
= var
->data
.location
;
193 unsigned end
= var
->data
.location
+ nir_uniform_type_size(var
->type
);
194 nir
->num_uniforms
= MAX2(nir
->num_uniforms
, end
);
196 nir_lower_io(nir
, nir_var_uniform
, nir_uniform_type_size
);
198 const unsigned *program
=
199 brw_compile_fs(compiler
, brw
, mem_ctx
, wm_key
, &wm_prog_data
, nir
,
200 NULL
, -1, -1, false, use_repclear
, program_size
, NULL
);
202 /* Copy the relavent bits of wm_prog_data over into the blorp prog data */
203 prog_data
->dispatch_8
= wm_prog_data
.dispatch_8
;
204 prog_data
->dispatch_16
= wm_prog_data
.dispatch_16
;
205 prog_data
->first_curbe_grf_0
= wm_prog_data
.base
.dispatch_grf_start_reg
;
206 prog_data
->first_curbe_grf_2
= wm_prog_data
.dispatch_grf_start_reg_2
;
207 prog_data
->ksp_offset_2
= wm_prog_data
.prog_offset_2
;
208 prog_data
->persample_msaa_dispatch
= wm_prog_data
.persample_dispatch
;
209 prog_data
->flat_inputs
= wm_prog_data
.flat_inputs
;
210 prog_data
->num_varying_inputs
= wm_prog_data
.num_varying_inputs
;
211 prog_data
->inputs_read
= nir
->info
.inputs_read
;
213 assert(wm_prog_data
.base
.nr_params
== 0);
218 static enum isl_msaa_layout
219 get_isl_msaa_layout(enum intel_msaa_layout layout
)
222 case INTEL_MSAA_LAYOUT_NONE
:
223 return ISL_MSAA_LAYOUT_NONE
;
224 case INTEL_MSAA_LAYOUT_IMS
:
225 return ISL_MSAA_LAYOUT_INTERLEAVED
;
226 case INTEL_MSAA_LAYOUT_UMS
:
227 case INTEL_MSAA_LAYOUT_CMS
:
228 return ISL_MSAA_LAYOUT_ARRAY
;
230 unreachable("Invalid MSAA layout");
234 struct surface_state_info
{
236 unsigned ss_align
; /* Required alignment of RENDER_SURFACE_STATE in bytes */
238 unsigned aux_reloc_dw
;
243 static const struct surface_state_info surface_state_infos
[] = {
245 [7] = {8, 32, 1, 6, GEN7_MOCS_L3
, GEN7_MOCS_L3
},
246 [8] = {13, 64, 8, 10, BDW_MOCS_WB
, BDW_MOCS_PTE
},
247 [9] = {16, 64, 8, 10, SKL_MOCS_WB
, SKL_MOCS_PTE
},
251 brw_blorp_emit_surface_state(struct brw_context
*brw
,
252 const struct brw_blorp_surface_info
*surface
,
253 uint32_t read_domains
, uint32_t write_domain
,
254 bool is_render_target
)
256 const struct surface_state_info ss_info
= surface_state_infos
[brw
->gen
];
258 struct isl_surf surf
= surface
->surf
;
260 /* Stomp surface dimensions and tiling (if needed) with info from blorp */
261 surf
.dim
= ISL_SURF_DIM_2D
;
262 surf
.dim_layout
= ISL_DIM_LAYOUT_GEN4_2D
;
263 surf
.msaa_layout
= get_isl_msaa_layout(surface
->msaa_layout
);
264 surf
.logical_level0_px
.width
= surface
->width
;
265 surf
.logical_level0_px
.height
= surface
->height
;
266 surf
.logical_level0_px
.depth
= 1;
267 surf
.logical_level0_px
.array_len
= 1;
269 surf
.samples
= MAX2(surface
->num_samples
, 1);
271 /* Alignment doesn't matter since we have 1 miplevel and 1 array slice so
272 * just pick something that works for everybody.
274 surf
.image_alignment_el
= isl_extent3d(4, 4, 1);
276 if (brw
->gen
== 6 && surface
->num_samples
> 1) {
277 /* Since gen6 uses INTEL_MSAA_LAYOUT_IMS, width and height are measured
278 * in samples. But SURFACE_STATE wants them in pixels, so we need to
279 * divide them each by 2.
281 surf
.logical_level0_px
.width
/= 2;
282 surf
.logical_level0_px
.height
/= 2;
285 if (brw
->gen
== 6 && surf
.image_alignment_el
.height
> 4) {
286 /* This can happen on stencil buffers on Sandy Bridge due to the
287 * single-LOD work-around. It's fairly harmless as long as we don't
288 * pass a bogus value into isl_surf_fill_state().
290 surf
.image_alignment_el
= isl_extent3d(4, 2, 1);
293 /* We need to fake W-tiling with Y-tiling */
294 if (surface
->map_stencil_as_y_tiled
)
295 surf
.tiling
= ISL_TILING_Y0
;
297 union isl_color_value clear_color
= { .u32
= { 0, 0, 0, 0 } };
299 const struct isl_surf
*aux_surf
= NULL
;
300 uint64_t aux_offset
= 0;
301 if (surface
->mt
->mcs_mt
) {
302 aux_surf
= &surface
->aux_surf
;
303 assert(surface
->mt
->mcs_mt
->offset
== 0);
304 aux_offset
= surface
->mt
->mcs_mt
->bo
->offset64
;
306 /* We only really need a clear color if we also have an auxiliary
307 * surface. Without one, it does nothing.
309 clear_color
= intel_miptree_get_isl_clear_color(brw
, surface
->mt
);
312 struct isl_view view
= {
313 .format
= surface
->brw_surfaceformat
,
316 .base_array_layer
= 0,
319 ISL_CHANNEL_SELECT_RED
,
320 ISL_CHANNEL_SELECT_GREEN
,
321 ISL_CHANNEL_SELECT_BLUE
,
322 ISL_CHANNEL_SELECT_ALPHA
,
324 .usage
= is_render_target
? ISL_SURF_USAGE_RENDER_TARGET_BIT
:
325 ISL_SURF_USAGE_TEXTURE_BIT
,
328 uint32_t offset
, tile_x
, tile_y
;
329 isl_tiling_get_intratile_offset_el(&brw
->isl_dev
, surf
.tiling
,
330 isl_format_get_layout(view
.format
)->bpb
/ 8,
332 surface
->x_offset
, surface
->y_offset
,
333 &offset
, &tile_x
, &tile_y
);
335 uint32_t surf_offset
;
336 uint32_t *dw
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
337 ss_info
.num_dwords
* 4, ss_info
.ss_align
,
340 const uint32_t mocs
= is_render_target
? ss_info
.rb_mocs
: ss_info
.tex_mocs
;
342 isl_surf_fill_state(&brw
->isl_dev
, dw
, .surf
= &surf
, .view
= &view
,
343 .address
= surface
->mt
->bo
->offset64
+ offset
,
344 .aux_surf
= aux_surf
, .aux_usage
= surface
->aux_usage
,
345 .aux_address
= aux_offset
,
346 .mocs
= mocs
, .clear_color
= clear_color
,
347 .x_offset_sa
= tile_x
, .y_offset_sa
= tile_y
);
349 /* Emit relocation to surface contents */
350 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
351 surf_offset
+ ss_info
.reloc_dw
* 4,
353 dw
[ss_info
.reloc_dw
] - surface
->mt
->bo
->offset64
,
354 read_domains
, write_domain
);
357 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
358 * used to store other information. This should be ok, however, because
359 * surface buffer addresses are always 4K page alinged.
361 assert((aux_offset
& 0xfff) == 0);
362 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
363 surf_offset
+ ss_info
.aux_reloc_dw
* 4,
364 surface
->mt
->mcs_mt
->bo
,
365 dw
[ss_info
.aux_reloc_dw
] & 0xfff,
366 read_domains
, write_domain
);
373 * Perform a HiZ or depth resolve operation.
375 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
376 * PRM, Volume 1, Part 2:
377 * - 7.5.3.1 Depth Buffer Clear
378 * - 7.5.3.2 Depth Buffer Resolve
379 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
382 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
383 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
)
385 const char *opname
= NULL
;
388 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
389 opname
= "depth resolve";
391 case GEN6_HIZ_OP_HIZ_RESOLVE
:
392 opname
= "hiz ambiguate";
394 case GEN6_HIZ_OP_DEPTH_CLEAR
:
395 opname
= "depth clear";
397 case GEN6_HIZ_OP_NONE
:
402 DBG("%s %s to mt %p level %d layer %d\n",
403 __func__
, opname
, mt
, level
, layer
);
406 gen8_hiz_exec(brw
, mt
, level
, layer
, op
);
408 gen6_blorp_hiz_exec(brw
, mt
, level
, layer
, op
);
413 brw_blorp_exec(struct brw_context
*brw
, const struct brw_blorp_params
*params
)
415 struct gl_context
*ctx
= &brw
->ctx
;
416 const uint32_t estimated_max_batch_usage
= brw
->gen
>= 8 ? 1800 : 1500;
417 bool check_aperture_failed_once
= false;
419 /* Flush the sampler and render caches. We definitely need to flush the
420 * sampler cache so that we get updated contents from the render cache for
421 * the glBlitFramebuffer() source. Also, we are sometimes warned in the
422 * docs to flush the cache between reinterpretations of the same surface
423 * data with different formats, which blorp does for stencil and depth
426 brw_emit_mi_flush(brw
);
428 brw_select_pipeline(brw
, BRW_RENDER_PIPELINE
);
431 intel_batchbuffer_require_space(brw
, estimated_max_batch_usage
, RENDER_RING
);
432 intel_batchbuffer_save_state(brw
);
433 drm_intel_bo
*saved_bo
= brw
->batch
.bo
;
434 uint32_t saved_used
= USED_BATCH(brw
->batch
);
435 uint32_t saved_state_batch_offset
= brw
->batch
.state_batch_offset
;
439 gen6_blorp_exec(brw
, params
);
442 gen7_blorp_exec(brw
, params
);
446 gen8_blorp_exec(brw
, params
);
449 /* BLORP is not supported before Gen6. */
450 unreachable("not reached");
453 /* Make sure we didn't wrap the batch unintentionally, and make sure we
454 * reserved enough space that a wrap will never happen.
456 assert(brw
->batch
.bo
== saved_bo
);
457 assert((USED_BATCH(brw
->batch
) - saved_used
) * 4 +
458 (saved_state_batch_offset
- brw
->batch
.state_batch_offset
) <
459 estimated_max_batch_usage
);
460 /* Shut up compiler warnings on release build */
463 (void)saved_state_batch_offset
;
465 /* Check if the blorp op we just did would make our batch likely to fail to
466 * map all the BOs into the GPU at batch exec time later. If so, flush the
467 * batch and try again with nothing else in the batch.
469 if (dri_bufmgr_check_aperture_space(&brw
->batch
.bo
, 1)) {
470 if (!check_aperture_failed_once
) {
471 check_aperture_failed_once
= true;
472 intel_batchbuffer_reset_to_saved(brw
);
473 intel_batchbuffer_flush(brw
);
476 int ret
= intel_batchbuffer_flush(brw
);
477 WARN_ONCE(ret
== -ENOSPC
,
478 "i965: blorp emit exceeded available aperture space\n");
482 if (unlikely(brw
->always_flush_batch
))
483 intel_batchbuffer_flush(brw
);
485 /* We've smashed all state compared to what the normal 3D pipeline
486 * rendering tracks for GL.
488 brw
->ctx
.NewDriverState
|= BRW_NEW_BLORP
;
489 brw
->no_depth_or_stencil
= false;
492 /* Flush the sampler cache so any texturing from the destination is
495 brw_emit_mi_flush(brw
);
499 gen6_blorp_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
500 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
)
502 struct brw_blorp_params params
;
503 brw_blorp_params_init(¶ms
);
507 brw_blorp_surface_info_init(brw
, ¶ms
.depth
, mt
, level
, layer
,
510 /* Align the rectangle primitive to 8x4 pixels.
512 * During fast depth clears, the emitted rectangle primitive must be
513 * aligned to 8x4 pixels. From the Ivybridge PRM, Vol 2 Part 1 Section
514 * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
516 * If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
517 * aligned to an 8x4 pixel block relative to the upper left corner
518 * of the depth buffer [...]
520 * For hiz resolves, the rectangle must also be 8x4 aligned. Item
521 * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
522 * Ivybridge simulator require the alignment.
524 * To be safe, let's just align the rect for all hiz operations and all
525 * hardware generations.
527 * However, for some miptree slices of a Z24 texture, emitting an 8x4
528 * aligned rectangle that covers the slice may clobber adjacent slices if
529 * we strictly adhered to the texture alignments specified in the PRM. The
530 * Ivybridge PRM, Section "Alignment Unit Size", states that
531 * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
532 * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
533 * prevents the clobbering.
535 params
.dst
.num_samples
= mt
->num_samples
;
536 if (params
.dst
.num_samples
> 1) {
537 params
.depth
.width
= ALIGN(mt
->logical_width0
, 8);
538 params
.depth
.height
= ALIGN(mt
->logical_height0
, 4);
540 params
.depth
.width
= ALIGN(params
.depth
.width
, 8);
541 params
.depth
.height
= ALIGN(params
.depth
.height
, 4);
544 params
.x1
= params
.depth
.width
;
545 params
.y1
= params
.depth
.height
;
547 assert(intel_miptree_level_has_hiz(mt
, level
));
549 switch (mt
->format
) {
550 case MESA_FORMAT_Z_UNORM16
:
551 params
.depth_format
= BRW_DEPTHFORMAT_D16_UNORM
;
553 case MESA_FORMAT_Z_FLOAT32
:
554 params
.depth_format
= BRW_DEPTHFORMAT_D32_FLOAT
;
556 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
557 params
.depth_format
= BRW_DEPTHFORMAT_D24_UNORM_X8_UINT
;
560 unreachable("not reached");
563 brw_blorp_exec(brw
, ¶ms
);