2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/blend.h"
27 #include "main/fbobject.h"
28 #include "main/renderbuffer.h"
29 #include "main/glformats.h"
31 #include "brw_blorp.h"
32 #include "brw_context.h"
33 #include "brw_defines.h"
34 #include "brw_meta_util.h"
35 #include "brw_state.h"
36 #include "intel_fbo.h"
37 #include "common/gen_debug.h"
39 #define FILE_DEBUG_FLAG DEBUG_BLORP
42 brw_blorp_lookup_shader(struct blorp_context
*blorp
,
43 const void *key
, uint32_t key_size
,
44 uint32_t *kernel_out
, void *prog_data_out
)
46 struct brw_context
*brw
= blorp
->driver_ctx
;
47 return brw_search_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
,
48 key
, key_size
, kernel_out
, prog_data_out
);
52 brw_blorp_upload_shader(struct blorp_context
*blorp
,
53 const void *key
, uint32_t key_size
,
54 const void *kernel
, uint32_t kernel_size
,
55 const struct brw_stage_prog_data
*prog_data
,
56 uint32_t prog_data_size
,
57 uint32_t *kernel_out
, void *prog_data_out
)
59 struct brw_context
*brw
= blorp
->driver_ctx
;
60 brw_upload_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
, key
, key_size
,
61 kernel
, kernel_size
, prog_data
, prog_data_size
,
62 kernel_out
, prog_data_out
);
67 brw_blorp_init(struct brw_context
*brw
)
69 blorp_init(&brw
->blorp
, brw
, &brw
->isl_dev
);
71 brw
->blorp
.compiler
= brw
->screen
->compiler
;
76 brw
->blorp
.exec
= gen45_blorp_exec
;
78 brw
->blorp
.exec
= gen4_blorp_exec
;
82 brw
->blorp
.exec
= gen5_blorp_exec
;
85 brw
->blorp
.mocs
.tex
= 0;
86 brw
->blorp
.mocs
.rb
= 0;
87 brw
->blorp
.mocs
.vb
= 0;
88 brw
->blorp
.exec
= gen6_blorp_exec
;
91 brw
->blorp
.mocs
.tex
= GEN7_MOCS_L3
;
92 brw
->blorp
.mocs
.rb
= GEN7_MOCS_L3
;
93 brw
->blorp
.mocs
.vb
= GEN7_MOCS_L3
;
94 if (brw
->is_haswell
) {
95 brw
->blorp
.exec
= gen75_blorp_exec
;
97 brw
->blorp
.exec
= gen7_blorp_exec
;
101 brw
->blorp
.mocs
.tex
= BDW_MOCS_WB
;
102 brw
->blorp
.mocs
.rb
= BDW_MOCS_PTE
;
103 brw
->blorp
.mocs
.vb
= BDW_MOCS_WB
;
104 brw
->blorp
.exec
= gen8_blorp_exec
;
107 brw
->blorp
.mocs
.tex
= SKL_MOCS_WB
;
108 brw
->blorp
.mocs
.rb
= SKL_MOCS_PTE
;
109 brw
->blorp
.mocs
.vb
= SKL_MOCS_WB
;
110 brw
->blorp
.exec
= gen9_blorp_exec
;
113 brw
->blorp
.mocs
.tex
= CNL_MOCS_WB
;
114 brw
->blorp
.mocs
.rb
= CNL_MOCS_PTE
;
115 brw
->blorp
.mocs
.vb
= CNL_MOCS_WB
;
116 brw
->blorp
.exec
= gen10_blorp_exec
;
119 unreachable("Invalid gen");
122 brw
->blorp
.lookup_shader
= brw_blorp_lookup_shader
;
123 brw
->blorp
.upload_shader
= brw_blorp_upload_shader
;
127 blorp_surf_for_miptree(struct brw_context
*brw
,
128 struct blorp_surf
*surf
,
129 struct intel_mipmap_tree
*mt
,
130 bool is_render_target
,
132 uint32_t safe_aux_usage
,
134 unsigned start_layer
, unsigned num_layers
,
135 struct isl_surf tmp_surfs
[2])
137 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
138 mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
139 const unsigned num_samples
= MAX2(1, mt
->num_samples
);
140 for (unsigned i
= 0; i
< num_layers
; i
++) {
141 for (unsigned s
= 0; s
< num_samples
; s
++) {
142 const unsigned phys_layer
= (start_layer
+ i
) * num_samples
+ s
;
143 intel_miptree_check_level_layer(mt
, *level
, phys_layer
);
147 for (unsigned i
= 0; i
< num_layers
; i
++)
148 intel_miptree_check_level_layer(mt
, *level
, start_layer
+ i
);
151 intel_miptree_get_isl_surf(brw
, mt
, &tmp_surfs
[0]);
152 surf
->surf
= &tmp_surfs
[0];
153 surf
->addr
= (struct blorp_address
) {
155 .offset
= mt
->offset
,
156 .read_domains
= is_render_target
? I915_GEM_DOMAIN_RENDER
:
157 I915_GEM_DOMAIN_SAMPLER
,
158 .write_domain
= is_render_target
? I915_GEM_DOMAIN_RENDER
: 0,
161 struct isl_surf
*aux_surf
= &tmp_surfs
[1];
162 intel_miptree_get_aux_isl_surf(brw
, mt
, aux_surf
, &surf
->aux_usage
);
165 bool supports_aux
= surf
->aux_usage
!= ISL_AUX_USAGE_NONE
&&
166 (safe_aux_usage
& (1 << surf
->aux_usage
));
167 intel_miptree_prepare_access(brw
, mt
, *level
, 1, start_layer
, num_layers
,
168 supports_aux
, supports_aux
);
170 surf
->aux_usage
= ISL_AUX_USAGE_NONE
;
172 if (is_render_target
) {
173 intel_miptree_finish_write(brw
, mt
, *level
, start_layer
, num_layers
,
178 if (surf
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
179 /* We only really need a clear color if we also have an auxiliary
180 * surface. Without one, it does nothing.
182 surf
->clear_color
= mt
->fast_clear_color
;
184 surf
->aux_surf
= aux_surf
;
185 surf
->aux_addr
= (struct blorp_address
) {
186 .read_domains
= is_render_target
? I915_GEM_DOMAIN_RENDER
:
187 I915_GEM_DOMAIN_SAMPLER
,
188 .write_domain
= is_render_target
? I915_GEM_DOMAIN_RENDER
: 0,
192 surf
->aux_addr
.buffer
= mt
->mcs_buf
->bo
;
193 surf
->aux_addr
.offset
= mt
->mcs_buf
->offset
;
195 assert(surf
->aux_usage
== ISL_AUX_USAGE_HIZ
);
197 surf
->aux_addr
.buffer
= mt
->hiz_buf
->aux_base
.bo
;
198 surf
->aux_addr
.offset
= mt
->hiz_buf
->aux_base
.offset
;
201 surf
->aux_addr
= (struct blorp_address
) {
204 memset(&surf
->clear_color
, 0, sizeof(surf
->clear_color
));
206 assert((surf
->aux_usage
== ISL_AUX_USAGE_NONE
) ==
207 (surf
->aux_addr
.buffer
== NULL
));
209 /* ISL wants real levels, not offset ones. */
210 *level
-= mt
->first_level
;
213 static enum isl_format
214 brw_blorp_to_isl_format(struct brw_context
*brw
, mesa_format format
,
215 bool is_render_target
)
218 case MESA_FORMAT_NONE
:
219 return ISL_FORMAT_UNSUPPORTED
;
220 case MESA_FORMAT_S_UINT8
:
221 return ISL_FORMAT_R8_UINT
;
222 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
223 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
224 return ISL_FORMAT_R24_UNORM_X8_TYPELESS
;
225 case MESA_FORMAT_Z_FLOAT32
:
226 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
227 return ISL_FORMAT_R32_FLOAT
;
228 case MESA_FORMAT_Z_UNORM16
:
229 return ISL_FORMAT_R16_UNORM
;
231 if (is_render_target
) {
232 assert(brw
->format_supported_as_render_target
[format
]);
233 return brw
->render_target_format
[format
];
235 return brw_isl_format_for_mesa_format(format
);
243 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
244 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
246 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
249 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
251 * which is simply adding 4 then modding by 8 (or anding with 7).
253 * We then may need to apply workarounds for textureGather hardware bugs.
255 static enum isl_channel_select
256 swizzle_to_scs(GLenum swizzle
)
258 return (enum isl_channel_select
)((swizzle
+ 4) & 7);
262 physical_to_logical_layer(struct intel_mipmap_tree
*mt
,
263 unsigned physical_layer
)
265 if (mt
->num_samples
> 1 &&
266 (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
267 mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
)) {
268 assert(physical_layer
% mt
->num_samples
== 0);
269 return physical_layer
/ mt
->num_samples
;
271 return physical_layer
;
276 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
277 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
278 * the physical layer holding sample 0. So, for example, if
279 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
283 brw_blorp_blit_miptrees(struct brw_context
*brw
,
284 struct intel_mipmap_tree
*src_mt
,
285 unsigned src_level
, unsigned src_layer
,
286 mesa_format src_format
, int src_swizzle
,
287 struct intel_mipmap_tree
*dst_mt
,
288 unsigned dst_level
, unsigned dst_layer
,
289 mesa_format dst_format
,
290 float src_x0
, float src_y0
,
291 float src_x1
, float src_y1
,
292 float dst_x0
, float dst_y0
,
293 float dst_x1
, float dst_y1
,
294 GLenum filter
, bool mirror_x
, bool mirror_y
,
295 bool decode_srgb
, bool encode_srgb
)
297 /* Blorp operates in logical layers */
298 src_layer
= physical_to_logical_layer(src_mt
, src_layer
);
299 dst_layer
= physical_to_logical_layer(dst_mt
, dst_layer
);
301 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
302 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
304 src_mt
->num_samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
305 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
306 dst_mt
->num_samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
307 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
310 if (!decode_srgb
&& _mesa_get_format_color_encoding(src_format
) == GL_SRGB
)
311 src_format
= _mesa_get_srgb_format_linear(src_format
);
313 if (!encode_srgb
&& _mesa_get_format_color_encoding(dst_format
) == GL_SRGB
)
314 dst_format
= _mesa_get_srgb_format_linear(dst_format
);
316 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
317 * texture, the above code configures the source format for L32_FLOAT or
318 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
319 * the SAMPLE message appears to handle multisampled L32_FLOAT and
320 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
321 * around the problem by using a source format of R32_FLOAT. This
322 * shouldn't affect rendering correctness, since the destination format is
323 * R32_FLOAT, so only the contents of the red channel matters.
326 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1 &&
327 src_mt
->format
== dst_mt
->format
&&
328 (dst_format
== MESA_FORMAT_L_FLOAT32
||
329 dst_format
== MESA_FORMAT_I_FLOAT32
)) {
330 src_format
= dst_format
= MESA_FORMAT_R_FLOAT32
;
333 uint32_t src_usage_flags
= (1 << ISL_AUX_USAGE_MCS
);
334 if (src_format
== src_mt
->format
)
335 src_usage_flags
|= (1 << ISL_AUX_USAGE_CCS_E
);
337 uint32_t dst_usage_flags
= (1 << ISL_AUX_USAGE_MCS
);
338 if (dst_format
== dst_mt
->format
) {
339 dst_usage_flags
|= (1 << ISL_AUX_USAGE_CCS_E
) |
340 (1 << ISL_AUX_USAGE_CCS_D
);
343 struct isl_surf tmp_surfs
[4];
344 struct blorp_surf src_surf
, dst_surf
;
345 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, false, true, src_usage_flags
,
346 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
347 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, true, true, dst_usage_flags
,
348 &dst_level
, dst_layer
, 1, &tmp_surfs
[2]);
350 struct isl_swizzle src_isl_swizzle
= {
351 .r
= swizzle_to_scs(GET_SWZ(src_swizzle
, 0)),
352 .g
= swizzle_to_scs(GET_SWZ(src_swizzle
, 1)),
353 .b
= swizzle_to_scs(GET_SWZ(src_swizzle
, 2)),
354 .a
= swizzle_to_scs(GET_SWZ(src_swizzle
, 3)),
357 struct blorp_batch batch
;
358 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
359 blorp_blit(&batch
, &src_surf
, src_level
, src_layer
,
360 brw_blorp_to_isl_format(brw
, src_format
, false), src_isl_swizzle
,
361 &dst_surf
, dst_level
, dst_layer
,
362 brw_blorp_to_isl_format(brw
, dst_format
, true),
363 ISL_SWIZZLE_IDENTITY
,
364 src_x0
, src_y0
, src_x1
, src_y1
,
365 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
366 filter
, mirror_x
, mirror_y
);
367 blorp_batch_finish(&batch
);
371 brw_blorp_copy_miptrees(struct brw_context
*brw
,
372 struct intel_mipmap_tree
*src_mt
,
373 unsigned src_level
, unsigned src_layer
,
374 struct intel_mipmap_tree
*dst_mt
,
375 unsigned dst_level
, unsigned dst_layer
,
376 unsigned src_x
, unsigned src_y
,
377 unsigned dst_x
, unsigned dst_y
,
378 unsigned src_width
, unsigned src_height
)
380 DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
381 "to %dx %s mt %p %d %d (%d,%d)\n",
383 src_mt
->num_samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
384 src_level
, src_layer
, src_x
, src_y
, src_width
, src_height
,
385 dst_mt
->num_samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
386 dst_level
, dst_layer
, dst_x
, dst_y
);
388 struct isl_surf tmp_surfs
[4];
389 struct blorp_surf src_surf
, dst_surf
;
390 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, false, true,
391 (1 << ISL_AUX_USAGE_MCS
) |
392 (1 << ISL_AUX_USAGE_CCS_E
),
393 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
394 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, true, true,
395 (1 << ISL_AUX_USAGE_MCS
) |
396 (1 << ISL_AUX_USAGE_CCS_E
),
397 &dst_level
, dst_layer
, 1, &tmp_surfs
[2]);
399 struct blorp_batch batch
;
400 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
401 blorp_copy(&batch
, &src_surf
, src_level
, src_layer
,
402 &dst_surf
, dst_level
, dst_layer
,
403 src_x
, src_y
, dst_x
, dst_y
, src_width
, src_height
);
404 blorp_batch_finish(&batch
);
407 static struct intel_mipmap_tree
*
408 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
410 struct intel_mipmap_tree
*mt
= irb
->mt
;
411 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
417 blorp_get_texture_swizzle(const struct intel_renderbuffer
*irb
)
419 return irb
->Base
.Base
._BaseFormat
== GL_RGB
?
420 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ONE
) :
425 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
426 struct intel_renderbuffer
*src_irb
, mesa_format src_format
,
427 struct intel_renderbuffer
*dst_irb
, mesa_format dst_format
,
428 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
429 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
430 GLenum filter
, bool mirror_x
, bool mirror_y
)
432 const struct gl_context
*ctx
= &brw
->ctx
;
434 /* Find source/dst miptrees */
435 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
436 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
438 const bool do_srgb
= ctx
->Color
.sRGBEnabled
;
441 brw_blorp_blit_miptrees(brw
,
442 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
443 src_format
, blorp_get_texture_swizzle(src_irb
),
444 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
446 srcX0
, srcY0
, srcX1
, srcY1
,
447 dstX0
, dstY0
, dstX1
, dstY1
,
448 filter
, mirror_x
, mirror_y
,
451 dst_irb
->need_downsample
= true;
455 try_blorp_blit(struct brw_context
*brw
,
456 const struct gl_framebuffer
*read_fb
,
457 const struct gl_framebuffer
*draw_fb
,
458 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
459 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
460 GLenum filter
, GLbitfield buffer_bit
)
462 struct gl_context
*ctx
= &brw
->ctx
;
464 /* Sync up the state of window system buffers. We need to do this before
465 * we go looking for the buffers.
467 intel_prepare_render(brw
);
469 bool mirror_x
, mirror_y
;
470 if (brw_meta_mirror_clip_and_scissor(ctx
, read_fb
, draw_fb
,
471 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
472 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
473 &mirror_x
, &mirror_y
))
477 struct intel_renderbuffer
*src_irb
;
478 struct intel_renderbuffer
*dst_irb
;
479 struct intel_mipmap_tree
*src_mt
;
480 struct intel_mipmap_tree
*dst_mt
;
481 switch (buffer_bit
) {
482 case GL_COLOR_BUFFER_BIT
:
483 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
484 for (unsigned i
= 0; i
< draw_fb
->_NumColorDrawBuffers
; ++i
) {
485 dst_irb
= intel_renderbuffer(draw_fb
->_ColorDrawBuffers
[i
]);
487 do_blorp_blit(brw
, buffer_bit
,
488 src_irb
, src_irb
->Base
.Base
.Format
,
489 dst_irb
, dst_irb
->Base
.Base
.Format
,
490 srcX0
, srcY0
, srcX1
, srcY1
,
491 dstX0
, dstY0
, dstX1
, dstY1
,
492 filter
, mirror_x
, mirror_y
);
495 case GL_DEPTH_BUFFER_BIT
:
497 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
499 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
500 src_mt
= find_miptree(buffer_bit
, src_irb
);
501 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
503 /* We can't handle format conversions between Z24 and other formats
504 * since we have to lie about the surface format. See the comments in
505 * brw_blorp_surface_info::set().
507 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
508 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
))
511 /* We also can't handle any combined depth-stencil formats because we
512 * have to reinterpret as a color format.
514 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
515 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
518 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
519 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
520 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
521 filter
, mirror_x
, mirror_y
);
523 case GL_STENCIL_BUFFER_BIT
:
524 /* Blorp doesn't support combined depth stencil which is all we have
531 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
533 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
534 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
535 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
536 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
537 filter
, mirror_x
, mirror_y
);
540 unreachable("not reached");
547 brw_blorp_copytexsubimage(struct brw_context
*brw
,
548 struct gl_renderbuffer
*src_rb
,
549 struct gl_texture_image
*dst_image
,
551 int srcX0
, int srcY0
,
552 int dstX0
, int dstY0
,
553 int width
, int height
)
555 struct gl_context
*ctx
= &brw
->ctx
;
556 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
557 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
559 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
560 if (brw
->ctx
._ImageTransferState
)
563 /* Sync up the state of window system buffers. We need to do this before
564 * we go looking at the src renderbuffer's miptree.
566 intel_prepare_render(brw
);
568 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
569 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
571 /* There is support for only up to eight samples. */
572 if (src_mt
->num_samples
> 8 || dst_mt
->num_samples
> 8)
575 if (_mesa_get_format_base_format(src_rb
->Format
) !=
576 _mesa_get_format_base_format(dst_image
->TexFormat
)) {
580 /* We can't handle format conversions between Z24 and other formats since
581 * we have to lie about the surface format. See the comments in
582 * brw_blorp_surface_info::set().
584 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
585 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
)) {
589 /* We also can't handle any combined depth-stencil formats because we
590 * have to reinterpret as a color format.
592 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
593 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
596 if (!brw
->format_supported_as_render_target
[dst_image
->TexFormat
])
599 /* Source clipping shouldn't be necessary, since copytexsubimage (in
600 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
603 * Destination clipping shouldn't be necessary since the restrictions on
604 * glCopyTexSubImage prevent the user from specifying a destination rectangle
605 * that falls outside the bounds of the destination texture.
606 * See error_check_subtexture_dimensions().
609 int srcY1
= srcY0
+ height
;
610 int srcX1
= srcX0
+ width
;
611 int dstX1
= dstX0
+ width
;
612 int dstY1
= dstY0
+ height
;
614 /* Account for the fact that in the system framebuffer, the origin is at
617 bool mirror_y
= false;
618 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
619 GLint tmp
= src_rb
->Height
- srcY0
;
620 srcY0
= src_rb
->Height
- srcY1
;
625 /* Account for face selection and texture view MinLayer */
626 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
627 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
629 brw_blorp_blit_miptrees(brw
,
630 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
631 src_rb
->Format
, blorp_get_texture_swizzle(src_irb
),
632 dst_mt
, dst_level
, dst_slice
,
633 dst_image
->TexFormat
,
634 srcX0
, srcY0
, srcX1
, srcY1
,
635 dstX0
, dstY0
, dstX1
, dstY1
,
636 GL_NEAREST
, false, mirror_y
,
639 /* If we're copying to a packed depth stencil texture and the source
640 * framebuffer has separate stencil, we need to also copy the stencil data
643 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
644 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
646 src_irb
= intel_renderbuffer(src_rb
);
647 src_mt
= src_irb
->mt
;
649 if (src_mt
->stencil_mt
)
650 src_mt
= src_mt
->stencil_mt
;
651 if (dst_mt
->stencil_mt
)
652 dst_mt
= dst_mt
->stencil_mt
;
654 if (src_mt
!= dst_mt
) {
655 brw_blorp_blit_miptrees(brw
,
656 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
658 blorp_get_texture_swizzle(src_irb
),
659 dst_mt
, dst_level
, dst_slice
,
661 srcX0
, srcY0
, srcX1
, srcY1
,
662 dstX0
, dstY0
, dstX1
, dstY1
,
663 GL_NEAREST
, false, mirror_y
,
673 brw_blorp_framebuffer(struct brw_context
*brw
,
674 struct gl_framebuffer
*readFb
,
675 struct gl_framebuffer
*drawFb
,
676 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
677 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
678 GLbitfield mask
, GLenum filter
)
680 static GLbitfield buffer_bits
[] = {
683 GL_STENCIL_BUFFER_BIT
,
686 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
687 if ((mask
& buffer_bits
[i
]) &&
688 try_blorp_blit(brw
, readFb
, drawFb
,
689 srcX0
, srcY0
, srcX1
, srcY1
,
690 dstX0
, dstY0
, dstX1
, dstY1
,
691 filter
, buffer_bits
[i
])) {
692 mask
&= ~buffer_bits
[i
];
700 set_write_disables(const struct intel_renderbuffer
*irb
,
701 const GLubyte
*color_mask
, bool *color_write_disable
)
703 /* Format information in the renderbuffer represents the requirements
704 * given by the client. There are cases where the backing miptree uses,
705 * for example, RGBA to represent RGBX. Since the client is only expecting
706 * RGB we can treat alpha as not used and write whatever we like into it.
708 const GLenum base_format
= irb
->Base
.Base
._BaseFormat
;
709 const int components
= _mesa_base_format_component_count(base_format
);
710 bool disables
= false;
712 assert(components
> 0);
714 for (int i
= 0; i
< components
; i
++) {
715 color_write_disable
[i
] = !color_mask
[i
];
716 disables
= disables
|| !color_mask
[i
];
723 irb_logical_mt_layer(struct intel_renderbuffer
*irb
)
725 return physical_to_logical_layer(irb
->mt
, irb
->mt_layer
);
729 do_single_blorp_clear(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
730 struct gl_renderbuffer
*rb
, unsigned buf
,
731 bool partial_clear
, bool encode_srgb
)
733 struct gl_context
*ctx
= &brw
->ctx
;
734 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
735 mesa_format format
= irb
->mt
->format
;
736 uint32_t x0
, x1
, y0
, y1
;
738 if (!encode_srgb
&& _mesa_get_format_color_encoding(format
) == GL_SRGB
)
739 format
= _mesa_get_srgb_format_linear(format
);
747 y0
= rb
->Height
- fb
->_Ymax
;
748 y1
= rb
->Height
- fb
->_Ymin
;
751 /* If the clear region is empty, just return. */
752 if (x0
== x1
|| y0
== y1
)
755 bool can_fast_clear
= !partial_clear
;
757 bool color_write_disable
[4] = { false, false, false, false };
758 if (set_write_disables(irb
, ctx
->Color
.ColorMask
[buf
], color_write_disable
))
759 can_fast_clear
= false;
761 if (irb
->mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
||
762 !brw_is_color_fast_clear_compatible(brw
, irb
->mt
, &ctx
->Color
.ClearColor
))
763 can_fast_clear
= false;
765 const unsigned logical_layer
= irb_logical_mt_layer(irb
);
767 /* Surface state can only record one fast clear color value. Therefore
768 * unless different levels/layers agree on the color it can be used to
769 * represent only single level/layer. Here it will be reserved for the
770 * first slice (level 0, layer 0).
772 if (irb
->layer_count
> 1 || irb
->mt_level
|| irb
->mt_layer
)
773 can_fast_clear
= false;
775 unsigned level
= irb
->mt_level
;
776 const unsigned num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
778 if (can_fast_clear
) {
779 /* If the MCS buffer hasn't been allocated yet, we need to allocate
782 if (!irb
->mt
->mcs_buf
) {
783 assert(!intel_miptree_is_lossless_compressed(brw
, irb
->mt
));
784 if (!intel_miptree_alloc_non_msrt_mcs(brw
, irb
->mt
, false)) {
785 /* MCS allocation failed--probably this will only happen in
786 * out-of-memory conditions. But in any case, try to recover
787 * by falling back to a non-blorp clear technique.
793 const enum isl_aux_state aux_state
=
794 intel_miptree_get_aux_state(irb
->mt
, irb
->mt_level
, logical_layer
);
795 union isl_color_value clear_color
=
796 brw_meta_convert_fast_clear_color(brw
, irb
->mt
,
797 &ctx
->Color
.ClearColor
);
799 /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
800 * is redundant and can be skipped.
802 if (aux_state
== ISL_AUX_STATE_CLEAR
&&
803 memcmp(&irb
->mt
->fast_clear_color
,
804 &clear_color
, sizeof(clear_color
)) == 0)
807 irb
->mt
->fast_clear_color
= clear_color
;
809 DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__
,
810 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
812 /* We can't setup the blorp_surf until we've allocated the MCS above */
813 struct isl_surf isl_tmp
[2];
814 struct blorp_surf surf
;
815 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, true, false, 0,
816 &level
, logical_layer
, num_layers
, isl_tmp
);
818 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
820 * "Any transition from any value in {Clear, Render, Resolve} to a
821 * different value in {Clear, Render, Resolve} requires end of pipe
824 * In other words, fast clear ops are not properly synchronized with
825 * other drawing. We need to use a PIPE_CONTROL to ensure that the
826 * contents of the previous draw hit the render target before we resolve
827 * and again afterwards to ensure that the resolve is complete before we
828 * do any more regular drawing.
830 brw_emit_pipe_control_flush(brw
,
831 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
832 PIPE_CONTROL_CS_STALL
);
834 struct blorp_batch batch
;
835 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
836 blorp_fast_clear(&batch
, &surf
,
837 brw
->render_target_format
[format
],
838 level
, logical_layer
, num_layers
,
840 blorp_batch_finish(&batch
);
842 brw_emit_pipe_control_flush(brw
,
843 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
844 PIPE_CONTROL_CS_STALL
);
846 /* Now that the fast clear has occurred, put the buffer in
847 * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
850 intel_miptree_set_aux_state(brw
, irb
->mt
, irb
->mt_level
,
851 logical_layer
, num_layers
,
852 ISL_AUX_STATE_CLEAR
);
854 DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__
,
855 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
857 struct isl_surf isl_tmp
[2];
858 struct blorp_surf surf
;
859 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, true, true,
860 (1 << ISL_AUX_USAGE_MCS
) |
861 (1 << ISL_AUX_USAGE_CCS_E
) |
862 (1 << ISL_AUX_USAGE_CCS_D
),
863 &level
, logical_layer
, num_layers
, isl_tmp
);
865 union isl_color_value clear_color
;
866 memcpy(clear_color
.f32
, ctx
->Color
.ClearColor
.f
, sizeof(float) * 4);
868 struct blorp_batch batch
;
869 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
870 blorp_clear(&batch
, &surf
,
871 brw
->render_target_format
[format
],
872 ISL_SWIZZLE_IDENTITY
,
873 level
, irb_logical_mt_layer(irb
), num_layers
,
875 clear_color
, color_write_disable
);
876 blorp_batch_finish(&batch
);
883 brw_blorp_clear_color(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
884 GLbitfield mask
, bool partial_clear
, bool encode_srgb
)
886 for (unsigned buf
= 0; buf
< fb
->_NumColorDrawBuffers
; buf
++) {
887 struct gl_renderbuffer
*rb
= fb
->_ColorDrawBuffers
[buf
];
888 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
890 /* Only clear the buffers present in the provided mask */
891 if (((1 << fb
->_ColorDrawBufferIndexes
[buf
]) & mask
) == 0)
894 /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
895 * the framebuffer can be complete with some attachments missing. In
896 * this case the _ColorDrawBuffers pointer will be NULL.
901 if (!do_single_blorp_clear(brw
, fb
, rb
, buf
, partial_clear
,
906 irb
->need_downsample
= true;
913 brw_blorp_resolve_color(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
914 unsigned level
, unsigned layer
,
915 enum blorp_fast_clear_op resolve_op
)
917 DBG("%s to mt %p level %u layer %u\n", __FUNCTION__
, mt
, level
, layer
);
919 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
921 struct isl_surf isl_tmp
[2];
922 struct blorp_surf surf
;
923 blorp_surf_for_miptree(brw
, &surf
, mt
, true, false, 0,
924 &level
, layer
, 1 /* num_layers */,
927 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
929 * "Any transition from any value in {Clear, Render, Resolve} to a
930 * different value in {Clear, Render, Resolve} requires end of pipe
933 * In other words, fast clear ops are not properly synchronized with
934 * other drawing. We need to use a PIPE_CONTROL to ensure that the
935 * contents of the previous draw hit the render target before we resolve
936 * and again afterwards to ensure that the resolve is complete before we
937 * do any more regular drawing.
939 brw_emit_pipe_control_flush(brw
,
940 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
941 PIPE_CONTROL_CS_STALL
);
944 struct blorp_batch batch
;
945 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
946 blorp_ccs_resolve(&batch
, &surf
, level
, layer
,
947 brw_blorp_to_isl_format(brw
, format
, true),
949 blorp_batch_finish(&batch
);
951 /* See comment above */
952 brw_emit_pipe_control_flush(brw
,
953 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
954 PIPE_CONTROL_CS_STALL
);
958 * Perform a HiZ or depth resolve operation.
960 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
961 * PRM, Volume 1, Part 2:
962 * - 7.5.3.1 Depth Buffer Clear
963 * - 7.5.3.2 Depth Buffer Resolve
964 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
967 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
968 unsigned int level
, unsigned int start_layer
,
969 unsigned int num_layers
, enum blorp_hiz_op op
)
971 assert(intel_miptree_level_has_hiz(mt
, level
));
972 assert(op
!= BLORP_HIZ_OP_NONE
);
973 const char *opname
= NULL
;
976 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
977 opname
= "depth resolve";
979 case BLORP_HIZ_OP_HIZ_RESOLVE
:
980 opname
= "hiz ambiguate";
982 case BLORP_HIZ_OP_DEPTH_CLEAR
:
983 opname
= "depth clear";
985 case BLORP_HIZ_OP_NONE
:
990 DBG("%s %s to mt %p level %d layers %d-%d\n",
991 __func__
, opname
, mt
, level
, start_layer
, start_layer
+ num_layers
- 1);
993 /* The following stalls and flushes are only documented to be required for
994 * HiZ clear operations. However, they also seem to be required for the
995 * HiZ resolve operation which is basically the same as a fast clear only a
996 * different value is written into the HiZ surface.
998 if (op
== BLORP_HIZ_OP_DEPTH_CLEAR
|| op
== BLORP_HIZ_OP_HIZ_RESOLVE
) {
1000 /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
1002 * "If other rendering operations have preceded this clear, a
1003 * PIPE_CONTROL with write cache flush enabled and Z-inhibit
1004 * disabled must be issued before the rectangle primitive used for
1005 * the depth buffer clear operation.
1007 brw_emit_pipe_control_flush(brw
,
1008 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1009 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1010 PIPE_CONTROL_CS_STALL
);
1011 } else if (brw
->gen
>= 7) {
1013 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
1015 * If other rendering operations have preceded this clear, a
1016 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
1017 * enabled must be issued before the rectangle primitive used for
1018 * the depth buffer clear operation.
1020 * Same applies for Gen8 and Gen9.
1022 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
1023 * PIPE_CONTROL, Depth Cache Flush Enable:
1025 * This bit must not be set when Depth Stall Enable bit is set in
1028 * This is confirmed to hold for real, HSW gets immediate gpu hangs.
1030 * Therefore issue two pipe control flushes, one for cache flush and
1031 * another for depth stall.
1033 brw_emit_pipe_control_flush(brw
,
1034 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1035 PIPE_CONTROL_CS_STALL
);
1037 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
1042 struct isl_surf isl_tmp
[2];
1043 struct blorp_surf surf
;
1044 blorp_surf_for_miptree(brw
, &surf
, mt
, true, false, 0,
1045 &level
, start_layer
, num_layers
, isl_tmp
);
1047 struct blorp_batch batch
;
1048 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1049 blorp_hiz_op(&batch
, &surf
, level
, start_layer
, num_layers
, op
);
1050 blorp_batch_finish(&batch
);
1052 /* The following stalls and flushes are only documented to be required for
1053 * HiZ clear operations. However, they also seem to be required for the
1054 * HiZ resolve operation which is basically the same as a fast clear only a
1055 * different value is written into the HiZ surface.
1057 if (op
== BLORP_HIZ_OP_DEPTH_CLEAR
|| op
== BLORP_HIZ_OP_HIZ_RESOLVE
) {
1058 if (brw
->gen
== 6) {
1059 /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
1061 * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be
1062 * followed by a PIPE_CONTROL command with DEPTH_STALL bit set
1063 * and Then followed by Depth FLUSH'
1065 brw_emit_pipe_control_flush(brw
,
1066 PIPE_CONTROL_DEPTH_STALL
);
1068 brw_emit_pipe_control_flush(brw
,
1069 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1070 PIPE_CONTROL_CS_STALL
);
1071 } else if (brw
->gen
>= 8) {
1073 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
1075 * "Depth buffer clear pass using any of the methods (WM_STATE,
1076 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
1077 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
1078 * "set" before starting to render. DepthStall and DepthFlush are
1079 * not needed between consecutive depth clear passes nor is it
1080 * required if the depth clear pass was done with
1081 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
1083 * TODO: Such as the spec says, this could be conditional.
1085 brw_emit_pipe_control_flush(brw
,
1086 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1087 PIPE_CONTROL_DEPTH_STALL
);