2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/blend.h"
27 #include "main/fbobject.h"
28 #include "main/renderbuffer.h"
29 #include "main/glformats.h"
31 #include "brw_blorp.h"
32 #include "brw_context.h"
33 #include "brw_defines.h"
34 #include "brw_meta_util.h"
35 #include "brw_state.h"
36 #include "intel_fbo.h"
37 #include "common/gen_debug.h"
39 #define FILE_DEBUG_FLAG DEBUG_BLORP
42 brw_blorp_lookup_shader(struct blorp_context
*blorp
,
43 const void *key
, uint32_t key_size
,
44 uint32_t *kernel_out
, void *prog_data_out
)
46 struct brw_context
*brw
= blorp
->driver_ctx
;
47 return brw_search_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
,
48 key
, key_size
, kernel_out
, prog_data_out
);
52 brw_blorp_upload_shader(struct blorp_context
*blorp
,
53 const void *key
, uint32_t key_size
,
54 const void *kernel
, uint32_t kernel_size
,
55 const struct brw_stage_prog_data
*prog_data
,
56 uint32_t prog_data_size
,
57 uint32_t *kernel_out
, void *prog_data_out
)
59 struct brw_context
*brw
= blorp
->driver_ctx
;
60 brw_upload_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
, key
, key_size
,
61 kernel
, kernel_size
, prog_data
, prog_data_size
,
62 kernel_out
, prog_data_out
);
67 brw_blorp_init(struct brw_context
*brw
)
69 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
71 blorp_init(&brw
->blorp
, brw
, &brw
->isl_dev
);
73 brw
->blorp
.compiler
= brw
->screen
->compiler
;
75 switch (devinfo
->gen
) {
77 if (devinfo
->is_g4x
) {
78 brw
->blorp
.exec
= gen45_blorp_exec
;
80 brw
->blorp
.exec
= gen4_blorp_exec
;
84 brw
->blorp
.exec
= gen5_blorp_exec
;
87 brw
->blorp
.mocs
.tex
= 0;
88 brw
->blorp
.mocs
.rb
= 0;
89 brw
->blorp
.mocs
.vb
= 0;
90 brw
->blorp
.exec
= gen6_blorp_exec
;
93 brw
->blorp
.mocs
.tex
= GEN7_MOCS_L3
;
94 brw
->blorp
.mocs
.rb
= GEN7_MOCS_L3
;
95 brw
->blorp
.mocs
.vb
= GEN7_MOCS_L3
;
96 if (devinfo
->is_haswell
) {
97 brw
->blorp
.exec
= gen75_blorp_exec
;
99 brw
->blorp
.exec
= gen7_blorp_exec
;
103 brw
->blorp
.mocs
.tex
= BDW_MOCS_WB
;
104 brw
->blorp
.mocs
.rb
= BDW_MOCS_PTE
;
105 brw
->blorp
.mocs
.vb
= BDW_MOCS_WB
;
106 brw
->blorp
.exec
= gen8_blorp_exec
;
109 brw
->blorp
.mocs
.tex
= SKL_MOCS_WB
;
110 brw
->blorp
.mocs
.rb
= SKL_MOCS_PTE
;
111 brw
->blorp
.mocs
.vb
= SKL_MOCS_WB
;
112 brw
->blorp
.exec
= gen9_blorp_exec
;
115 brw
->blorp
.mocs
.tex
= CNL_MOCS_WB
;
116 brw
->blorp
.mocs
.rb
= CNL_MOCS_PTE
;
117 brw
->blorp
.mocs
.vb
= CNL_MOCS_WB
;
118 brw
->blorp
.exec
= gen10_blorp_exec
;
121 unreachable("Invalid gen");
124 brw
->blorp
.lookup_shader
= brw_blorp_lookup_shader
;
125 brw
->blorp
.upload_shader
= brw_blorp_upload_shader
;
129 blorp_surf_for_miptree(struct brw_context
*brw
,
130 struct blorp_surf
*surf
,
131 struct intel_mipmap_tree
*mt
,
132 enum isl_aux_usage aux_usage
,
133 bool is_render_target
,
135 unsigned start_layer
, unsigned num_layers
,
136 struct isl_surf tmp_surfs
[1])
138 if (mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
) {
139 const unsigned num_samples
= mt
->surf
.samples
;
140 for (unsigned i
= 0; i
< num_layers
; i
++) {
141 for (unsigned s
= 0; s
< num_samples
; s
++) {
142 const unsigned phys_layer
= (start_layer
+ i
) * num_samples
+ s
;
143 intel_miptree_check_level_layer(mt
, *level
, phys_layer
);
147 for (unsigned i
= 0; i
< num_layers
; i
++)
148 intel_miptree_check_level_layer(mt
, *level
, start_layer
+ i
);
151 surf
->surf
= &mt
->surf
;
152 surf
->addr
= (struct blorp_address
) {
154 .offset
= mt
->offset
,
155 .reloc_flags
= is_render_target
? EXEC_OBJECT_WRITE
: 0,
158 surf
->aux_usage
= aux_usage
;
160 struct isl_surf
*aux_surf
= NULL
;
162 aux_surf
= &mt
->mcs_buf
->surf
;
163 else if (mt
->hiz_buf
)
164 aux_surf
= &mt
->hiz_buf
->surf
;
166 if (surf
->aux_usage
== ISL_AUX_USAGE_HIZ
&&
167 !intel_miptree_level_has_hiz(mt
, *level
))
168 surf
->aux_usage
= ISL_AUX_USAGE_NONE
;
170 if (surf
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
171 /* We only really need a clear color if we also have an auxiliary
172 * surface. Without one, it does nothing.
174 surf
->clear_color
= mt
->fast_clear_color
;
176 surf
->aux_surf
= aux_surf
;
177 surf
->aux_addr
= (struct blorp_address
) {
178 .reloc_flags
= is_render_target
? EXEC_OBJECT_WRITE
: 0,
182 surf
->aux_addr
.buffer
= mt
->mcs_buf
->bo
;
183 surf
->aux_addr
.offset
= mt
->mcs_buf
->offset
;
186 assert(surf
->aux_usage
== ISL_AUX_USAGE_HIZ
);
188 surf
->aux_addr
.buffer
= mt
->hiz_buf
->bo
;
189 surf
->aux_addr
.offset
= mt
->hiz_buf
->offset
;
192 surf
->aux_addr
= (struct blorp_address
) {
195 memset(&surf
->clear_color
, 0, sizeof(surf
->clear_color
));
197 assert((surf
->aux_usage
== ISL_AUX_USAGE_NONE
) ==
198 (surf
->aux_addr
.buffer
== NULL
));
200 /* ISL wants real levels, not offset ones. */
201 *level
-= mt
->first_level
;
204 static enum isl_format
205 brw_blorp_to_isl_format(struct brw_context
*brw
, mesa_format format
,
206 bool is_render_target
)
209 case MESA_FORMAT_NONE
:
210 return ISL_FORMAT_UNSUPPORTED
;
211 case MESA_FORMAT_S_UINT8
:
212 return ISL_FORMAT_R8_UINT
;
213 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
214 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
215 return ISL_FORMAT_R24_UNORM_X8_TYPELESS
;
216 case MESA_FORMAT_Z_FLOAT32
:
217 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
218 return ISL_FORMAT_R32_FLOAT
;
219 case MESA_FORMAT_Z_UNORM16
:
220 return ISL_FORMAT_R16_UNORM
;
222 if (is_render_target
) {
223 assert(brw
->mesa_format_supports_render
[format
]);
224 return brw
->mesa_to_isl_render_format
[format
];
226 return brw_isl_format_for_mesa_format(format
);
234 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
235 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
237 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
240 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
242 * which is simply adding 4 then modding by 8 (or anding with 7).
244 * We then may need to apply workarounds for textureGather hardware bugs.
246 static enum isl_channel_select
247 swizzle_to_scs(GLenum swizzle
)
249 return (enum isl_channel_select
)((swizzle
+ 4) & 7);
253 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
254 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
255 * the physical layer holding sample 0. So, for example, if
256 * src_mt->surf.samples == 4, then logical layer n corresponds to src_layer ==
260 brw_blorp_blit_miptrees(struct brw_context
*brw
,
261 struct intel_mipmap_tree
*src_mt
,
262 unsigned src_level
, unsigned src_layer
,
263 mesa_format src_format
, int src_swizzle
,
264 struct intel_mipmap_tree
*dst_mt
,
265 unsigned dst_level
, unsigned dst_layer
,
266 mesa_format dst_format
,
267 float src_x0
, float src_y0
,
268 float src_x1
, float src_y1
,
269 float dst_x0
, float dst_y0
,
270 float dst_x1
, float dst_y1
,
271 GLenum filter
, bool mirror_x
, bool mirror_y
,
272 bool decode_srgb
, bool encode_srgb
)
274 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
276 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
277 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
279 src_mt
->surf
.samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
280 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
281 dst_mt
->surf
.samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
282 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
285 if (!decode_srgb
&& _mesa_get_format_color_encoding(src_format
) == GL_SRGB
)
286 src_format
= _mesa_get_srgb_format_linear(src_format
);
288 if (!encode_srgb
&& _mesa_get_format_color_encoding(dst_format
) == GL_SRGB
)
289 dst_format
= _mesa_get_srgb_format_linear(dst_format
);
291 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
292 * texture, the above code configures the source format for L32_FLOAT or
293 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
294 * the SAMPLE message appears to handle multisampled L32_FLOAT and
295 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
296 * around the problem by using a source format of R32_FLOAT. This
297 * shouldn't affect rendering correctness, since the destination format is
298 * R32_FLOAT, so only the contents of the red channel matters.
300 if (devinfo
->gen
== 6 &&
301 src_mt
->surf
.samples
> 1 && dst_mt
->surf
.samples
<= 1 &&
302 src_mt
->format
== dst_mt
->format
&&
303 (dst_format
== MESA_FORMAT_L_FLOAT32
||
304 dst_format
== MESA_FORMAT_I_FLOAT32
)) {
305 src_format
= dst_format
= MESA_FORMAT_R_FLOAT32
;
308 enum isl_format src_isl_format
= brw_isl_format_for_mesa_format(src_format
);
309 enum isl_aux_usage src_aux_usage
=
310 intel_miptree_texture_aux_usage(brw
, src_mt
, src_isl_format
);
311 /* We do format workarounds for some depth formats so we can't reliably
312 * sample with HiZ. One of these days, we should fix that.
314 if (src_aux_usage
== ISL_AUX_USAGE_HIZ
)
315 src_aux_usage
= ISL_AUX_USAGE_NONE
;
316 const bool src_clear_supported
=
317 src_aux_usage
!= ISL_AUX_USAGE_NONE
&& src_mt
->format
== src_format
;
318 intel_miptree_prepare_access(brw
, src_mt
, src_level
, 1, src_layer
, 1,
319 src_aux_usage
, src_clear_supported
);
321 enum isl_aux_usage dst_aux_usage
=
322 intel_miptree_render_aux_usage(brw
, dst_mt
, encode_srgb
, false);
323 const bool dst_clear_supported
= dst_aux_usage
!= ISL_AUX_USAGE_NONE
;
324 intel_miptree_prepare_access(brw
, dst_mt
, dst_level
, 1, dst_layer
, 1,
325 dst_aux_usage
, dst_clear_supported
);
327 struct isl_surf tmp_surfs
[2];
328 struct blorp_surf src_surf
, dst_surf
;
329 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, src_aux_usage
, false,
330 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
331 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, dst_aux_usage
, true,
332 &dst_level
, dst_layer
, 1, &tmp_surfs
[1]);
334 struct isl_swizzle src_isl_swizzle
= {
335 .r
= swizzle_to_scs(GET_SWZ(src_swizzle
, 0)),
336 .g
= swizzle_to_scs(GET_SWZ(src_swizzle
, 1)),
337 .b
= swizzle_to_scs(GET_SWZ(src_swizzle
, 2)),
338 .a
= swizzle_to_scs(GET_SWZ(src_swizzle
, 3)),
341 struct blorp_batch batch
;
342 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
343 blorp_blit(&batch
, &src_surf
, src_level
, src_layer
,
344 brw_blorp_to_isl_format(brw
, src_format
, false), src_isl_swizzle
,
345 &dst_surf
, dst_level
, dst_layer
,
346 brw_blorp_to_isl_format(brw
, dst_format
, true),
347 ISL_SWIZZLE_IDENTITY
,
348 src_x0
, src_y0
, src_x1
, src_y1
,
349 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
350 filter
, mirror_x
, mirror_y
);
351 blorp_batch_finish(&batch
);
353 intel_miptree_finish_write(brw
, dst_mt
, dst_level
, dst_layer
, 1,
358 brw_blorp_copy_miptrees(struct brw_context
*brw
,
359 struct intel_mipmap_tree
*src_mt
,
360 unsigned src_level
, unsigned src_layer
,
361 struct intel_mipmap_tree
*dst_mt
,
362 unsigned dst_level
, unsigned dst_layer
,
363 unsigned src_x
, unsigned src_y
,
364 unsigned dst_x
, unsigned dst_y
,
365 unsigned src_width
, unsigned src_height
)
367 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
369 DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
370 "to %dx %s mt %p %d %d (%d,%d)\n",
372 src_mt
->surf
.samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
373 src_level
, src_layer
, src_x
, src_y
, src_width
, src_height
,
374 dst_mt
->surf
.samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
375 dst_level
, dst_layer
, dst_x
, dst_y
);
377 enum isl_aux_usage src_aux_usage
, dst_aux_usage
;
378 bool src_clear_supported
, dst_clear_supported
;
380 switch (src_mt
->aux_usage
) {
381 case ISL_AUX_USAGE_MCS
:
382 case ISL_AUX_USAGE_CCS_E
:
383 src_aux_usage
= src_mt
->aux_usage
;
384 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
385 * we're going to re-interpret the format as an integer format possibly
386 * with a different number of components, we can't handle clear colors
389 src_clear_supported
= devinfo
->gen
>= 9;
392 src_aux_usage
= ISL_AUX_USAGE_NONE
;
393 src_clear_supported
= false;
397 switch (dst_mt
->aux_usage
) {
398 case ISL_AUX_USAGE_MCS
:
399 case ISL_AUX_USAGE_CCS_E
:
400 dst_aux_usage
= dst_mt
->aux_usage
;
401 /* Prior to gen9, fast-clear only supported 0/1 clear colors. Since
402 * we're going to re-interpret the format as an integer format possibly
403 * with a different number of components, we can't handle clear colors
406 dst_clear_supported
= devinfo
->gen
>= 9;
409 dst_aux_usage
= ISL_AUX_USAGE_NONE
;
410 dst_clear_supported
= false;
414 intel_miptree_prepare_access(brw
, src_mt
, src_level
, 1, src_layer
, 1,
415 src_aux_usage
, src_clear_supported
);
416 intel_miptree_prepare_access(brw
, dst_mt
, dst_level
, 1, dst_layer
, 1,
417 dst_aux_usage
, dst_clear_supported
);
419 struct isl_surf tmp_surfs
[2];
420 struct blorp_surf src_surf
, dst_surf
;
421 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, src_aux_usage
, false,
422 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
423 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, dst_aux_usage
, true,
424 &dst_level
, dst_layer
, 1, &tmp_surfs
[1]);
426 struct blorp_batch batch
;
427 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
428 blorp_copy(&batch
, &src_surf
, src_level
, src_layer
,
429 &dst_surf
, dst_level
, dst_layer
,
430 src_x
, src_y
, dst_x
, dst_y
, src_width
, src_height
);
431 blorp_batch_finish(&batch
);
433 intel_miptree_finish_write(brw
, dst_mt
, dst_level
, dst_layer
, 1,
437 static struct intel_mipmap_tree
*
438 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
440 struct intel_mipmap_tree
*mt
= irb
->mt
;
441 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
447 blorp_get_texture_swizzle(const struct intel_renderbuffer
*irb
)
449 return irb
->Base
.Base
._BaseFormat
== GL_RGB
?
450 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ONE
) :
455 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
456 struct intel_renderbuffer
*src_irb
, mesa_format src_format
,
457 struct intel_renderbuffer
*dst_irb
, mesa_format dst_format
,
458 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
459 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
460 GLenum filter
, bool mirror_x
, bool mirror_y
)
462 const struct gl_context
*ctx
= &brw
->ctx
;
464 /* Find source/dst miptrees */
465 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
466 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
468 const bool do_srgb
= ctx
->Color
.sRGBEnabled
;
471 brw_blorp_blit_miptrees(brw
,
472 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
473 src_format
, blorp_get_texture_swizzle(src_irb
),
474 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
476 srcX0
, srcY0
, srcX1
, srcY1
,
477 dstX0
, dstY0
, dstX1
, dstY1
,
478 filter
, mirror_x
, mirror_y
,
481 dst_irb
->need_downsample
= true;
485 try_blorp_blit(struct brw_context
*brw
,
486 const struct gl_framebuffer
*read_fb
,
487 const struct gl_framebuffer
*draw_fb
,
488 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
489 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
490 GLenum filter
, GLbitfield buffer_bit
)
492 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
493 struct gl_context
*ctx
= &brw
->ctx
;
495 /* Sync up the state of window system buffers. We need to do this before
496 * we go looking for the buffers.
498 intel_prepare_render(brw
);
500 bool mirror_x
, mirror_y
;
501 if (brw_meta_mirror_clip_and_scissor(ctx
, read_fb
, draw_fb
,
502 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
503 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
504 &mirror_x
, &mirror_y
))
508 struct intel_renderbuffer
*src_irb
;
509 struct intel_renderbuffer
*dst_irb
;
510 struct intel_mipmap_tree
*src_mt
;
511 struct intel_mipmap_tree
*dst_mt
;
512 switch (buffer_bit
) {
513 case GL_COLOR_BUFFER_BIT
:
514 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
515 for (unsigned i
= 0; i
< draw_fb
->_NumColorDrawBuffers
; ++i
) {
516 dst_irb
= intel_renderbuffer(draw_fb
->_ColorDrawBuffers
[i
]);
518 do_blorp_blit(brw
, buffer_bit
,
519 src_irb
, src_irb
->Base
.Base
.Format
,
520 dst_irb
, dst_irb
->Base
.Base
.Format
,
521 srcX0
, srcY0
, srcX1
, srcY1
,
522 dstX0
, dstY0
, dstX1
, dstY1
,
523 filter
, mirror_x
, mirror_y
);
526 case GL_DEPTH_BUFFER_BIT
:
528 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
530 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
531 src_mt
= find_miptree(buffer_bit
, src_irb
);
532 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
534 /* We can't handle format conversions between Z24 and other formats
535 * since we have to lie about the surface format. See the comments in
536 * brw_blorp_surface_info::set().
538 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
539 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
))
542 /* We also can't handle any combined depth-stencil formats because we
543 * have to reinterpret as a color format.
545 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
546 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
549 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
550 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
551 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
552 filter
, mirror_x
, mirror_y
);
554 case GL_STENCIL_BUFFER_BIT
:
555 /* Blorp doesn't support combined depth stencil which is all we have
558 if (devinfo
->gen
< 6)
562 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
564 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
565 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
566 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
567 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
568 filter
, mirror_x
, mirror_y
);
571 unreachable("not reached");
578 brw_blorp_copytexsubimage(struct brw_context
*brw
,
579 struct gl_renderbuffer
*src_rb
,
580 struct gl_texture_image
*dst_image
,
582 int srcX0
, int srcY0
,
583 int dstX0
, int dstY0
,
584 int width
, int height
)
586 struct gl_context
*ctx
= &brw
->ctx
;
587 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
588 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
590 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
591 if (brw
->ctx
._ImageTransferState
)
594 /* Sync up the state of window system buffers. We need to do this before
595 * we go looking at the src renderbuffer's miptree.
597 intel_prepare_render(brw
);
599 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
600 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
602 /* There is support for only up to eight samples. */
603 if (src_mt
->surf
.samples
> 8 || dst_mt
->surf
.samples
> 8)
606 if (_mesa_get_format_base_format(src_rb
->Format
) !=
607 _mesa_get_format_base_format(dst_image
->TexFormat
)) {
611 /* We can't handle format conversions between Z24 and other formats since
612 * we have to lie about the surface format. See the comments in
613 * brw_blorp_surface_info::set().
615 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
616 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
)) {
620 /* We also can't handle any combined depth-stencil formats because we
621 * have to reinterpret as a color format.
623 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
624 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
627 if (!brw
->mesa_format_supports_render
[dst_image
->TexFormat
])
630 /* Source clipping shouldn't be necessary, since copytexsubimage (in
631 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
634 * Destination clipping shouldn't be necessary since the restrictions on
635 * glCopyTexSubImage prevent the user from specifying a destination rectangle
636 * that falls outside the bounds of the destination texture.
637 * See error_check_subtexture_dimensions().
640 int srcY1
= srcY0
+ height
;
641 int srcX1
= srcX0
+ width
;
642 int dstX1
= dstX0
+ width
;
643 int dstY1
= dstY0
+ height
;
645 /* Account for the fact that in the system framebuffer, the origin is at
648 bool mirror_y
= false;
649 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
650 GLint tmp
= src_rb
->Height
- srcY0
;
651 srcY0
= src_rb
->Height
- srcY1
;
656 /* Account for face selection and texture view MinLayer */
657 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
658 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
660 brw_blorp_blit_miptrees(brw
,
661 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
662 src_rb
->Format
, blorp_get_texture_swizzle(src_irb
),
663 dst_mt
, dst_level
, dst_slice
,
664 dst_image
->TexFormat
,
665 srcX0
, srcY0
, srcX1
, srcY1
,
666 dstX0
, dstY0
, dstX1
, dstY1
,
667 GL_NEAREST
, false, mirror_y
,
670 /* If we're copying to a packed depth stencil texture and the source
671 * framebuffer has separate stencil, we need to also copy the stencil data
674 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
675 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
677 src_irb
= intel_renderbuffer(src_rb
);
678 src_mt
= src_irb
->mt
;
680 if (src_mt
->stencil_mt
)
681 src_mt
= src_mt
->stencil_mt
;
682 if (dst_mt
->stencil_mt
)
683 dst_mt
= dst_mt
->stencil_mt
;
685 if (src_mt
!= dst_mt
) {
686 brw_blorp_blit_miptrees(brw
,
687 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
689 blorp_get_texture_swizzle(src_irb
),
690 dst_mt
, dst_level
, dst_slice
,
692 srcX0
, srcY0
, srcX1
, srcY1
,
693 dstX0
, dstY0
, dstX1
, dstY1
,
694 GL_NEAREST
, false, mirror_y
,
704 brw_blorp_framebuffer(struct brw_context
*brw
,
705 struct gl_framebuffer
*readFb
,
706 struct gl_framebuffer
*drawFb
,
707 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
708 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
709 GLbitfield mask
, GLenum filter
)
711 static GLbitfield buffer_bits
[] = {
714 GL_STENCIL_BUFFER_BIT
,
717 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
718 if ((mask
& buffer_bits
[i
]) &&
719 try_blorp_blit(brw
, readFb
, drawFb
,
720 srcX0
, srcY0
, srcX1
, srcY1
,
721 dstX0
, dstY0
, dstX1
, dstY1
,
722 filter
, buffer_bits
[i
])) {
723 mask
&= ~buffer_bits
[i
];
731 set_write_disables(const struct intel_renderbuffer
*irb
,
732 const GLubyte
*color_mask
, bool *color_write_disable
)
734 /* Format information in the renderbuffer represents the requirements
735 * given by the client. There are cases where the backing miptree uses,
736 * for example, RGBA to represent RGBX. Since the client is only expecting
737 * RGB we can treat alpha as not used and write whatever we like into it.
739 const GLenum base_format
= irb
->Base
.Base
._BaseFormat
;
740 const int components
= _mesa_base_format_component_count(base_format
);
741 bool disables
= false;
743 assert(components
> 0);
745 for (int i
= 0; i
< components
; i
++) {
746 color_write_disable
[i
] = !color_mask
[i
];
747 disables
= disables
|| !color_mask
[i
];
754 do_single_blorp_clear(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
755 struct gl_renderbuffer
*rb
, unsigned buf
,
756 bool partial_clear
, bool encode_srgb
)
758 struct gl_context
*ctx
= &brw
->ctx
;
759 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
760 uint32_t x0
, x1
, y0
, y1
;
762 mesa_format format
= irb
->Base
.Base
.Format
;
763 if (!encode_srgb
&& _mesa_get_format_color_encoding(format
) == GL_SRGB
)
764 format
= _mesa_get_srgb_format_linear(format
);
772 y0
= rb
->Height
- fb
->_Ymax
;
773 y1
= rb
->Height
- fb
->_Ymin
;
776 /* If the clear region is empty, just return. */
777 if (x0
== x1
|| y0
== y1
)
780 bool can_fast_clear
= !partial_clear
;
782 bool color_write_disable
[4] = { false, false, false, false };
783 if (set_write_disables(irb
, ctx
->Color
.ColorMask
[buf
], color_write_disable
))
784 can_fast_clear
= false;
786 /* We store clear colors as floats or uints as needed. If there are
787 * texture views in play, the formats will not properly be respected
788 * during resolves because the resolve operations only know about the
789 * miptree and not the renderbuffer.
791 if (irb
->Base
.Base
.Format
!= irb
->mt
->format
)
792 can_fast_clear
= false;
794 if (!irb
->mt
->supports_fast_clear
||
795 !brw_is_color_fast_clear_compatible(brw
, irb
->mt
, &ctx
->Color
.ClearColor
))
796 can_fast_clear
= false;
798 /* Surface state can only record one fast clear color value. Therefore
799 * unless different levels/layers agree on the color it can be used to
800 * represent only single level/layer. Here it will be reserved for the
801 * first slice (level 0, layer 0).
803 if (irb
->layer_count
> 1 || irb
->mt_level
|| irb
->mt_layer
)
804 can_fast_clear
= false;
806 unsigned level
= irb
->mt_level
;
807 const unsigned num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
809 /* If the MCS buffer hasn't been allocated yet, we need to allocate it now.
811 if (can_fast_clear
&& !irb
->mt
->mcs_buf
) {
812 assert(irb
->mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
813 if (!intel_miptree_alloc_ccs(brw
, irb
->mt
)) {
814 /* There are a few reasons in addition to out-of-memory, that can
815 * cause intel_miptree_alloc_non_msrt_mcs to fail. Try to recover by
816 * falling back to non-fast clear.
818 can_fast_clear
= false;
822 if (can_fast_clear
) {
823 const enum isl_aux_state aux_state
=
824 intel_miptree_get_aux_state(irb
->mt
, irb
->mt_level
, irb
->mt_layer
);
825 union isl_color_value clear_color
=
826 brw_meta_convert_fast_clear_color(brw
, irb
->mt
,
827 &ctx
->Color
.ClearColor
);
829 bool same_clear_color
= memcmp(&irb
->mt
->fast_clear_color
,
830 &clear_color
, sizeof(clear_color
)) == 0;
832 /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
833 * is redundant and can be skipped.
835 if (aux_state
== ISL_AUX_STATE_CLEAR
&& same_clear_color
)
838 irb
->mt
->fast_clear_color
= clear_color
;
840 /* If the clear color has changed, we need to emit a new SURFACE_STATE
841 * on the next draw call.
843 if (!same_clear_color
)
844 ctx
->NewDriverState
|= BRW_NEW_FAST_CLEAR_COLOR
;
846 DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__
,
847 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
849 /* We can't setup the blorp_surf until we've allocated the MCS above */
850 struct isl_surf isl_tmp
[2];
851 struct blorp_surf surf
;
852 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, irb
->mt
->aux_usage
, true,
853 &level
, irb
->mt_layer
, num_layers
, isl_tmp
);
855 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
857 * "Any transition from any value in {Clear, Render, Resolve} to a
858 * different value in {Clear, Render, Resolve} requires end of pipe
861 * In other words, fast clear ops are not properly synchronized with
862 * other drawing. We need to use a PIPE_CONTROL to ensure that the
863 * contents of the previous draw hit the render target before we resolve
864 * and again afterwards to ensure that the resolve is complete before we
865 * do any more regular drawing.
867 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
869 struct blorp_batch batch
;
870 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
871 blorp_fast_clear(&batch
, &surf
,
872 brw
->mesa_to_isl_render_format
[format
],
873 level
, irb
->mt_layer
, num_layers
,
875 blorp_batch_finish(&batch
);
877 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
879 /* Now that the fast clear has occurred, put the buffer in
880 * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
883 intel_miptree_set_aux_state(brw
, irb
->mt
, irb
->mt_level
,
884 irb
->mt_layer
, num_layers
,
885 ISL_AUX_STATE_CLEAR
);
887 DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__
,
888 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
890 enum isl_aux_usage aux_usage
=
891 intel_miptree_render_aux_usage(brw
, irb
->mt
, encode_srgb
, false);
892 intel_miptree_prepare_render(brw
, irb
->mt
, level
, irb
->mt_layer
,
893 num_layers
, encode_srgb
, false);
895 struct isl_surf isl_tmp
[2];
896 struct blorp_surf surf
;
897 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, aux_usage
, true,
898 &level
, irb
->mt_layer
, num_layers
, isl_tmp
);
900 union isl_color_value clear_color
;
901 memcpy(clear_color
.f32
, ctx
->Color
.ClearColor
.f
, sizeof(float) * 4);
903 struct blorp_batch batch
;
904 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
905 blorp_clear(&batch
, &surf
,
906 brw
->mesa_to_isl_render_format
[format
],
907 ISL_SWIZZLE_IDENTITY
,
908 level
, irb
->mt_layer
, num_layers
,
910 clear_color
, color_write_disable
);
911 blorp_batch_finish(&batch
);
913 intel_miptree_finish_render(brw
, irb
->mt
, level
, irb
->mt_layer
,
914 num_layers
, encode_srgb
, false);
921 brw_blorp_clear_color(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
922 GLbitfield mask
, bool partial_clear
, bool encode_srgb
)
924 for (unsigned buf
= 0; buf
< fb
->_NumColorDrawBuffers
; buf
++) {
925 struct gl_renderbuffer
*rb
= fb
->_ColorDrawBuffers
[buf
];
926 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
928 /* Only clear the buffers present in the provided mask */
929 if (((1 << fb
->_ColorDrawBufferIndexes
[buf
]) & mask
) == 0)
932 /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
933 * the framebuffer can be complete with some attachments missing. In
934 * this case the _ColorDrawBuffers pointer will be NULL.
939 do_single_blorp_clear(brw
, fb
, rb
, buf
, partial_clear
, encode_srgb
);
940 irb
->need_downsample
= true;
947 brw_blorp_clear_depth_stencil(struct brw_context
*brw
,
948 struct gl_framebuffer
*fb
,
949 GLbitfield mask
, bool partial_clear
)
951 const struct gl_context
*ctx
= &brw
->ctx
;
952 struct gl_renderbuffer
*depth_rb
=
953 fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
;
954 struct gl_renderbuffer
*stencil_rb
=
955 fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
957 if (!depth_rb
|| ctx
->Depth
.Mask
== GL_FALSE
)
958 mask
&= ~BUFFER_BIT_DEPTH
;
960 if (!stencil_rb
|| (ctx
->Stencil
.WriteMask
[0] & 0xff) == 0)
961 mask
&= ~BUFFER_BIT_STENCIL
;
963 if (!(mask
& (BUFFER_BITS_DEPTH_STENCIL
)))
966 uint32_t x0
, x1
, y0
, y1
, rb_name
, rb_height
;
968 rb_name
= depth_rb
->Name
;
969 rb_height
= depth_rb
->Height
;
971 assert(depth_rb
->Width
== stencil_rb
->Width
);
972 assert(depth_rb
->Height
== stencil_rb
->Height
);
976 rb_name
= stencil_rb
->Name
;
977 rb_height
= stencil_rb
->Height
;
986 y0
= rb_height
- fb
->_Ymax
;
987 y1
= rb_height
- fb
->_Ymin
;
990 /* If the clear region is empty, just return. */
991 if (x0
== x1
|| y0
== y1
)
994 uint32_t level
, start_layer
, num_layers
;
995 struct isl_surf isl_tmp
[4];
996 struct blorp_surf depth_surf
, stencil_surf
;
998 struct intel_mipmap_tree
*depth_mt
= NULL
;
999 if (mask
& BUFFER_BIT_DEPTH
) {
1000 struct intel_renderbuffer
*irb
= intel_renderbuffer(depth_rb
);
1001 depth_mt
= find_miptree(GL_DEPTH_BUFFER_BIT
, irb
);
1003 level
= irb
->mt_level
;
1004 start_layer
= irb
->mt_layer
;
1005 num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1007 intel_miptree_prepare_depth(brw
, depth_mt
, level
,
1008 start_layer
, num_layers
);
1010 unsigned depth_level
= level
;
1011 blorp_surf_for_miptree(brw
, &depth_surf
, depth_mt
, depth_mt
->aux_usage
,
1012 true, &depth_level
, start_layer
, num_layers
,
1014 assert(depth_level
== level
);
1017 uint8_t stencil_mask
= 0;
1018 struct intel_mipmap_tree
*stencil_mt
= NULL
;
1019 if (mask
& BUFFER_BIT_STENCIL
) {
1020 struct intel_renderbuffer
*irb
= intel_renderbuffer(stencil_rb
);
1021 stencil_mt
= find_miptree(GL_STENCIL_BUFFER_BIT
, irb
);
1023 if (mask
& BUFFER_BIT_DEPTH
) {
1024 assert(level
== irb
->mt_level
);
1025 assert(start_layer
== irb
->mt_layer
);
1026 assert(num_layers
== fb
->MaxNumLayers
? irb
->layer_count
: 1);
1028 level
= irb
->mt_level
;
1029 start_layer
= irb
->mt_layer
;
1030 num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
1033 stencil_mask
= ctx
->Stencil
.WriteMask
[0] & 0xff;
1035 intel_miptree_prepare_access(brw
, stencil_mt
, level
, 1,
1036 start_layer
, num_layers
,
1037 ISL_AUX_USAGE_NONE
, false);
1039 unsigned stencil_level
= level
;
1040 blorp_surf_for_miptree(brw
, &stencil_surf
, stencil_mt
,
1041 ISL_AUX_USAGE_NONE
, true,
1042 &stencil_level
, start_layer
, num_layers
,
1046 assert((mask
& BUFFER_BIT_DEPTH
) || stencil_mask
);
1048 struct blorp_batch batch
;
1049 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1050 blorp_clear_depth_stencil(&batch
, &depth_surf
, &stencil_surf
,
1051 level
, start_layer
, num_layers
,
1053 (mask
& BUFFER_BIT_DEPTH
), ctx
->Depth
.Clear
,
1054 stencil_mask
, ctx
->Stencil
.Clear
);
1055 blorp_batch_finish(&batch
);
1057 if (mask
& BUFFER_BIT_DEPTH
) {
1058 intel_miptree_finish_depth(brw
, depth_mt
, level
,
1059 start_layer
, num_layers
, true);
1063 intel_miptree_finish_write(brw
, stencil_mt
, level
,
1064 start_layer
, num_layers
,
1065 ISL_AUX_USAGE_NONE
);
1070 brw_blorp_resolve_color(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1071 unsigned level
, unsigned layer
,
1072 enum blorp_fast_clear_op resolve_op
)
1074 DBG("%s to mt %p level %u layer %u\n", __FUNCTION__
, mt
, level
, layer
);
1076 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
1078 struct isl_surf isl_tmp
[1];
1079 struct blorp_surf surf
;
1080 blorp_surf_for_miptree(brw
, &surf
, mt
, mt
->aux_usage
, true,
1081 &level
, layer
, 1 /* num_layers */,
1084 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1086 * "Any transition from any value in {Clear, Render, Resolve} to a
1087 * different value in {Clear, Render, Resolve} requires end of pipe
1090 * In other words, fast clear ops are not properly synchronized with
1091 * other drawing. We need to use a PIPE_CONTROL to ensure that the
1092 * contents of the previous draw hit the render target before we resolve
1093 * and again afterwards to ensure that the resolve is complete before we
1094 * do any more regular drawing.
1096 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1099 struct blorp_batch batch
;
1100 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1101 blorp_ccs_resolve(&batch
, &surf
, level
, layer
,
1102 brw_blorp_to_isl_format(brw
, format
, true),
1104 blorp_batch_finish(&batch
);
1106 /* See comment above */
1107 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1111 brw_blorp_mcs_partial_resolve(struct brw_context
*brw
,
1112 struct intel_mipmap_tree
*mt
,
1113 uint32_t start_layer
, uint32_t num_layers
)
1115 DBG("%s to mt %p layers %u-%u\n", __FUNCTION__
, mt
,
1116 start_layer
, start_layer
+ num_layers
- 1);
1118 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1120 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
1121 enum isl_format isl_format
= brw_blorp_to_isl_format(brw
, format
, true);
1123 struct isl_surf isl_tmp
[1];
1124 struct blorp_surf surf
;
1126 blorp_surf_for_miptree(brw
, &surf
, mt
, ISL_AUX_USAGE_MCS
, true,
1127 &level
, start_layer
, num_layers
, isl_tmp
);
1129 struct blorp_batch batch
;
1130 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1131 blorp_mcs_partial_resolve(&batch
, &surf
, isl_format
,
1132 start_layer
, num_layers
);
1133 blorp_batch_finish(&batch
);
1137 * Perform a HiZ or depth resolve operation.
1139 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
1140 * PRM, Volume 1, Part 2:
1141 * - 7.5.3.1 Depth Buffer Clear
1142 * - 7.5.3.2 Depth Buffer Resolve
1143 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1146 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1147 unsigned int level
, unsigned int start_layer
,
1148 unsigned int num_layers
, enum blorp_hiz_op op
)
1150 assert(intel_miptree_level_has_hiz(mt
, level
));
1151 assert(op
!= BLORP_HIZ_OP_NONE
);
1152 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1153 const char *opname
= NULL
;
1156 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
1157 opname
= "depth resolve";
1159 case BLORP_HIZ_OP_HIZ_RESOLVE
:
1160 opname
= "hiz ambiguate";
1162 case BLORP_HIZ_OP_DEPTH_CLEAR
:
1163 opname
= "depth clear";
1165 case BLORP_HIZ_OP_NONE
:
1170 DBG("%s %s to mt %p level %d layers %d-%d\n",
1171 __func__
, opname
, mt
, level
, start_layer
, start_layer
+ num_layers
- 1);
1173 /* The following stalls and flushes are only documented to be required for
1174 * HiZ clear operations. However, they also seem to be required for
1175 * resolve operations.
1177 if (devinfo
->gen
== 6) {
1178 /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
1180 * "If other rendering operations have preceded this clear, a
1181 * PIPE_CONTROL with write cache flush enabled and Z-inhibit
1182 * disabled must be issued before the rectangle primitive used for
1183 * the depth buffer clear operation.
1185 brw_emit_pipe_control_flush(brw
,
1186 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1187 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1188 PIPE_CONTROL_CS_STALL
);
1189 } else if (devinfo
->gen
>= 7) {
1191 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
1193 * If other rendering operations have preceded this clear, a
1194 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
1195 * enabled must be issued before the rectangle primitive used for
1196 * the depth buffer clear operation.
1198 * Same applies for Gen8 and Gen9.
1200 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
1201 * PIPE_CONTROL, Depth Cache Flush Enable:
1203 * This bit must not be set when Depth Stall Enable bit is set in
1206 * This is confirmed to hold for real, HSW gets immediate gpu hangs.
1208 * Therefore issue two pipe control flushes, one for cache flush and
1209 * another for depth stall.
1211 brw_emit_pipe_control_flush(brw
,
1212 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1213 PIPE_CONTROL_CS_STALL
);
1215 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
1218 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
&& mt
->hiz_buf
);
1220 struct isl_surf isl_tmp
[2];
1221 struct blorp_surf surf
;
1222 blorp_surf_for_miptree(brw
, &surf
, mt
, ISL_AUX_USAGE_HIZ
, true,
1223 &level
, start_layer
, num_layers
, isl_tmp
);
1225 struct blorp_batch batch
;
1226 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1227 blorp_hiz_op(&batch
, &surf
, level
, start_layer
, num_layers
, op
);
1228 blorp_batch_finish(&batch
);
1230 /* The following stalls and flushes are only documented to be required for
1231 * HiZ clear operations. However, they also seem to be required for
1232 * resolve operations.
1234 if (devinfo
->gen
== 6) {
1235 /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
1237 * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be
1238 * followed by a PIPE_CONTROL command with DEPTH_STALL bit set
1239 * and Then followed by Depth FLUSH'
1241 brw_emit_pipe_control_flush(brw
,
1242 PIPE_CONTROL_DEPTH_STALL
);
1244 brw_emit_pipe_control_flush(brw
,
1245 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1246 PIPE_CONTROL_CS_STALL
);
1247 } else if (devinfo
->gen
>= 8) {
1249 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
1251 * "Depth buffer clear pass using any of the methods (WM_STATE,
1252 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
1253 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
1254 * "set" before starting to render. DepthStall and DepthFlush are
1255 * not needed between consecutive depth clear passes nor is it
1256 * required if the depth clear pass was done with
1257 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
1259 * TODO: Such as the spec says, this could be conditional.
1261 brw_emit_pipe_control_flush(brw
,
1262 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1263 PIPE_CONTROL_DEPTH_STALL
);