2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/blend.h"
27 #include "main/fbobject.h"
28 #include "main/renderbuffer.h"
29 #include "main/glformats.h"
31 #include "brw_blorp.h"
32 #include "brw_context.h"
33 #include "brw_defines.h"
34 #include "brw_meta_util.h"
35 #include "brw_state.h"
36 #include "intel_fbo.h"
37 #include "intel_debug.h"
39 #define FILE_DEBUG_FLAG DEBUG_BLORP
42 brw_blorp_lookup_shader(struct blorp_context
*blorp
,
43 const void *key
, uint32_t key_size
,
44 uint32_t *kernel_out
, void *prog_data_out
)
46 struct brw_context
*brw
= blorp
->driver_ctx
;
47 return brw_search_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
,
48 key
, key_size
, kernel_out
, prog_data_out
);
52 brw_blorp_upload_shader(struct blorp_context
*blorp
,
53 const void *key
, uint32_t key_size
,
54 const void *kernel
, uint32_t kernel_size
,
55 const void *prog_data
, uint32_t prog_data_size
,
56 uint32_t *kernel_out
, void *prog_data_out
)
58 struct brw_context
*brw
= blorp
->driver_ctx
;
59 brw_upload_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
, key
, key_size
,
60 kernel
, kernel_size
, prog_data
, prog_data_size
,
61 kernel_out
, prog_data_out
);
65 brw_blorp_init(struct brw_context
*brw
)
67 blorp_init(&brw
->blorp
, brw
, &brw
->isl_dev
);
69 brw
->blorp
.compiler
= brw
->intelScreen
->compiler
;
73 brw
->blorp
.mocs
.tex
= 0;
74 brw
->blorp
.mocs
.rb
= 0;
75 brw
->blorp
.mocs
.vb
= 0;
76 brw
->blorp
.exec
= gen6_blorp_exec
;
79 brw
->blorp
.mocs
.tex
= GEN7_MOCS_L3
;
80 brw
->blorp
.mocs
.rb
= GEN7_MOCS_L3
;
81 brw
->blorp
.mocs
.vb
= GEN7_MOCS_L3
;
82 if (brw
->is_haswell
) {
83 brw
->blorp
.exec
= gen75_blorp_exec
;
85 brw
->blorp
.exec
= gen7_blorp_exec
;
89 brw
->blorp
.mocs
.tex
= BDW_MOCS_WB
;
90 brw
->blorp
.mocs
.rb
= BDW_MOCS_PTE
;
91 brw
->blorp
.mocs
.vb
= BDW_MOCS_WB
;
92 brw
->blorp
.exec
= gen8_blorp_exec
;
95 brw
->blorp
.mocs
.tex
= SKL_MOCS_WB
;
96 brw
->blorp
.mocs
.rb
= SKL_MOCS_PTE
;
97 brw
->blorp
.mocs
.vb
= SKL_MOCS_WB
;
98 brw
->blorp
.exec
= gen9_blorp_exec
;
101 unreachable("Invalid gen");
104 brw
->blorp
.lookup_shader
= brw_blorp_lookup_shader
;
105 brw
->blorp
.upload_shader
= brw_blorp_upload_shader
;
109 apply_gen6_stencil_hiz_offset(struct isl_surf
*surf
,
110 struct intel_mipmap_tree
*mt
,
114 assert(mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
);
116 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
117 /* Note: we can't compute the stencil offset using
118 * intel_miptree_get_aligned_offset(), because the miptree
119 * claims that the region is untiled even though it's W tiled.
121 *offset
= mt
->level
[lod
].level_y
* mt
->pitch
+
122 mt
->level
[lod
].level_x
* 64;
124 *offset
= intel_miptree_get_aligned_offset(mt
,
125 mt
->level
[lod
].level_x
,
126 mt
->level
[lod
].level_y
,
130 surf
->logical_level0_px
.width
= minify(surf
->logical_level0_px
.width
, lod
);
131 surf
->logical_level0_px
.height
= minify(surf
->logical_level0_px
.height
, lod
);
132 surf
->phys_level0_sa
.width
= minify(surf
->phys_level0_sa
.width
, lod
);
133 surf
->phys_level0_sa
.height
= minify(surf
->phys_level0_sa
.height
, lod
);
135 surf
->array_pitch_el_rows
=
136 ALIGN(surf
->phys_level0_sa
.height
, surf
->image_alignment_el
.height
);
140 blorp_surf_for_miptree(struct brw_context
*brw
,
141 struct blorp_surf
*surf
,
142 struct intel_mipmap_tree
*mt
,
143 bool is_render_target
,
145 struct isl_surf tmp_surfs
[2])
147 intel_miptree_get_isl_surf(brw
, mt
, &tmp_surfs
[0]);
148 surf
->surf
= &tmp_surfs
[0];
149 surf
->addr
= (struct blorp_address
) {
151 .offset
= mt
->offset
,
152 .read_domains
= is_render_target
? I915_GEM_DOMAIN_RENDER
:
153 I915_GEM_DOMAIN_SAMPLER
,
154 .write_domain
= is_render_target
? I915_GEM_DOMAIN_RENDER
: 0,
157 if (brw
->gen
== 6 && mt
->format
== MESA_FORMAT_S_UINT8
&&
158 mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
159 /* Sandy bridge stencil and HiZ use this ALL_SLICES_AT_EACH_LOD hack in
160 * order to allow for layered rendering. The hack makes each LOD of the
161 * stencil or HiZ buffer a single tightly packed array surface at some
162 * offset into the surface. Since ISL doesn't know how to deal with the
163 * crazy ALL_SLICES_AT_EACH_LOD layout and since we have to do a manual
164 * offset of it anyway, we might as well do the offset here and keep the
165 * hacks inside the i965 driver.
167 * See also gen6_depth_stencil_state.c
170 apply_gen6_stencil_hiz_offset(&tmp_surfs
[0], mt
, *level
, &offset
);
171 surf
->addr
.offset
+= offset
;
175 struct isl_surf
*aux_surf
= &tmp_surfs
[1];
176 intel_miptree_get_aux_isl_surf(brw
, mt
, aux_surf
, &surf
->aux_usage
);
178 /* For textures that are in the RESOLVED state, we ignore the MCS */
179 if (mt
->mcs_mt
&& !is_render_target
&&
180 mt
->fast_clear_state
== INTEL_FAST_CLEAR_STATE_RESOLVED
)
181 surf
->aux_usage
= ISL_AUX_USAGE_NONE
;
183 if (surf
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
184 /* We only really need a clear color if we also have an auxiliary
185 * surface. Without one, it does nothing.
187 surf
->clear_color
= intel_miptree_get_isl_clear_color(brw
, mt
);
189 surf
->aux_surf
= aux_surf
;
190 surf
->aux_addr
= (struct blorp_address
) {
191 .read_domains
= is_render_target
? I915_GEM_DOMAIN_RENDER
:
192 I915_GEM_DOMAIN_SAMPLER
,
193 .write_domain
= is_render_target
? I915_GEM_DOMAIN_RENDER
: 0,
197 surf
->aux_addr
.buffer
= mt
->mcs_mt
->bo
;
198 surf
->aux_addr
.offset
= mt
->mcs_mt
->offset
;
200 assert(surf
->aux_usage
== ISL_AUX_USAGE_HIZ
);
201 struct intel_mipmap_tree
*hiz_mt
= mt
->hiz_buf
->mt
;
203 surf
->aux_addr
.buffer
= hiz_mt
->bo
;
205 hiz_mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
206 /* gen6 requires the HiZ buffer to be manually offset to the
207 * right location. We could fixup the surf but it doesn't
208 * matter since most of those fields don't matter.
210 apply_gen6_stencil_hiz_offset(aux_surf
, hiz_mt
, *level
,
211 &surf
->aux_addr
.offset
);
213 surf
->aux_addr
.offset
= 0;
215 assert(hiz_mt
->pitch
== aux_surf
->row_pitch
);
217 surf
->aux_addr
.buffer
= mt
->hiz_buf
->bo
;
218 surf
->aux_addr
.offset
= 0;
222 surf
->aux_addr
= (struct blorp_address
) {
225 memset(&surf
->clear_color
, 0, sizeof(surf
->clear_color
));
227 assert((surf
->aux_usage
== ISL_AUX_USAGE_NONE
) ==
228 (surf
->aux_addr
.buffer
== NULL
));
231 static enum isl_format
232 brw_blorp_to_isl_format(struct brw_context
*brw
, mesa_format format
,
233 bool is_render_target
)
236 case MESA_FORMAT_NONE
:
237 return ISL_FORMAT_UNSUPPORTED
;
238 case MESA_FORMAT_S_UINT8
:
239 return ISL_FORMAT_R8_UINT
;
240 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
241 return ISL_FORMAT_R24_UNORM_X8_TYPELESS
;
242 case MESA_FORMAT_Z_FLOAT32
:
243 return ISL_FORMAT_R32_FLOAT
;
244 case MESA_FORMAT_Z_UNORM16
:
245 return ISL_FORMAT_R16_UNORM
;
247 if (is_render_target
) {
248 assert(brw
->format_supported_as_render_target
[format
]);
249 return brw
->render_target_format
[format
];
251 return brw_format_for_mesa_format(format
);
259 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
260 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
261 * the physical layer holding sample 0. So, for example, if
262 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
266 brw_blorp_blit_miptrees(struct brw_context
*brw
,
267 struct intel_mipmap_tree
*src_mt
,
268 unsigned src_level
, unsigned src_layer
,
269 mesa_format src_format
, int src_swizzle
,
270 struct intel_mipmap_tree
*dst_mt
,
271 unsigned dst_level
, unsigned dst_layer
,
272 mesa_format dst_format
,
273 float src_x0
, float src_y0
,
274 float src_x1
, float src_y1
,
275 float dst_x0
, float dst_y0
,
276 float dst_x1
, float dst_y1
,
277 GLenum filter
, bool mirror_x
, bool mirror_y
,
278 bool decode_srgb
, bool encode_srgb
)
280 /* Get ready to blit. This includes depth resolving the src and dst
281 * buffers if necessary. Note: it's not necessary to do a color resolve on
282 * the destination buffer because we use the standard render path to render
283 * to destination color buffers, and the standard render path is
286 intel_miptree_resolve_color(brw
, src_mt
, INTEL_MIPTREE_IGNORE_CCS_E
);
287 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_layer
);
288 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_layer
);
290 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
291 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
293 src_mt
->num_samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
294 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
295 dst_mt
->num_samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
296 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
299 if (!decode_srgb
&& _mesa_get_format_color_encoding(src_format
) == GL_SRGB
)
300 src_format
= _mesa_get_srgb_format_linear(src_format
);
302 if (!encode_srgb
&& _mesa_get_format_color_encoding(dst_format
) == GL_SRGB
)
303 dst_format
= _mesa_get_srgb_format_linear(dst_format
);
305 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
306 * texture, the above code configures the source format for L32_FLOAT or
307 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
308 * the SAMPLE message appears to handle multisampled L32_FLOAT and
309 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
310 * around the problem by using a source format of R32_FLOAT. This
311 * shouldn't affect rendering correctness, since the destination format is
312 * R32_FLOAT, so only the contents of the red channel matters.
315 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1 &&
316 src_mt
->format
== dst_mt
->format
&&
317 (dst_format
== MESA_FORMAT_L_FLOAT32
||
318 dst_format
== MESA_FORMAT_I_FLOAT32
)) {
319 src_format
= dst_format
= MESA_FORMAT_R_FLOAT32
;
322 intel_miptree_check_level_layer(src_mt
, src_level
, src_layer
);
323 intel_miptree_check_level_layer(dst_mt
, dst_level
, dst_layer
);
324 intel_miptree_used_for_rendering(dst_mt
);
326 struct isl_surf tmp_surfs
[4];
327 struct blorp_surf src_surf
, dst_surf
;
328 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, false,
329 &src_level
, &tmp_surfs
[0]);
330 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, true,
331 &dst_level
, &tmp_surfs
[2]);
333 struct blorp_batch batch
;
334 blorp_batch_init(&brw
->blorp
, &batch
, brw
);
335 blorp_blit(&batch
, &src_surf
, src_level
, src_layer
,
336 brw_blorp_to_isl_format(brw
, src_format
, false), src_swizzle
,
337 &dst_surf
, dst_level
, dst_layer
,
338 brw_blorp_to_isl_format(brw
, dst_format
, true),
339 src_x0
, src_y0
, src_x1
, src_y1
,
340 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
341 filter
, mirror_x
, mirror_y
);
342 blorp_batch_finish(&batch
);
344 intel_miptree_slice_set_needs_hiz_resolve(dst_mt
, dst_level
, dst_layer
);
346 if (intel_miptree_is_lossless_compressed(brw
, dst_mt
))
347 dst_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_UNRESOLVED
;
350 static struct intel_mipmap_tree
*
351 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
353 struct intel_mipmap_tree
*mt
= irb
->mt
;
354 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
360 blorp_get_texture_swizzle(const struct intel_renderbuffer
*irb
)
362 return irb
->Base
.Base
._BaseFormat
== GL_RGB
?
363 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ONE
) :
368 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
369 struct intel_renderbuffer
*src_irb
, mesa_format src_format
,
370 struct intel_renderbuffer
*dst_irb
, mesa_format dst_format
,
371 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
372 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
373 GLenum filter
, bool mirror_x
, bool mirror_y
)
375 const struct gl_context
*ctx
= &brw
->ctx
;
377 /* Find source/dst miptrees */
378 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
379 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
381 const bool do_srgb
= ctx
->Color
.sRGBEnabled
;
384 brw_blorp_blit_miptrees(brw
,
385 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
386 src_format
, blorp_get_texture_swizzle(src_irb
),
387 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
389 srcX0
, srcY0
, srcX1
, srcY1
,
390 dstX0
, dstY0
, dstX1
, dstY1
,
391 filter
, mirror_x
, mirror_y
,
394 dst_irb
->need_downsample
= true;
398 try_blorp_blit(struct brw_context
*brw
,
399 const struct gl_framebuffer
*read_fb
,
400 const struct gl_framebuffer
*draw_fb
,
401 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
402 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
403 GLenum filter
, GLbitfield buffer_bit
)
405 struct gl_context
*ctx
= &brw
->ctx
;
407 /* Sync up the state of window system buffers. We need to do this before
408 * we go looking for the buffers.
410 intel_prepare_render(brw
);
412 bool mirror_x
, mirror_y
;
413 if (brw_meta_mirror_clip_and_scissor(ctx
, read_fb
, draw_fb
,
414 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
415 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
416 &mirror_x
, &mirror_y
))
420 struct intel_renderbuffer
*src_irb
;
421 struct intel_renderbuffer
*dst_irb
;
422 struct intel_mipmap_tree
*src_mt
;
423 struct intel_mipmap_tree
*dst_mt
;
424 switch (buffer_bit
) {
425 case GL_COLOR_BUFFER_BIT
:
426 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
427 for (unsigned i
= 0; i
< draw_fb
->_NumColorDrawBuffers
; ++i
) {
428 dst_irb
= intel_renderbuffer(draw_fb
->_ColorDrawBuffers
[i
]);
430 do_blorp_blit(brw
, buffer_bit
,
431 src_irb
, src_irb
->Base
.Base
.Format
,
432 dst_irb
, dst_irb
->Base
.Base
.Format
,
433 srcX0
, srcY0
, srcX1
, srcY1
,
434 dstX0
, dstY0
, dstX1
, dstY1
,
435 filter
, mirror_x
, mirror_y
);
438 case GL_DEPTH_BUFFER_BIT
:
440 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
442 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
443 src_mt
= find_miptree(buffer_bit
, src_irb
);
444 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
446 /* We can't handle format conversions between Z24 and other formats
447 * since we have to lie about the surface format. See the comments in
448 * brw_blorp_surface_info::set().
450 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
451 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
))
454 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
455 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
456 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
457 filter
, mirror_x
, mirror_y
);
459 case GL_STENCIL_BUFFER_BIT
:
461 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
463 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
464 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
465 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
466 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
467 filter
, mirror_x
, mirror_y
);
470 unreachable("not reached");
477 brw_blorp_copytexsubimage(struct brw_context
*brw
,
478 struct gl_renderbuffer
*src_rb
,
479 struct gl_texture_image
*dst_image
,
481 int srcX0
, int srcY0
,
482 int dstX0
, int dstY0
,
483 int width
, int height
)
485 struct gl_context
*ctx
= &brw
->ctx
;
486 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
487 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
489 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
490 if (brw
->ctx
._ImageTransferState
)
493 /* Sync up the state of window system buffers. We need to do this before
494 * we go looking at the src renderbuffer's miptree.
496 intel_prepare_render(brw
);
498 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
499 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
501 /* There is support for only up to eight samples. */
502 if (src_mt
->num_samples
> 8 || dst_mt
->num_samples
> 8)
505 /* BLORP is only supported from Gen6 onwards. */
509 if (_mesa_get_format_base_format(src_rb
->Format
) !=
510 _mesa_get_format_base_format(dst_image
->TexFormat
)) {
514 /* We can't handle format conversions between Z24 and other formats since
515 * we have to lie about the surface format. See the comments in
516 * brw_blorp_surface_info::set().
518 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
519 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
)) {
523 if (!brw
->format_supported_as_render_target
[dst_image
->TexFormat
])
526 /* Source clipping shouldn't be necessary, since copytexsubimage (in
527 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
530 * Destination clipping shouldn't be necessary since the restrictions on
531 * glCopyTexSubImage prevent the user from specifying a destination rectangle
532 * that falls outside the bounds of the destination texture.
533 * See error_check_subtexture_dimensions().
536 int srcY1
= srcY0
+ height
;
537 int srcX1
= srcX0
+ width
;
538 int dstX1
= dstX0
+ width
;
539 int dstY1
= dstY0
+ height
;
541 /* Account for the fact that in the system framebuffer, the origin is at
544 bool mirror_y
= false;
545 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
546 GLint tmp
= src_rb
->Height
- srcY0
;
547 srcY0
= src_rb
->Height
- srcY1
;
552 /* Account for face selection and texture view MinLayer */
553 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
554 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
556 brw_blorp_blit_miptrees(brw
,
557 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
558 src_rb
->Format
, blorp_get_texture_swizzle(src_irb
),
559 dst_mt
, dst_level
, dst_slice
,
560 dst_image
->TexFormat
,
561 srcX0
, srcY0
, srcX1
, srcY1
,
562 dstX0
, dstY0
, dstX1
, dstY1
,
563 GL_NEAREST
, false, mirror_y
,
566 /* If we're copying to a packed depth stencil texture and the source
567 * framebuffer has separate stencil, we need to also copy the stencil data
570 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
571 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
573 src_irb
= intel_renderbuffer(src_rb
);
574 src_mt
= src_irb
->mt
;
576 if (src_mt
->stencil_mt
)
577 src_mt
= src_mt
->stencil_mt
;
578 if (dst_mt
->stencil_mt
)
579 dst_mt
= dst_mt
->stencil_mt
;
581 if (src_mt
!= dst_mt
) {
582 brw_blorp_blit_miptrees(brw
,
583 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
585 blorp_get_texture_swizzle(src_irb
),
586 dst_mt
, dst_level
, dst_slice
,
588 srcX0
, srcY0
, srcX1
, srcY1
,
589 dstX0
, dstY0
, dstX1
, dstY1
,
590 GL_NEAREST
, false, mirror_y
,
600 brw_blorp_framebuffer(struct brw_context
*brw
,
601 struct gl_framebuffer
*readFb
,
602 struct gl_framebuffer
*drawFb
,
603 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
604 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
605 GLbitfield mask
, GLenum filter
)
607 /* BLORP is not supported before Gen6. */
611 static GLbitfield buffer_bits
[] = {
614 GL_STENCIL_BUFFER_BIT
,
617 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
618 if ((mask
& buffer_bits
[i
]) &&
619 try_blorp_blit(brw
, readFb
, drawFb
,
620 srcX0
, srcY0
, srcX1
, srcY1
,
621 dstX0
, dstY0
, dstX1
, dstY1
,
622 filter
, buffer_bits
[i
])) {
623 mask
&= ~buffer_bits
[i
];
631 set_write_disables(const struct intel_renderbuffer
*irb
,
632 const GLubyte
*color_mask
, bool *color_write_disable
)
634 /* Format information in the renderbuffer represents the requirements
635 * given by the client. There are cases where the backing miptree uses,
636 * for example, RGBA to represent RGBX. Since the client is only expecting
637 * RGB we can treat alpha as not used and write whatever we like into it.
639 const GLenum base_format
= irb
->Base
.Base
._BaseFormat
;
640 const int components
= _mesa_base_format_component_count(base_format
);
641 bool disables
= false;
643 assert(components
> 0);
645 for (int i
= 0; i
< components
; i
++) {
646 color_write_disable
[i
] = !color_mask
[i
];
647 disables
= disables
|| !color_mask
[i
];
654 do_single_blorp_clear(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
655 struct gl_renderbuffer
*rb
, unsigned buf
,
656 bool partial_clear
, bool encode_srgb
, unsigned layer
)
658 struct gl_context
*ctx
= &brw
->ctx
;
659 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
660 mesa_format format
= irb
->mt
->format
;
661 uint32_t x0
, x1
, y0
, y1
;
663 if (!encode_srgb
&& _mesa_get_format_color_encoding(format
) == GL_SRGB
)
664 format
= _mesa_get_srgb_format_linear(format
);
672 y0
= rb
->Height
- fb
->_Ymax
;
673 y1
= rb
->Height
- fb
->_Ymin
;
676 /* If the clear region is empty, just return. */
677 if (x0
== x1
|| y0
== y1
)
680 bool can_fast_clear
= !partial_clear
;
682 bool color_write_disable
[4] = { false, false, false, false };
683 if (set_write_disables(irb
, ctx
->Color
.ColorMask
[buf
], color_write_disable
))
684 can_fast_clear
= false;
686 if (irb
->mt
->fast_clear_state
== INTEL_FAST_CLEAR_STATE_NO_MCS
||
687 !brw_is_color_fast_clear_compatible(brw
, irb
->mt
, &ctx
->Color
.ClearColor
))
688 can_fast_clear
= false;
690 const bool is_lossless_compressed
= intel_miptree_is_lossless_compressed(
693 if (can_fast_clear
) {
694 /* Record the clear color in the miptree so that it will be
695 * programmed in SURFACE_STATE by later rendering and resolve
698 const bool color_updated
= brw_meta_set_fast_clear_color(
699 brw
, irb
->mt
, &ctx
->Color
.ClearColor
);
701 /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
702 * is redundant and can be skipped.
704 if (!color_updated
&&
705 irb
->mt
->fast_clear_state
== INTEL_FAST_CLEAR_STATE_CLEAR
)
708 /* If the MCS buffer hasn't been allocated yet, we need to allocate
711 if (!irb
->mt
->mcs_mt
) {
712 assert(!is_lossless_compressed
);
713 if (!intel_miptree_alloc_non_msrt_mcs(brw
, irb
->mt
, false)) {
714 /* MCS allocation failed--probably this will only happen in
715 * out-of-memory conditions. But in any case, try to recover
716 * by falling back to a non-blorp clear technique.
723 intel_miptree_check_level_layer(irb
->mt
, irb
->mt_level
, layer
);
724 intel_miptree_used_for_rendering(irb
->mt
);
726 /* We can't setup the blorp_surf until we've allocated the MCS above */
727 struct isl_surf isl_tmp
[2];
728 struct blorp_surf surf
;
729 unsigned level
= irb
->mt_level
;
730 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, true, &level
, isl_tmp
);
732 if (can_fast_clear
) {
733 DBG("%s (fast) to mt %p level %d layer %d\n", __FUNCTION__
,
734 irb
->mt
, irb
->mt_level
, irb
->mt_layer
);
736 struct blorp_batch batch
;
737 blorp_batch_init(&brw
->blorp
, &batch
, brw
);
738 blorp_fast_clear(&batch
, &surf
,
739 (enum isl_format
)brw
->render_target_format
[format
],
740 level
, layer
, 1, x0
, y0
, x1
, y1
);
741 blorp_batch_finish(&batch
);
743 /* Now that the fast clear has occurred, put the buffer in
744 * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
747 irb
->mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
749 DBG("%s (slow) to mt %p level %d layer %d\n", __FUNCTION__
,
750 irb
->mt
, irb
->mt_level
, irb
->mt_layer
);
752 union isl_color_value clear_color
;
753 memcpy(clear_color
.f32
, ctx
->Color
.ClearColor
.f
, sizeof(float) * 4);
755 struct blorp_batch batch
;
756 blorp_batch_init(&brw
->blorp
, &batch
, brw
);
757 blorp_clear(&batch
, &surf
, level
, layer
, 1, x0
, y0
, x1
, y1
,
758 (enum isl_format
)brw
->render_target_format
[format
],
759 clear_color
, color_write_disable
);
760 blorp_batch_finish(&batch
);
762 if (is_lossless_compressed
) {
763 /* Compressed buffers can be cleared also using normal rep-clear. In
764 * such case they behave such as if they were drawn using normal 3D
765 * render pipeline, and we simply mark the mcs as dirty.
767 irb
->mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_UNRESOLVED
;
775 brw_blorp_clear_color(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
776 GLbitfield mask
, bool partial_clear
, bool encode_srgb
)
778 for (unsigned buf
= 0; buf
< fb
->_NumColorDrawBuffers
; buf
++) {
779 struct gl_renderbuffer
*rb
= fb
->_ColorDrawBuffers
[buf
];
780 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
782 /* Only clear the buffers present in the provided mask */
783 if (((1 << fb
->_ColorDrawBufferIndexes
[buf
]) & mask
) == 0)
786 /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
787 * the framebuffer can be complete with some attachments missing. In
788 * this case the _ColorDrawBuffers pointer will be NULL.
793 if (fb
->MaxNumLayers
> 0) {
794 unsigned layer_multiplier
=
795 (irb
->mt
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
796 irb
->mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) ?
797 irb
->mt
->num_samples
: 1;
798 unsigned num_layers
= irb
->layer_count
;
799 for (unsigned layer
= 0; layer
< num_layers
; layer
++) {
800 if (!do_single_blorp_clear(
801 brw
, fb
, rb
, buf
, partial_clear
, encode_srgb
,
802 irb
->mt_layer
+ layer
* layer_multiplier
)) {
807 unsigned layer
= irb
->mt_layer
;
808 if (!do_single_blorp_clear(brw
, fb
, rb
, buf
, partial_clear
,
813 irb
->need_downsample
= true;
820 brw_blorp_resolve_color(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
822 DBG("%s to mt %p\n", __FUNCTION__
, mt
);
824 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
826 intel_miptree_check_level_layer(mt
, 0 /* level */, 0 /* layer */);
827 intel_miptree_used_for_rendering(mt
);
829 struct isl_surf isl_tmp
[2];
830 struct blorp_surf surf
;
832 blorp_surf_for_miptree(brw
, &surf
, mt
, true, &level
, isl_tmp
);
834 struct blorp_batch batch
;
835 blorp_batch_init(&brw
->blorp
, &batch
, brw
);
836 blorp_ccs_resolve(&batch
, &surf
,
837 brw_blorp_to_isl_format(brw
, format
, true));
838 blorp_batch_finish(&batch
);
840 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
844 gen6_blorp_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
845 unsigned int level
, unsigned int layer
, enum blorp_hiz_op op
)
847 intel_miptree_check_level_layer(mt
, level
, layer
);
848 intel_miptree_used_for_rendering(mt
);
850 assert(intel_miptree_level_has_hiz(mt
, level
));
852 struct isl_surf isl_tmp
[2];
853 struct blorp_surf surf
;
854 blorp_surf_for_miptree(brw
, &surf
, mt
, true, &level
, isl_tmp
);
856 struct blorp_batch batch
;
857 blorp_batch_init(&brw
->blorp
, &batch
, brw
);
858 blorp_gen6_hiz_op(&batch
, &surf
, level
, layer
, op
);
859 blorp_batch_finish(&batch
);
863 * Perform a HiZ or depth resolve operation.
865 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
866 * PRM, Volume 1, Part 2:
867 * - 7.5.3.1 Depth Buffer Clear
868 * - 7.5.3.2 Depth Buffer Resolve
869 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
872 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
873 unsigned int level
, unsigned int layer
, enum blorp_hiz_op op
)
875 const char *opname
= NULL
;
878 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
879 opname
= "depth resolve";
881 case BLORP_HIZ_OP_HIZ_RESOLVE
:
882 opname
= "hiz ambiguate";
884 case BLORP_HIZ_OP_DEPTH_CLEAR
:
885 opname
= "depth clear";
887 case BLORP_HIZ_OP_NONE
:
892 DBG("%s %s to mt %p level %d layer %d\n",
893 __func__
, opname
, mt
, level
, layer
);
896 gen8_hiz_exec(brw
, mt
, level
, layer
, op
);
898 gen6_blorp_hiz_exec(brw
, mt
, level
, layer
, op
);