2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_batchbuffer.h"
26 #include "intel_fbo.h"
28 #include "brw_blorp.h"
29 #include "brw_compiler.h"
31 #include "brw_state.h"
33 #define FILE_DEBUG_FLAG DEBUG_BLORP
36 * A variant of isl_surf_get_image_offset_sa() specific to gen6 stencil and
40 get_image_offset_sa_gen6_stencil(const struct isl_surf
*surf
,
41 uint32_t level
, uint32_t logical_array_layer
,
42 uint32_t *x_offset_sa
,
43 uint32_t *y_offset_sa
)
45 assert(surf
->tiling
== ISL_TILING_W
|| surf
->format
== ISL_FORMAT_HIZ
);
46 assert(level
< surf
->levels
);
47 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
49 const struct isl_extent3d image_align_sa
=
50 isl_surf_get_image_alignment_sa(surf
);
52 const uint32_t W0
= surf
->phys_level0_sa
.width
;
53 const uint32_t H0
= surf
->phys_level0_sa
.height
;
55 uint32_t x
= 0, y
= 0;
56 for (uint32_t l
= 0; l
< level
; ++l
) {
58 uint32_t W
= minify(W0
, l
);
60 if (surf
->samples
> 1) {
61 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
62 assert(surf
->samples
== 4);
66 x
+= ALIGN(W
, image_align_sa
.w
);
68 uint32_t H
= minify(H0
, l
);
70 if (surf
->samples
> 1) {
71 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
72 assert(surf
->samples
== 4);
76 y
+= ALIGN(H
, image_align_sa
.h
) * surf
->logical_level0_px
.array_len
;
80 /* Now account for our location within the given LOD */
81 uint32_t Hl
= minify(H0
, level
);
82 if (surf
->samples
> 1) {
83 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
84 assert(surf
->samples
== 4);
85 Hl
= ALIGN(Hl
, 2) * 2;
87 y
+= ALIGN(Hl
, image_align_sa
.h
) * logical_array_layer
;
94 blorp_get_image_offset_sa(struct isl_device
*dev
, const struct isl_surf
*surf
,
95 uint32_t level
, uint32_t layer
,
96 uint32_t *x_offset_sa
,
97 uint32_t *y_offset_sa
)
99 if (ISL_DEV_GEN(dev
) == 6 && surf
->tiling
== ISL_TILING_W
) {
100 get_image_offset_sa_gen6_stencil(surf
, level
, layer
,
101 x_offset_sa
, y_offset_sa
);
103 /* Using base_array_layer for Z in 3-D surfaces is a bit abusive, but it
104 * will go away soon enough.
107 if (surf
->dim
== ISL_SURF_DIM_3D
) {
112 isl_surf_get_image_offset_sa(surf
, level
, layer
, z
,
113 x_offset_sa
, y_offset_sa
);
118 surf_apply_level_layer_offsets(struct isl_device
*dev
, struct isl_surf
*surf
,
119 struct isl_view
*view
, uint32_t *byte_offset
,
120 uint32_t *tile_x_sa
, uint32_t *tile_y_sa
)
122 /* This only makes sense for a single level and array slice */
123 assert(view
->levels
== 1 && view
->array_len
== 1);
125 uint32_t x_offset_sa
, y_offset_sa
;
126 blorp_get_image_offset_sa(dev
, surf
, view
->base_level
,
127 view
->base_array_layer
,
128 &x_offset_sa
, &y_offset_sa
);
130 isl_tiling_get_intratile_offset_sa(dev
, surf
->tiling
, view
->format
,
131 surf
->row_pitch
, x_offset_sa
, y_offset_sa
,
132 byte_offset
, tile_x_sa
, tile_y_sa
);
134 /* Now that that's done, we have a very bare 2-D surface */
135 surf
->dim
= ISL_SURF_DIM_2D
;
136 surf
->dim_layout
= ISL_DIM_LAYOUT_GEN4_2D
;
138 surf
->logical_level0_px
.width
=
139 minify(surf
->logical_level0_px
.width
, view
->base_level
);
140 surf
->logical_level0_px
.height
=
141 minify(surf
->logical_level0_px
.height
, view
->base_level
);
142 surf
->logical_level0_px
.depth
= 1;
143 surf
->logical_level0_px
.array_len
= 1;
146 /* Alignment doesn't matter since we have 1 miplevel and 1 array slice so
147 * just pick something that works for everybody.
149 surf
->image_alignment_el
= isl_extent3d(4, 4, 1);
151 /* TODO: surf->physcal_level0_extent_sa? */
153 view
->base_level
= 0;
154 view
->base_array_layer
= 0;
158 brw_blorp_surface_info_init(struct brw_context
*brw
,
159 struct brw_blorp_surface_info
*info
,
160 struct intel_mipmap_tree
*mt
,
161 unsigned int level
, unsigned int layer
,
162 mesa_format format
, bool is_render_target
)
164 /* Layer is a physical layer, so if this is a 2D multisample array texture
165 * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it had better
166 * be a multiple of num_samples.
168 unsigned layer_multiplier
= 1;
169 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
170 mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
171 assert(mt
->num_samples
<= 1 || layer
% mt
->num_samples
== 0);
172 layer_multiplier
= MAX2(mt
->num_samples
, 1);
175 intel_miptree_check_level_layer(mt
, level
, layer
);
179 intel_miptree_get_isl_surf(brw
, mt
, &info
->surf
);
182 intel_miptree_get_aux_isl_surf(brw
, mt
, &info
->aux_surf
,
185 info
->aux_usage
= ISL_AUX_USAGE_NONE
;
188 info
->view
= (struct isl_view
) {
189 .usage
= is_render_target
? ISL_SURF_USAGE_RENDER_TARGET_BIT
:
190 ISL_SURF_USAGE_TEXTURE_BIT
,
191 .format
= ISL_FORMAT_UNSUPPORTED
, /* Set later */
194 .base_array_layer
= layer
/ layer_multiplier
,
197 ISL_CHANNEL_SELECT_RED
,
198 ISL_CHANNEL_SELECT_GREEN
,
199 ISL_CHANNEL_SELECT_BLUE
,
200 ISL_CHANNEL_SELECT_ALPHA
,
207 if (format
== MESA_FORMAT_NONE
)
211 case MESA_FORMAT_S_UINT8
:
212 assert(info
->surf
.tiling
== ISL_TILING_W
);
213 /* Prior to Broadwell, we can't render to R8_UINT */
214 info
->view
.format
= brw
->gen
>= 8 ? BRW_SURFACEFORMAT_R8_UINT
:
215 BRW_SURFACEFORMAT_R8_UNORM
;
217 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
218 /* It would make sense to use BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
219 * here, but unfortunately it isn't supported as a render target, which
220 * would prevent us from blitting to 24-bit depth.
222 * The miptree consists of 32 bits per pixel, arranged as 24-bit depth
223 * values interleaved with 8 "don't care" bits. Since depth values don't
224 * require any blending, it doesn't matter how we interpret the bit
225 * pattern as long as we copy the right amount of data, so just map it
228 info
->view
.format
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
230 case MESA_FORMAT_Z_FLOAT32
:
231 info
->view
.format
= BRW_SURFACEFORMAT_R32_FLOAT
;
233 case MESA_FORMAT_Z_UNORM16
:
234 info
->view
.format
= BRW_SURFACEFORMAT_R16_UNORM
;
237 if (is_render_target
) {
238 assert(brw
->format_supported_as_render_target
[format
]);
239 info
->view
.format
= brw
->render_target_format
[format
];
241 info
->view
.format
= brw_format_for_mesa_format(format
);
247 surf_apply_level_layer_offsets(&brw
->isl_dev
, &info
->surf
, &info
->view
,
249 &info
->tile_x_sa
, &info
->tile_y_sa
);
254 brw_blorp_params_init(struct brw_blorp_params
*params
)
256 memset(params
, 0, sizeof(*params
));
257 params
->hiz_op
= GEN6_HIZ_OP_NONE
;
258 params
->fast_clear_op
= 0;
259 params
->num_draw_buffers
= 1;
260 params
->num_layers
= 1;
264 brw_blorp_init_wm_prog_key(struct brw_wm_prog_key
*wm_key
)
266 memset(wm_key
, 0, sizeof(*wm_key
));
267 wm_key
->nr_color_regions
= 1;
268 for (int i
= 0; i
< MAX_SAMPLERS
; i
++)
269 wm_key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;
273 nir_uniform_type_size(const struct glsl_type
*type
)
275 /* Only very basic types are allowed */
276 assert(glsl_type_is_vector_or_scalar(type
));
277 assert(glsl_get_bit_size(type
) == 32);
279 return glsl_get_vector_elements(type
) * 4;
283 brw_blorp_compile_nir_shader(struct brw_context
*brw
, struct nir_shader
*nir
,
284 const struct brw_wm_prog_key
*wm_key
,
286 struct brw_blorp_prog_data
*prog_data
,
287 unsigned *program_size
)
289 const struct brw_compiler
*compiler
= brw
->intelScreen
->compiler
;
291 void *mem_ctx
= ralloc_context(NULL
);
293 /* Calling brw_preprocess_nir and friends is destructive and, if cloning is
294 * enabled, may end up completely replacing the nir_shader. Therefore, we
295 * own it and might as well put it in our context for easy cleanup.
297 ralloc_steal(mem_ctx
, nir
);
299 compiler
->glsl_compiler_options
[MESA_SHADER_FRAGMENT
].NirOptions
;
301 struct brw_wm_prog_data wm_prog_data
;
302 memset(&wm_prog_data
, 0, sizeof(wm_prog_data
));
304 wm_prog_data
.base
.nr_params
= 0;
305 wm_prog_data
.base
.param
= NULL
;
307 /* BLORP always just uses the first two binding table entries */
308 wm_prog_data
.binding_table
.render_target_start
= 0;
309 wm_prog_data
.base
.binding_table
.texture_start
= 1;
311 nir
= brw_preprocess_nir(compiler
, nir
);
312 nir_remove_dead_variables(nir
, nir_var_shader_in
);
313 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
)->impl
);
315 /* Uniforms are required to be lowered before going into compile_fs. For
316 * BLORP, we'll assume that whoever builds the shader sets the location
317 * they want so we just need to lower them and figure out how many we have
320 nir
->num_uniforms
= 0;
321 nir_foreach_variable(var
, &nir
->uniforms
) {
322 var
->data
.driver_location
= var
->data
.location
;
323 unsigned end
= var
->data
.location
+ nir_uniform_type_size(var
->type
);
324 nir
->num_uniforms
= MAX2(nir
->num_uniforms
, end
);
326 nir_lower_io(nir
, nir_var_uniform
, nir_uniform_type_size
);
328 const unsigned *program
=
329 brw_compile_fs(compiler
, brw
, mem_ctx
, wm_key
, &wm_prog_data
, nir
,
330 NULL
, -1, -1, false, use_repclear
, program_size
, NULL
);
332 /* Copy the relavent bits of wm_prog_data over into the blorp prog data */
333 prog_data
->dispatch_8
= wm_prog_data
.dispatch_8
;
334 prog_data
->dispatch_16
= wm_prog_data
.dispatch_16
;
335 prog_data
->first_curbe_grf_0
= wm_prog_data
.base
.dispatch_grf_start_reg
;
336 prog_data
->first_curbe_grf_2
= wm_prog_data
.dispatch_grf_start_reg_2
;
337 prog_data
->ksp_offset_2
= wm_prog_data
.prog_offset_2
;
338 prog_data
->persample_msaa_dispatch
= wm_prog_data
.persample_dispatch
;
339 prog_data
->flat_inputs
= wm_prog_data
.flat_inputs
;
340 prog_data
->num_varying_inputs
= wm_prog_data
.num_varying_inputs
;
341 prog_data
->inputs_read
= nir
->info
.inputs_read
;
343 assert(wm_prog_data
.base
.nr_params
== 0);
348 struct surface_state_info
{
350 unsigned ss_align
; /* Required alignment of RENDER_SURFACE_STATE in bytes */
352 unsigned aux_reloc_dw
;
357 static const struct surface_state_info surface_state_infos
[] = {
359 [7] = {8, 32, 1, 6, GEN7_MOCS_L3
, GEN7_MOCS_L3
},
360 [8] = {13, 64, 8, 10, BDW_MOCS_WB
, BDW_MOCS_PTE
},
361 [9] = {16, 64, 8, 10, SKL_MOCS_WB
, SKL_MOCS_PTE
},
365 brw_blorp_emit_surface_state(struct brw_context
*brw
,
366 const struct brw_blorp_surface_info
*surface
,
367 uint32_t read_domains
, uint32_t write_domain
,
368 bool is_render_target
)
370 const struct surface_state_info ss_info
= surface_state_infos
[brw
->gen
];
372 struct isl_surf surf
= surface
->surf
;
374 union isl_color_value clear_color
= { .u32
= { 0, 0, 0, 0 } };
376 const struct isl_surf
*aux_surf
= NULL
;
377 uint64_t aux_offset
= 0;
378 if (surface
->mt
->mcs_mt
) {
379 aux_surf
= &surface
->aux_surf
;
380 assert(surface
->mt
->mcs_mt
->offset
== 0);
381 aux_offset
= surface
->mt
->mcs_mt
->bo
->offset64
;
383 /* We only really need a clear color if we also have an auxiliary
384 * surface. Without one, it does nothing.
386 clear_color
= intel_miptree_get_isl_clear_color(brw
, surface
->mt
);
389 struct isl_view view
= {
390 .format
= surface
->view
.format
,
393 .base_array_layer
= 0,
396 ISL_CHANNEL_SELECT_RED
,
397 ISL_CHANNEL_SELECT_GREEN
,
398 ISL_CHANNEL_SELECT_BLUE
,
399 ISL_CHANNEL_SELECT_ALPHA
,
401 .usage
= is_render_target
? ISL_SURF_USAGE_RENDER_TARGET_BIT
:
402 ISL_SURF_USAGE_TEXTURE_BIT
,
405 uint32_t surf_offset
;
406 uint32_t *dw
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
407 ss_info
.num_dwords
* 4, ss_info
.ss_align
,
410 const uint32_t mocs
= is_render_target
? ss_info
.rb_mocs
: ss_info
.tex_mocs
;
412 isl_surf_fill_state(&brw
->isl_dev
, dw
, .surf
= &surf
, .view
= &view
,
413 .address
= surface
->mt
->bo
->offset64
+ surface
->bo_offset
,
414 .aux_surf
= aux_surf
, .aux_usage
= surface
->aux_usage
,
415 .aux_address
= aux_offset
,
416 .mocs
= mocs
, .clear_color
= clear_color
,
417 .x_offset_sa
= surface
->tile_x_sa
,
418 .y_offset_sa
= surface
->tile_y_sa
);
420 /* Emit relocation to surface contents */
421 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
422 surf_offset
+ ss_info
.reloc_dw
* 4,
424 dw
[ss_info
.reloc_dw
] - surface
->mt
->bo
->offset64
,
425 read_domains
, write_domain
);
428 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
429 * used to store other information. This should be ok, however, because
430 * surface buffer addresses are always 4K page alinged.
432 assert((aux_offset
& 0xfff) == 0);
433 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
434 surf_offset
+ ss_info
.aux_reloc_dw
* 4,
435 surface
->mt
->mcs_mt
->bo
,
436 dw
[ss_info
.aux_reloc_dw
] & 0xfff,
437 read_domains
, write_domain
);
444 * Perform a HiZ or depth resolve operation.
446 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
447 * PRM, Volume 1, Part 2:
448 * - 7.5.3.1 Depth Buffer Clear
449 * - 7.5.3.2 Depth Buffer Resolve
450 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
453 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
454 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
)
456 const char *opname
= NULL
;
459 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
460 opname
= "depth resolve";
462 case GEN6_HIZ_OP_HIZ_RESOLVE
:
463 opname
= "hiz ambiguate";
465 case GEN6_HIZ_OP_DEPTH_CLEAR
:
466 opname
= "depth clear";
468 case GEN6_HIZ_OP_NONE
:
473 DBG("%s %s to mt %p level %d layer %d\n",
474 __func__
, opname
, mt
, level
, layer
);
477 gen8_hiz_exec(brw
, mt
, level
, layer
, op
);
479 gen6_blorp_hiz_exec(brw
, mt
, level
, layer
, op
);
484 brw_blorp_exec(struct brw_context
*brw
, const struct brw_blorp_params
*params
)
486 struct gl_context
*ctx
= &brw
->ctx
;
487 const uint32_t estimated_max_batch_usage
= brw
->gen
>= 8 ? 1800 : 1500;
488 bool check_aperture_failed_once
= false;
490 /* Flush the sampler and render caches. We definitely need to flush the
491 * sampler cache so that we get updated contents from the render cache for
492 * the glBlitFramebuffer() source. Also, we are sometimes warned in the
493 * docs to flush the cache between reinterpretations of the same surface
494 * data with different formats, which blorp does for stencil and depth
497 brw_emit_mi_flush(brw
);
499 brw_select_pipeline(brw
, BRW_RENDER_PIPELINE
);
502 intel_batchbuffer_require_space(brw
, estimated_max_batch_usage
, RENDER_RING
);
503 intel_batchbuffer_save_state(brw
);
504 drm_intel_bo
*saved_bo
= brw
->batch
.bo
;
505 uint32_t saved_used
= USED_BATCH(brw
->batch
);
506 uint32_t saved_state_batch_offset
= brw
->batch
.state_batch_offset
;
510 gen6_blorp_exec(brw
, params
);
513 gen7_blorp_exec(brw
, params
);
517 gen8_blorp_exec(brw
, params
);
520 /* BLORP is not supported before Gen6. */
521 unreachable("not reached");
524 /* Make sure we didn't wrap the batch unintentionally, and make sure we
525 * reserved enough space that a wrap will never happen.
527 assert(brw
->batch
.bo
== saved_bo
);
528 assert((USED_BATCH(brw
->batch
) - saved_used
) * 4 +
529 (saved_state_batch_offset
- brw
->batch
.state_batch_offset
) <
530 estimated_max_batch_usage
);
531 /* Shut up compiler warnings on release build */
534 (void)saved_state_batch_offset
;
536 /* Check if the blorp op we just did would make our batch likely to fail to
537 * map all the BOs into the GPU at batch exec time later. If so, flush the
538 * batch and try again with nothing else in the batch.
540 if (dri_bufmgr_check_aperture_space(&brw
->batch
.bo
, 1)) {
541 if (!check_aperture_failed_once
) {
542 check_aperture_failed_once
= true;
543 intel_batchbuffer_reset_to_saved(brw
);
544 intel_batchbuffer_flush(brw
);
547 int ret
= intel_batchbuffer_flush(brw
);
548 WARN_ONCE(ret
== -ENOSPC
,
549 "i965: blorp emit exceeded available aperture space\n");
553 if (unlikely(brw
->always_flush_batch
))
554 intel_batchbuffer_flush(brw
);
556 /* We've smashed all state compared to what the normal 3D pipeline
557 * rendering tracks for GL.
559 brw
->ctx
.NewDriverState
|= BRW_NEW_BLORP
;
560 brw
->no_depth_or_stencil
= false;
563 /* Flush the sampler cache so any texturing from the destination is
566 brw_emit_mi_flush(brw
);
570 gen6_blorp_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
571 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
)
573 struct brw_blorp_params params
;
574 brw_blorp_params_init(¶ms
);
578 brw_blorp_surface_info_init(brw
, ¶ms
.depth
, mt
, level
, layer
,
581 /* Align the rectangle primitive to 8x4 pixels.
583 * During fast depth clears, the emitted rectangle primitive must be
584 * aligned to 8x4 pixels. From the Ivybridge PRM, Vol 2 Part 1 Section
585 * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
587 * If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
588 * aligned to an 8x4 pixel block relative to the upper left corner
589 * of the depth buffer [...]
591 * For hiz resolves, the rectangle must also be 8x4 aligned. Item
592 * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
593 * Ivybridge simulator require the alignment.
595 * To be safe, let's just align the rect for all hiz operations and all
596 * hardware generations.
598 * However, for some miptree slices of a Z24 texture, emitting an 8x4
599 * aligned rectangle that covers the slice may clobber adjacent slices if
600 * we strictly adhered to the texture alignments specified in the PRM. The
601 * Ivybridge PRM, Section "Alignment Unit Size", states that
602 * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
603 * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
604 * prevents the clobbering.
606 params
.dst
.surf
.samples
= MAX2(mt
->num_samples
, 1);
607 params
.depth
.surf
.logical_level0_px
.width
=
608 ALIGN(params
.depth
.surf
.logical_level0_px
.width
, 8);
609 params
.depth
.surf
.logical_level0_px
.height
=
610 ALIGN(params
.depth
.surf
.logical_level0_px
.height
, 4);
612 params
.x1
= params
.depth
.surf
.logical_level0_px
.width
;
613 params
.y1
= params
.depth
.surf
.logical_level0_px
.height
;
615 assert(intel_miptree_level_has_hiz(mt
, level
));
617 switch (mt
->format
) {
618 case MESA_FORMAT_Z_UNORM16
:
619 params
.depth_format
= BRW_DEPTHFORMAT_D16_UNORM
;
621 case MESA_FORMAT_Z_FLOAT32
:
622 params
.depth_format
= BRW_DEPTHFORMAT_D32_FLOAT
;
624 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
625 params
.depth_format
= BRW_DEPTHFORMAT_D24_UNORM_X8_UINT
;
628 unreachable("not reached");
631 brw_blorp_exec(brw
, ¶ms
);