src/mesa/drivers/dri/i965/brw_blorp.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/context.h"
  25 #include "main/teximage.h"
  26 #include "main/blend.h"
  27 #include "main/fbobject.h"
  28 #include "main/renderbuffer.h"
  29 #include "main/glformats.h"
  30
  31 #include "brw_blorp.h"
  32 #include "brw_context.h"
  33 #include "brw_meta_util.h"
  34 #include "brw_state.h"
  35 #include "intel_fbo.h"
  36 #include "intel_debug.h"
  37
  38 #define FILE_DEBUG_FLAG DEBUG_BLORP
  39
  40 static void
  41 apply_gen6_stencil_hiz_offset(struct isl_surf *surf,
  42                               struct intel_mipmap_tree *mt,
  43                               uint32_t lod,
  44                               uint32_t *offset)
  45 {
  46    assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD);
  47
  48    if (mt->format == MESA_FORMAT_S_UINT8) {
  49       /* Note: we can't compute the stencil offset using
  50        * intel_miptree_get_aligned_offset(), because the miptree
  51        * claims that the region is untiled even though it's W tiled.
  52        */
  53       *offset = mt->level[lod].level_y * mt->pitch +
  54                 mt->level[lod].level_x * 64;
  55    } else {
  56       *offset = intel_miptree_get_aligned_offset(mt,
  57                                                  mt->level[lod].level_x,
  58                                                  mt->level[lod].level_y,
  59                                                  false);
  60    }
  61
  62    surf->logical_level0_px.width = minify(surf->logical_level0_px.width, lod);
  63    surf->logical_level0_px.height = minify(surf->logical_level0_px.height, lod);
  64    surf->phys_level0_sa.width = minify(surf->phys_level0_sa.width, lod);
  65    surf->phys_level0_sa.height = minify(surf->phys_level0_sa.height, lod);
  66    surf->levels = 1;
  67    surf->array_pitch_el_rows =
  68       ALIGN(surf->phys_level0_sa.height, surf->image_alignment_el.height);
  69 }
  70
  71 static void
  72 brw_blorp_surf_for_miptree(struct brw_context *brw,
  73                            struct brw_blorp_surf *surf,
  74                            struct intel_mipmap_tree *mt,
  75                            bool is_render_target,
  76                            unsigned *level,
  77                            struct isl_surf tmp_surfs[2])
  78 {
  79    intel_miptree_get_isl_surf(brw, mt, &tmp_surfs[0]);
  80    surf->surf = &tmp_surfs[0];
  81    surf->bo = mt->bo;
  82    surf->offset = mt->offset;
  83
  84    if (brw->gen == 6 && mt->format == MESA_FORMAT_S_UINT8 &&
  85        mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
  86       /* Sandy bridge stencil and HiZ use this ALL_SLICES_AT_EACH_LOD hack in
  87        * order to allow for layered rendering.  The hack makes each LOD of the
  88        * stencil or HiZ buffer a single tightly packed array surface at some
  89        * offset into the surface.  Since ISL doesn't know how to deal with the
  90        * crazy ALL_SLICES_AT_EACH_LOD layout and since we have to do a manual
  91        * offset of it anyway, we might as well do the offset here and keep the
  92        * hacks inside the i965 driver.
  93        *
  94        * See also gen6_depth_stencil_state.c
  95        */
  96       uint32_t offset;
  97       apply_gen6_stencil_hiz_offset(&tmp_surfs[0], mt, *level, &offset);
  98       surf->offset += offset;
  99       *level = 0;
 100    }
 101
 102    struct isl_surf *aux_surf = &tmp_surfs[1];
 103    intel_miptree_get_aux_isl_surf(brw, mt, aux_surf, &surf->aux_usage);
 104
 105    /* For textures that are in the RESOLVED state, we ignore the MCS */
 106    if (mt->mcs_mt && !is_render_target &&
 107        mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED)
 108       surf->aux_usage = ISL_AUX_USAGE_NONE;
 109
 110    if (surf->aux_usage != ISL_AUX_USAGE_NONE) {
 111       /* We only really need a clear color if we also have an auxiliary
 112        * surface.  Without one, it does nothing.
 113        */
 114       surf->clear_color = intel_miptree_get_isl_clear_color(brw, mt);
 115
 116       surf->aux_surf = aux_surf;
 117       if (mt->mcs_mt) {
 118          surf->aux_bo = mt->mcs_mt->bo;
 119          surf->aux_offset = mt->mcs_mt->offset;
 120       } else {
 121          assert(surf->aux_usage == ISL_AUX_USAGE_HIZ);
 122          struct intel_mipmap_tree *hiz_mt = mt->hiz_buf->mt;
 123          if (hiz_mt) {
 124             surf->aux_bo = hiz_mt->bo;
 125             if (brw->gen == 6 &&
 126                 hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
 127                /* gen6 requires the HiZ buffer to be manually offset to the
 128                 * right location.  We could fixup the surf but it doesn't
 129                 * matter since most of those fields don't matter.
 130                 */
 131                apply_gen6_stencil_hiz_offset(aux_surf, hiz_mt, *level,
 132                                              &surf->aux_offset);
 133             } else {
 134                surf->aux_offset = 0;
 135             }
 136             assert(hiz_mt->pitch == aux_surf->row_pitch);
 137          } else {
 138             surf->aux_bo = mt->hiz_buf->bo;
 139             surf->aux_offset = 0;
 140          }
 141       }
 142    } else {
 143       surf->aux_bo = NULL;
 144       surf->aux_offset = 0;
 145       memset(&surf->clear_color, 0, sizeof(surf->clear_color));
 146    }
 147    assert((surf->aux_usage == ISL_AUX_USAGE_NONE) == (surf->aux_bo == NULL));
 148 }
 149
 150 static enum isl_format
 151 brw_blorp_to_isl_format(struct brw_context *brw, mesa_format format,
 152                         bool is_render_target)
 153 {
 154    switch (format) {
 155    case MESA_FORMAT_NONE:
 156       return ISL_FORMAT_UNSUPPORTED;
 157    case MESA_FORMAT_S_UINT8:
 158       return ISL_FORMAT_R8_UINT;
 159    case MESA_FORMAT_Z24_UNORM_X8_UINT:
 160       return ISL_FORMAT_R24_UNORM_X8_TYPELESS;
 161    case MESA_FORMAT_Z_FLOAT32:
 162       return ISL_FORMAT_R32_FLOAT;
 163    case MESA_FORMAT_Z_UNORM16:
 164       return ISL_FORMAT_R16_UNORM;
 165    default: {
 166       if (is_render_target) {
 167          assert(brw->format_supported_as_render_target[format]);
 168          return brw->render_target_format[format];
 169       } else {
 170          return brw_format_for_mesa_format(format);
 171       }
 172       break;
 173    }
 174    }
 175 }
 176
 177 /**
 178  * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
 179  * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
 180  * the physical layer holding sample 0.  So, for example, if
 181  * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
 182  * 4*n.
 183  */
 184 void
 185 brw_blorp_blit_miptrees(struct brw_context *brw,
 186                         struct intel_mipmap_tree *src_mt,
 187                         unsigned src_level, unsigned src_layer,
 188                         mesa_format src_format, int src_swizzle,
 189                         struct intel_mipmap_tree *dst_mt,
 190                         unsigned dst_level, unsigned dst_layer,
 191                         mesa_format dst_format,
 192                         float src_x0, float src_y0,
 193                         float src_x1, float src_y1,
 194                         float dst_x0, float dst_y0,
 195                         float dst_x1, float dst_y1,
 196                         GLenum filter, bool mirror_x, bool mirror_y,
 197                         bool decode_srgb, bool encode_srgb)
 198 {
 199    /* Get ready to blit.  This includes depth resolving the src and dst
 200     * buffers if necessary.  Note: it's not necessary to do a color resolve on
 201     * the destination buffer because we use the standard render path to render
 202     * to destination color buffers, and the standard render path is
 203     * fast-color-aware.
 204     */
 205    intel_miptree_resolve_color(brw, src_mt, INTEL_MIPTREE_IGNORE_CCS_E);
 206    intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_layer);
 207    intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_layer);
 208
 209    intel_miptree_prepare_mcs(brw, dst_mt);
 210
 211    DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
 212        "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
 213        __func__,
 214        src_mt->num_samples, _mesa_get_format_name(src_mt->format), src_mt,
 215        src_level, src_layer, src_x0, src_y0, src_x1, src_y1,
 216        dst_mt->num_samples, _mesa_get_format_name(dst_mt->format), dst_mt,
 217        dst_level, dst_layer, dst_x0, dst_y0, dst_x1, dst_y1,
 218        mirror_x, mirror_y);
 219
 220    if (!decode_srgb && _mesa_get_format_color_encoding(src_format) == GL_SRGB)
 221       src_format = _mesa_get_srgb_format_linear(src_format);
 222
 223    if (!encode_srgb && _mesa_get_format_color_encoding(dst_format) == GL_SRGB)
 224       dst_format = _mesa_get_srgb_format_linear(dst_format);
 225
 226    /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
 227     * texture, the above code configures the source format for L32_FLOAT or
 228     * I32_FLOAT, and the destination format for R32_FLOAT.  On Sandy Bridge,
 229     * the SAMPLE message appears to handle multisampled L32_FLOAT and
 230     * I32_FLOAT textures incorrectly, resulting in blocky artifacts.  So work
 231     * around the problem by using a source format of R32_FLOAT.  This
 232     * shouldn't affect rendering correctness, since the destination format is
 233     * R32_FLOAT, so only the contents of the red channel matters.
 234     */
 235    if (brw->gen == 6 &&
 236        src_mt->num_samples > 1 && dst_mt->num_samples <= 1 &&
 237        src_mt->format == dst_mt->format &&
 238        (dst_format == MESA_FORMAT_L_FLOAT32 ||
 239         dst_format == MESA_FORMAT_I_FLOAT32)) {
 240       src_format = dst_format = MESA_FORMAT_R_FLOAT32;
 241    }
 242
 243    intel_miptree_check_level_layer(src_mt, src_level, src_layer);
 244    intel_miptree_check_level_layer(dst_mt, dst_level, dst_layer);
 245    intel_miptree_used_for_rendering(dst_mt);
 246
 247    struct isl_surf tmp_surfs[4];
 248    struct brw_blorp_surf src_surf, dst_surf;
 249    brw_blorp_surf_for_miptree(brw, &src_surf, src_mt, false,
 250                               &src_level, &tmp_surfs[0]);
 251    brw_blorp_surf_for_miptree(brw, &dst_surf, dst_mt, true,
 252                               &dst_level, &tmp_surfs[2]);
 253
 254    brw_blorp_blit(brw, &src_surf, src_level, src_layer,
 255                   brw_blorp_to_isl_format(brw, src_format, false), src_swizzle,
 256                   &dst_surf, dst_level, dst_layer,
 257                   brw_blorp_to_isl_format(brw, dst_format, true),
 258                   src_x0, src_y0, src_x1, src_y1,
 259                   dst_x0, dst_y0, dst_x1, dst_y1,
 260                   filter, mirror_x, mirror_y);
 261
 262    intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_layer);
 263
 264    if (intel_miptree_is_lossless_compressed(brw, dst_mt))
 265       dst_mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
 266 }
 267
 268 static struct intel_mipmap_tree *
 269 find_miptree(GLbitfield buffer_bit, struct intel_renderbuffer *irb)
 270 {
 271    struct intel_mipmap_tree *mt = irb->mt;
 272    if (buffer_bit == GL_STENCIL_BUFFER_BIT && mt->stencil_mt)
 273       mt = mt->stencil_mt;
 274    return mt;
 275 }
 276
 277 static int
 278 blorp_get_texture_swizzle(const struct intel_renderbuffer *irb)
 279 {
 280    return irb->Base.Base._BaseFormat == GL_RGB ?
 281       MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE) :
 282       SWIZZLE_XYZW;
 283 }
 284
 285 static void
 286 do_blorp_blit(struct brw_context *brw, GLbitfield buffer_bit,
 287               struct intel_renderbuffer *src_irb, mesa_format src_format,
 288               struct intel_renderbuffer *dst_irb, mesa_format dst_format,
 289               GLfloat srcX0, GLfloat srcY0, GLfloat srcX1, GLfloat srcY1,
 290               GLfloat dstX0, GLfloat dstY0, GLfloat dstX1, GLfloat dstY1,
 291               GLenum filter, bool mirror_x, bool mirror_y)
 292 {
 293    const struct gl_context *ctx = &brw->ctx;
 294
 295    /* Find source/dst miptrees */
 296    struct intel_mipmap_tree *src_mt = find_miptree(buffer_bit, src_irb);
 297    struct intel_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_irb);
 298
 299    const bool do_srgb = ctx->Color.sRGBEnabled;
 300
 301    /* Do the blit */
 302    brw_blorp_blit_miptrees(brw,
 303                            src_mt, src_irb->mt_level, src_irb->mt_layer,
 304                            src_format, blorp_get_texture_swizzle(src_irb),
 305                            dst_mt, dst_irb->mt_level, dst_irb->mt_layer,
 306                            dst_format,
 307                            srcX0, srcY0, srcX1, srcY1,
 308                            dstX0, dstY0, dstX1, dstY1,
 309                            filter, mirror_x, mirror_y,
 310                            do_srgb, do_srgb);
 311
 312    dst_irb->need_downsample = true;
 313 }
 314
 315 static bool
 316 try_blorp_blit(struct brw_context *brw,
 317                const struct gl_framebuffer *read_fb,
 318                const struct gl_framebuffer *draw_fb,
 319                GLfloat srcX0, GLfloat srcY0, GLfloat srcX1, GLfloat srcY1,
 320                GLfloat dstX0, GLfloat dstY0, GLfloat dstX1, GLfloat dstY1,
 321                GLenum filter, GLbitfield buffer_bit)
 322 {
 323    struct gl_context *ctx = &brw->ctx;
 324
 325    /* Sync up the state of window system buffers.  We need to do this before
 326     * we go looking for the buffers.
 327     */
 328    intel_prepare_render(brw);
 329
 330    bool mirror_x, mirror_y;
 331    if (brw_meta_mirror_clip_and_scissor(ctx, read_fb, draw_fb,
 332                                         &srcX0, &srcY0, &srcX1, &srcY1,
 333                                         &dstX0, &dstY0, &dstX1, &dstY1,
 334                                         &mirror_x, &mirror_y))
 335       return true;
 336
 337    /* Find buffers */
 338    struct intel_renderbuffer *src_irb;
 339    struct intel_renderbuffer *dst_irb;
 340    struct intel_mipmap_tree *src_mt;
 341    struct intel_mipmap_tree *dst_mt;
 342    switch (buffer_bit) {
 343    case GL_COLOR_BUFFER_BIT:
 344       src_irb = intel_renderbuffer(read_fb->_ColorReadBuffer);
 345       for (unsigned i = 0; i < draw_fb->_NumColorDrawBuffers; ++i) {
 346          dst_irb = intel_renderbuffer(draw_fb->_ColorDrawBuffers[i]);
 347          if (dst_irb)
 348             do_blorp_blit(brw, buffer_bit,
 349                           src_irb, src_irb->Base.Base.Format,
 350                           dst_irb, dst_irb->Base.Base.Format,
 351                           srcX0, srcY0, srcX1, srcY1,
 352                           dstX0, dstY0, dstX1, dstY1,
 353                           filter, mirror_x, mirror_y);
 354       }
 355       break;
 356    case GL_DEPTH_BUFFER_BIT:
 357       src_irb =
 358          intel_renderbuffer(read_fb->Attachment[BUFFER_DEPTH].Renderbuffer);
 359       dst_irb =
 360          intel_renderbuffer(draw_fb->Attachment[BUFFER_DEPTH].Renderbuffer);
 361       src_mt = find_miptree(buffer_bit, src_irb);
 362       dst_mt = find_miptree(buffer_bit, dst_irb);
 363
 364       /* We can't handle format conversions between Z24 and other formats
 365        * since we have to lie about the surface format. See the comments in
 366        * brw_blorp_surface_info::set().
 367        */
 368       if ((src_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT) !=
 369           (dst_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT))
 370          return false;
 371
 372       do_blorp_blit(brw, buffer_bit, src_irb, MESA_FORMAT_NONE,
 373                     dst_irb, MESA_FORMAT_NONE, srcX0, srcY0,
 374                     srcX1, srcY1, dstX0, dstY0, dstX1, dstY1,
 375                     filter, mirror_x, mirror_y);
 376       break;
 377    case GL_STENCIL_BUFFER_BIT:
 378       src_irb =
 379          intel_renderbuffer(read_fb->Attachment[BUFFER_STENCIL].Renderbuffer);
 380       dst_irb =
 381          intel_renderbuffer(draw_fb->Attachment[BUFFER_STENCIL].Renderbuffer);
 382       do_blorp_blit(brw, buffer_bit, src_irb, MESA_FORMAT_NONE,
 383                     dst_irb, MESA_FORMAT_NONE, srcX0, srcY0,
 384                     srcX1, srcY1, dstX0, dstY0, dstX1, dstY1,
 385                     filter, mirror_x, mirror_y);
 386       break;
 387    default:
 388       unreachable("not reached");
 389    }
 390
 391    return true;
 392 }
 393
 394 bool
 395 brw_blorp_copytexsubimage(struct brw_context *brw,
 396                           struct gl_renderbuffer *src_rb,
 397                           struct gl_texture_image *dst_image,
 398                           int slice,
 399                           int srcX0, int srcY0,
 400                           int dstX0, int dstY0,
 401                           int width, int height)
 402 {
 403    struct gl_context *ctx = &brw->ctx;
 404    struct intel_renderbuffer *src_irb = intel_renderbuffer(src_rb);
 405    struct intel_texture_image *intel_image = intel_texture_image(dst_image);
 406
 407    /* No pixel transfer operations (zoom, bias, mapping), just a blit */
 408    if (brw->ctx._ImageTransferState)
 409       return false;
 410
 411    /* Sync up the state of window system buffers.  We need to do this before
 412     * we go looking at the src renderbuffer's miptree.
 413     */
 414    intel_prepare_render(brw);
 415
 416    struct intel_mipmap_tree *src_mt = src_irb->mt;
 417    struct intel_mipmap_tree *dst_mt = intel_image->mt;
 418
 419    /* There is support for only up to eight samples. */
 420    if (src_mt->num_samples > 8 || dst_mt->num_samples > 8)
 421       return false;
 422
 423    /* BLORP is only supported from Gen6 onwards. */
 424    if (brw->gen < 6)
 425       return false;
 426
 427    if (_mesa_get_format_base_format(src_rb->Format) !=
 428        _mesa_get_format_base_format(dst_image->TexFormat)) {
 429       return false;
 430    }
 431
 432    /* We can't handle format conversions between Z24 and other formats since
 433     * we have to lie about the surface format.  See the comments in
 434     * brw_blorp_surface_info::set().
 435     */
 436    if ((src_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT) !=
 437        (dst_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT)) {
 438       return false;
 439    }
 440
 441    if (!brw->format_supported_as_render_target[dst_image->TexFormat])
 442       return false;
 443
 444    /* Source clipping shouldn't be necessary, since copytexsubimage (in
 445     * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
 446     * takes care of it.
 447     *
 448     * Destination clipping shouldn't be necessary since the restrictions on
 449     * glCopyTexSubImage prevent the user from specifying a destination rectangle
 450     * that falls outside the bounds of the destination texture.
 451     * See error_check_subtexture_dimensions().
 452     */
 453
 454    int srcY1 = srcY0 + height;
 455    int srcX1 = srcX0 + width;
 456    int dstX1 = dstX0 + width;
 457    int dstY1 = dstY0 + height;
 458
 459    /* Account for the fact that in the system framebuffer, the origin is at
 460     * the lower left.
 461     */
 462    bool mirror_y = false;
 463    if (_mesa_is_winsys_fbo(ctx->ReadBuffer)) {
 464       GLint tmp = src_rb->Height - srcY0;
 465       srcY0 = src_rb->Height - srcY1;
 466       srcY1 = tmp;
 467       mirror_y = true;
 468    }
 469
 470    /* Account for face selection and texture view MinLayer */
 471    int dst_slice = slice + dst_image->TexObject->MinLayer + dst_image->Face;
 472    int dst_level = dst_image->Level + dst_image->TexObject->MinLevel;
 473
 474    brw_blorp_blit_miptrees(brw,
 475                            src_mt, src_irb->mt_level, src_irb->mt_layer,
 476                            src_rb->Format, blorp_get_texture_swizzle(src_irb),
 477                            dst_mt, dst_level, dst_slice,
 478                            dst_image->TexFormat,
 479                            srcX0, srcY0, srcX1, srcY1,
 480                            dstX0, dstY0, dstX1, dstY1,
 481                            GL_NEAREST, false, mirror_y,
 482                            false, false);
 483
 484    /* If we're copying to a packed depth stencil texture and the source
 485     * framebuffer has separate stencil, we need to also copy the stencil data
 486     * over.
 487     */
 488    src_rb = ctx->ReadBuffer->Attachment[BUFFER_STENCIL].Renderbuffer;
 489    if (_mesa_get_format_bits(dst_image->TexFormat, GL_STENCIL_BITS) > 0 &&
 490        src_rb != NULL) {
 491       src_irb = intel_renderbuffer(src_rb);
 492       src_mt = src_irb->mt;
 493
 494       if (src_mt->stencil_mt)
 495          src_mt = src_mt->stencil_mt;
 496       if (dst_mt->stencil_mt)
 497          dst_mt = dst_mt->stencil_mt;
 498
 499       if (src_mt != dst_mt) {
 500          brw_blorp_blit_miptrees(brw,
 501                                  src_mt, src_irb->mt_level, src_irb->mt_layer,
 502                                  src_mt->format,
 503                                  blorp_get_texture_swizzle(src_irb),
 504                                  dst_mt, dst_level, dst_slice,
 505                                  dst_mt->format,
 506                                  srcX0, srcY0, srcX1, srcY1,
 507                                  dstX0, dstY0, dstX1, dstY1,
 508                                  GL_NEAREST, false, mirror_y,
 509                                  false, false);
 510       }
 511    }
 512
 513    return true;
 514 }
 515
 516
 517 GLbitfield
 518 brw_blorp_framebuffer(struct brw_context *brw,
 519                       struct gl_framebuffer *readFb,
 520                       struct gl_framebuffer *drawFb,
 521                       GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
 522                       GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
 523                       GLbitfield mask, GLenum filter)
 524 {
 525    /* BLORP is not supported before Gen6. */
 526    if (brw->gen < 6)
 527       return mask;
 528
 529    static GLbitfield buffer_bits[] = {
 530       GL_COLOR_BUFFER_BIT,
 531       GL_DEPTH_BUFFER_BIT,
 532       GL_STENCIL_BUFFER_BIT,
 533    };
 534
 535    for (unsigned int i = 0; i < ARRAY_SIZE(buffer_bits); ++i) {
 536       if ((mask & buffer_bits[i]) &&
 537        try_blorp_blit(brw, readFb, drawFb,
 538                       srcX0, srcY0, srcX1, srcY1,
 539                       dstX0, dstY0, dstX1, dstY1,
 540                       filter, buffer_bits[i])) {
 541          mask &= ~buffer_bits[i];
 542       }
 543    }
 544
 545    return mask;
 546 }
 547
 548 static bool
 549 set_write_disables(const struct intel_renderbuffer *irb,
 550                    const GLubyte *color_mask, bool *color_write_disable)
 551 {
 552    /* Format information in the renderbuffer represents the requirements
 553     * given by the client. There are cases where the backing miptree uses,
 554     * for example, RGBA to represent RGBX. Since the client is only expecting
 555     * RGB we can treat alpha as not used and write whatever we like into it.
 556     */
 557    const GLenum base_format = irb->Base.Base._BaseFormat;
 558    const int components = _mesa_base_format_component_count(base_format);
 559    bool disables = false;
 560
 561    assert(components > 0);
 562
 563    for (int i = 0; i < components; i++) {
 564       color_write_disable[i] = !color_mask[i];
 565       disables = disables || !color_mask[i];
 566    }
 567
 568    return disables;
 569 }
 570
 571 static bool
 572 do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
 573                       struct gl_renderbuffer *rb, unsigned buf,
 574                       bool partial_clear, bool encode_srgb, unsigned layer)
 575 {
 576    struct gl_context *ctx = &brw->ctx;
 577    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 578    mesa_format format = irb->mt->format;
 579    uint32_t x0, x1, y0, y1;
 580
 581    if (!encode_srgb && _mesa_get_format_color_encoding(format) == GL_SRGB)
 582       format = _mesa_get_srgb_format_linear(format);
 583
 584    x0 = fb->_Xmin;
 585    x1 = fb->_Xmax;
 586    if (rb->Name != 0) {
 587       y0 = fb->_Ymin;
 588       y1 = fb->_Ymax;
 589    } else {
 590       y0 = rb->Height - fb->_Ymax;
 591       y1 = rb->Height - fb->_Ymin;
 592    }
 593
 594    bool can_fast_clear = !partial_clear;
 595
 596    bool color_write_disable[4] = { false, false, false, false };
 597    if (set_write_disables(irb, ctx->Color.ColorMask[buf], color_write_disable))
 598       can_fast_clear = false;
 599
 600    if (irb->mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_NO_MCS ||
 601        !brw_is_color_fast_clear_compatible(brw, irb->mt, &ctx->Color.ClearColor))
 602       can_fast_clear = false;
 603
 604    if (can_fast_clear) {
 605       /* Record the clear color in the miptree so that it will be
 606        * programmed in SURFACE_STATE by later rendering and resolve
 607        * operations.
 608        */
 609       const bool color_updated = brw_meta_set_fast_clear_color(
 610                                     brw, irb->mt, &ctx->Color.ClearColor);
 611
 612       /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
 613        * is redundant and can be skipped.
 614        */
 615       if (!color_updated &&
 616           irb->mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
 617          return true;
 618
 619       /* If the MCS buffer hasn't been allocated yet, we need to allocate
 620        * it now.
 621        */
 622       if (!irb->mt->mcs_mt) {
 623          if (!intel_miptree_alloc_non_msrt_mcs(brw, irb->mt)) {
 624             /* MCS allocation failed--probably this will only happen in
 625              * out-of-memory conditions.  But in any case, try to recover
 626              * by falling back to a non-blorp clear technique.
 627              */
 628             return false;
 629          }
 630       }
 631    }
 632
 633    intel_miptree_check_level_layer(irb->mt, irb->mt_level, layer);
 634    intel_miptree_used_for_rendering(irb->mt);
 635
 636    /* We can't setup the blorp_surf until we've allocated the MCS above */
 637    struct isl_surf isl_tmp[2];
 638    struct brw_blorp_surf surf;
 639    unsigned level = irb->mt_level;
 640    brw_blorp_surf_for_miptree(brw, &surf, irb->mt, true, &level, isl_tmp);
 641
 642    if (can_fast_clear) {
 643       DBG("%s (fast) to mt %p level %d layer %d\n", __FUNCTION__,
 644           irb->mt, irb->mt_level, irb->mt_layer);
 645
 646       blorp_fast_clear(brw, &surf, level, layer, x0, y0, x1, y1);
 647
 648       /* Now that the fast clear has occurred, put the buffer in
 649        * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
 650        * redundant clears.
 651        */
 652       irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_CLEAR;
 653    } else {
 654       DBG("%s (slow) to mt %p level %d layer %d\n", __FUNCTION__,
 655           irb->mt, irb->mt_level, irb->mt_layer);
 656
 657       union isl_color_value clear_color;
 658       memcpy(clear_color.f32, ctx->Color.ClearColor.f, sizeof(float) * 4);
 659
 660       blorp_clear(brw, &surf, level, layer, x0, y0, x1, y1,
 661                   (enum isl_format)brw->render_target_format[format],
 662                   clear_color, color_write_disable);
 663
 664       if (intel_miptree_is_lossless_compressed(brw, irb->mt)) {
 665          /* Compressed buffers can be cleared also using normal rep-clear. In
 666           * such case they bahave such as if they were drawn using normal 3D
 667           * render pipeline, and we simply mark the mcs as dirty.
 668           */
 669          assert(partial_clear);
 670          irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
 671       }
 672    }
 673
 674    return true;
 675 }
 676
 677 bool
 678 brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb,
 679                       GLbitfield mask, bool partial_clear, bool encode_srgb)
 680 {
 681    for (unsigned buf = 0; buf < fb->_NumColorDrawBuffers; buf++) {
 682       struct gl_renderbuffer *rb = fb->_ColorDrawBuffers[buf];
 683       struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 684
 685       /* Only clear the buffers present in the provided mask */
 686       if (((1 << fb->_ColorDrawBufferIndexes[buf]) & mask) == 0)
 687          continue;
 688
 689       /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
 690        * the framebuffer can be complete with some attachments missing.  In
 691        * this case the _ColorDrawBuffers pointer will be NULL.
 692        */
 693       if (rb == NULL)
 694          continue;
 695
 696       if (fb->MaxNumLayers > 0) {
 697          unsigned layer_multiplier =
 698             (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
 699              irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ?
 700             irb->mt->num_samples : 1;
 701          unsigned num_layers = irb->layer_count;
 702          for (unsigned layer = 0; layer < num_layers; layer++) {
 703             if (!do_single_blorp_clear(
 704                     brw, fb, rb, buf, partial_clear, encode_srgb,
 705                     irb->mt_layer + layer * layer_multiplier)) {
 706                return false;
 707             }
 708          }
 709       } else {
 710          unsigned layer = irb->mt_layer;
 711          if (!do_single_blorp_clear(brw, fb, rb, buf, partial_clear,
 712                                     encode_srgb, layer))
 713             return false;
 714       }
 715
 716       irb->need_downsample = true;
 717    }
 718
 719    return true;
 720 }
 721
 722 void
 723 brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt)
 724 {
 725    DBG("%s to mt %p\n", __FUNCTION__, mt);
 726
 727    const mesa_format format = _mesa_get_srgb_format_linear(mt->format);
 728
 729    intel_miptree_check_level_layer(mt, 0 /* level */, 0 /* layer */);
 730    intel_miptree_used_for_rendering(mt);
 731
 732    struct isl_surf isl_tmp[2];
 733    struct brw_blorp_surf surf;
 734    unsigned level = 0;
 735    brw_blorp_surf_for_miptree(brw, &surf, mt, true, &level, isl_tmp);
 736
 737    brw_blorp_ccs_resolve(brw, &surf, brw_blorp_to_isl_format(brw, format, true));
 738
 739    mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
 740 }
 741
 742 static void
 743 gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 744                     unsigned int level, unsigned int layer, enum gen6_hiz_op op)
 745 {
 746    intel_miptree_check_level_layer(mt, level, layer);
 747    intel_miptree_used_for_rendering(mt);
 748
 749    assert(intel_miptree_level_has_hiz(mt, level));
 750
 751    struct isl_surf isl_tmp[2];
 752    struct brw_blorp_surf surf;
 753    brw_blorp_surf_for_miptree(brw, &surf, mt, true, &level, isl_tmp);
 754
 755    blorp_gen6_hiz_op(brw, &surf, level, layer, op);
 756 }
 757
 758 /**
 759  * Perform a HiZ or depth resolve operation.
 760  *
 761  * For an overview of HiZ ops, see the following sections of the Sandy Bridge
 762  * PRM, Volume 1, Part 2:
 763  *   - 7.5.3.1 Depth Buffer Clear
 764  *   - 7.5.3.2 Depth Buffer Resolve
 765  *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
 766  */
 767 void
 768 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 769                unsigned int level, unsigned int layer, enum gen6_hiz_op op)
 770 {
 771    const char *opname = NULL;
 772
 773    switch (op) {
 774    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 775       opname = "depth resolve";
 776       break;
 777    case GEN6_HIZ_OP_HIZ_RESOLVE:
 778       opname = "hiz ambiguate";
 779       break;
 780    case GEN6_HIZ_OP_DEPTH_CLEAR:
 781       opname = "depth clear";
 782       break;
 783    case GEN6_HIZ_OP_NONE:
 784       opname = "noop?";
 785       break;
 786    }
 787
 788    DBG("%s %s to mt %p level %d layer %d\n",
 789        __func__, opname, mt, level, layer);
 790
 791    if (brw->gen >= 8) {
 792       gen8_hiz_exec(brw, mt, level, layer, op);
 793    } else {
 794       gen6_blorp_hiz_exec(brw, mt, level, layer, op);
 795    }
 796 }