2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/blend.h"
27 #include "main/fbobject.h"
28 #include "main/renderbuffer.h"
29 #include "main/glformats.h"
31 #include "brw_blorp.h"
32 #include "brw_context.h"
33 #include "brw_defines.h"
34 #include "brw_meta_util.h"
35 #include "brw_state.h"
36 #include "intel_fbo.h"
37 #include "common/gen_debug.h"
39 #define FILE_DEBUG_FLAG DEBUG_BLORP
42 brw_blorp_lookup_shader(struct blorp_context
*blorp
,
43 const void *key
, uint32_t key_size
,
44 uint32_t *kernel_out
, void *prog_data_out
)
46 struct brw_context
*brw
= blorp
->driver_ctx
;
47 return brw_search_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
,
48 key
, key_size
, kernel_out
, prog_data_out
);
52 brw_blorp_upload_shader(struct blorp_context
*blorp
,
53 const void *key
, uint32_t key_size
,
54 const void *kernel
, uint32_t kernel_size
,
55 const struct brw_stage_prog_data
*prog_data
,
56 uint32_t prog_data_size
,
57 uint32_t *kernel_out
, void *prog_data_out
)
59 struct brw_context
*brw
= blorp
->driver_ctx
;
60 brw_upload_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
, key
, key_size
,
61 kernel
, kernel_size
, prog_data
, prog_data_size
,
62 kernel_out
, prog_data_out
);
67 brw_blorp_init(struct brw_context
*brw
)
69 blorp_init(&brw
->blorp
, brw
, &brw
->isl_dev
);
71 brw
->blorp
.compiler
= brw
->screen
->compiler
;
76 brw
->blorp
.exec
= gen45_blorp_exec
;
78 brw
->blorp
.exec
= gen4_blorp_exec
;
82 brw
->blorp
.exec
= gen5_blorp_exec
;
85 brw
->blorp
.mocs
.tex
= 0;
86 brw
->blorp
.mocs
.rb
= 0;
87 brw
->blorp
.mocs
.vb
= 0;
88 brw
->blorp
.exec
= gen6_blorp_exec
;
91 brw
->blorp
.mocs
.tex
= GEN7_MOCS_L3
;
92 brw
->blorp
.mocs
.rb
= GEN7_MOCS_L3
;
93 brw
->blorp
.mocs
.vb
= GEN7_MOCS_L3
;
94 if (brw
->is_haswell
) {
95 brw
->blorp
.exec
= gen75_blorp_exec
;
97 brw
->blorp
.exec
= gen7_blorp_exec
;
101 brw
->blorp
.mocs
.tex
= BDW_MOCS_WB
;
102 brw
->blorp
.mocs
.rb
= BDW_MOCS_PTE
;
103 brw
->blorp
.mocs
.vb
= BDW_MOCS_WB
;
104 brw
->blorp
.exec
= gen8_blorp_exec
;
107 brw
->blorp
.mocs
.tex
= SKL_MOCS_WB
;
108 brw
->blorp
.mocs
.rb
= SKL_MOCS_PTE
;
109 brw
->blorp
.mocs
.vb
= SKL_MOCS_WB
;
110 brw
->blorp
.exec
= gen9_blorp_exec
;
113 unreachable("Invalid gen");
116 brw
->blorp
.lookup_shader
= brw_blorp_lookup_shader
;
117 brw
->blorp
.upload_shader
= brw_blorp_upload_shader
;
121 blorp_surf_for_miptree(struct brw_context
*brw
,
122 struct blorp_surf
*surf
,
123 struct intel_mipmap_tree
*mt
,
124 bool is_render_target
,
125 uint32_t safe_aux_usage
,
127 unsigned start_layer
, unsigned num_layers
,
128 struct isl_surf tmp_surfs
[2])
130 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
131 mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
132 const unsigned num_samples
= MAX2(1, mt
->num_samples
);
133 for (unsigned i
= 0; i
< num_layers
; i
++) {
134 for (unsigned s
= 0; s
< num_samples
; s
++) {
135 const unsigned phys_layer
= (start_layer
+ i
) * num_samples
+ s
;
136 intel_miptree_check_level_layer(mt
, *level
, phys_layer
);
140 for (unsigned i
= 0; i
< num_layers
; i
++)
141 intel_miptree_check_level_layer(mt
, *level
, start_layer
+ i
);
144 intel_miptree_get_isl_surf(brw
, mt
, &tmp_surfs
[0]);
145 surf
->surf
= &tmp_surfs
[0];
146 surf
->addr
= (struct blorp_address
) {
148 .offset
= mt
->offset
,
149 .read_domains
= is_render_target
? I915_GEM_DOMAIN_RENDER
:
150 I915_GEM_DOMAIN_SAMPLER
,
151 .write_domain
= is_render_target
? I915_GEM_DOMAIN_RENDER
: 0,
154 struct isl_surf
*aux_surf
= &tmp_surfs
[1];
155 intel_miptree_get_aux_isl_surf(brw
, mt
, aux_surf
, &surf
->aux_usage
);
157 if (surf
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
158 if (surf
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
159 /* If we're not going to use it as a depth buffer, resolve HiZ */
160 if (!(safe_aux_usage
& (1 << ISL_AUX_USAGE_HIZ
))) {
161 for (unsigned i
= 0; i
< num_layers
; i
++) {
162 intel_miptree_slice_resolve_depth(brw
, mt
, *level
,
165 /* If we're rendering to it then we'll need a HiZ resolve once
166 * we're done before we can use it with HiZ again.
168 if (is_render_target
)
169 intel_miptree_slice_set_needs_hiz_resolve(mt
, *level
,
172 surf
->aux_usage
= ISL_AUX_USAGE_NONE
;
174 } else if (!(safe_aux_usage
& (1 << surf
->aux_usage
))) {
176 if (safe_aux_usage
& (1 << ISL_AUX_USAGE_CCS_E
))
177 flags
|= INTEL_MIPTREE_IGNORE_CCS_E
;
179 intel_miptree_resolve_color(brw
, mt
,
180 *level
, start_layer
, num_layers
, flags
);
182 assert(!intel_miptree_has_color_unresolved(mt
, *level
, 1,
183 start_layer
, num_layers
));
184 surf
->aux_usage
= ISL_AUX_USAGE_NONE
;
188 if (is_render_target
)
189 intel_miptree_used_for_rendering(brw
, mt
, *level
,
190 start_layer
, num_layers
);
192 if (surf
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
193 /* We only really need a clear color if we also have an auxiliary
194 * surface. Without one, it does nothing.
196 surf
->clear_color
= mt
->fast_clear_color
;
198 surf
->aux_surf
= aux_surf
;
199 surf
->aux_addr
= (struct blorp_address
) {
200 .read_domains
= is_render_target
? I915_GEM_DOMAIN_RENDER
:
201 I915_GEM_DOMAIN_SAMPLER
,
202 .write_domain
= is_render_target
? I915_GEM_DOMAIN_RENDER
: 0,
206 surf
->aux_addr
.buffer
= mt
->mcs_buf
->bo
;
207 surf
->aux_addr
.offset
= mt
->mcs_buf
->offset
;
209 assert(surf
->aux_usage
== ISL_AUX_USAGE_HIZ
);
211 surf
->aux_addr
.buffer
= mt
->hiz_buf
->aux_base
.bo
;
212 surf
->aux_addr
.offset
= mt
->hiz_buf
->aux_base
.offset
;
215 surf
->aux_addr
= (struct blorp_address
) {
218 memset(&surf
->clear_color
, 0, sizeof(surf
->clear_color
));
220 assert((surf
->aux_usage
== ISL_AUX_USAGE_NONE
) ==
221 (surf
->aux_addr
.buffer
== NULL
));
223 /* ISL wants real levels, not offset ones. */
224 *level
-= mt
->first_level
;
227 static enum isl_format
228 brw_blorp_to_isl_format(struct brw_context
*brw
, mesa_format format
,
229 bool is_render_target
)
232 case MESA_FORMAT_NONE
:
233 return ISL_FORMAT_UNSUPPORTED
;
234 case MESA_FORMAT_S_UINT8
:
235 return ISL_FORMAT_R8_UINT
;
236 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
237 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
238 return ISL_FORMAT_R24_UNORM_X8_TYPELESS
;
239 case MESA_FORMAT_Z_FLOAT32
:
240 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
241 return ISL_FORMAT_R32_FLOAT
;
242 case MESA_FORMAT_Z_UNORM16
:
243 return ISL_FORMAT_R16_UNORM
;
245 if (is_render_target
) {
246 assert(brw
->format_supported_as_render_target
[format
]);
247 return brw
->render_target_format
[format
];
249 return brw_isl_format_for_mesa_format(format
);
257 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
258 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
260 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
263 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
265 * which is simply adding 4 then modding by 8 (or anding with 7).
267 * We then may need to apply workarounds for textureGather hardware bugs.
269 static enum isl_channel_select
270 swizzle_to_scs(GLenum swizzle
)
272 return (enum isl_channel_select
)((swizzle
+ 4) & 7);
276 physical_to_logical_layer(struct intel_mipmap_tree
*mt
,
277 unsigned physical_layer
)
279 if (mt
->num_samples
> 1 &&
280 (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
281 mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
)) {
282 assert(physical_layer
% mt
->num_samples
== 0);
283 return physical_layer
/ mt
->num_samples
;
285 return physical_layer
;
290 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
291 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
292 * the physical layer holding sample 0. So, for example, if
293 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
297 brw_blorp_blit_miptrees(struct brw_context
*brw
,
298 struct intel_mipmap_tree
*src_mt
,
299 unsigned src_level
, unsigned src_layer
,
300 mesa_format src_format
, int src_swizzle
,
301 struct intel_mipmap_tree
*dst_mt
,
302 unsigned dst_level
, unsigned dst_layer
,
303 mesa_format dst_format
,
304 float src_x0
, float src_y0
,
305 float src_x1
, float src_y1
,
306 float dst_x0
, float dst_y0
,
307 float dst_x1
, float dst_y1
,
308 GLenum filter
, bool mirror_x
, bool mirror_y
,
309 bool decode_srgb
, bool encode_srgb
)
311 /* Blorp operates in logical layers */
312 src_layer
= physical_to_logical_layer(src_mt
, src_layer
);
313 dst_layer
= physical_to_logical_layer(dst_mt
, dst_layer
);
315 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
316 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
318 src_mt
->num_samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
319 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
320 dst_mt
->num_samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
321 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
324 if (!decode_srgb
&& _mesa_get_format_color_encoding(src_format
) == GL_SRGB
)
325 src_format
= _mesa_get_srgb_format_linear(src_format
);
327 if (!encode_srgb
&& _mesa_get_format_color_encoding(dst_format
) == GL_SRGB
)
328 dst_format
= _mesa_get_srgb_format_linear(dst_format
);
330 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
331 * texture, the above code configures the source format for L32_FLOAT or
332 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
333 * the SAMPLE message appears to handle multisampled L32_FLOAT and
334 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
335 * around the problem by using a source format of R32_FLOAT. This
336 * shouldn't affect rendering correctness, since the destination format is
337 * R32_FLOAT, so only the contents of the red channel matters.
340 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1 &&
341 src_mt
->format
== dst_mt
->format
&&
342 (dst_format
== MESA_FORMAT_L_FLOAT32
||
343 dst_format
== MESA_FORMAT_I_FLOAT32
)) {
344 src_format
= dst_format
= MESA_FORMAT_R_FLOAT32
;
347 uint32_t src_usage_flags
= (1 << ISL_AUX_USAGE_MCS
);
348 if (src_format
== src_mt
->format
)
349 src_usage_flags
|= (1 << ISL_AUX_USAGE_CCS_E
);
351 uint32_t dst_usage_flags
= (1 << ISL_AUX_USAGE_MCS
);
352 if (dst_format
== dst_mt
->format
) {
353 dst_usage_flags
|= (1 << ISL_AUX_USAGE_CCS_E
) |
354 (1 << ISL_AUX_USAGE_CCS_D
);
357 struct isl_surf tmp_surfs
[4];
358 struct blorp_surf src_surf
, dst_surf
;
359 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, false, src_usage_flags
,
360 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
361 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, true, dst_usage_flags
,
362 &dst_level
, dst_layer
, 1, &tmp_surfs
[2]);
364 struct isl_swizzle src_isl_swizzle
= {
365 .r
= swizzle_to_scs(GET_SWZ(src_swizzle
, 0)),
366 .g
= swizzle_to_scs(GET_SWZ(src_swizzle
, 1)),
367 .b
= swizzle_to_scs(GET_SWZ(src_swizzle
, 2)),
368 .a
= swizzle_to_scs(GET_SWZ(src_swizzle
, 3)),
371 struct blorp_batch batch
;
372 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
373 blorp_blit(&batch
, &src_surf
, src_level
, src_layer
,
374 brw_blorp_to_isl_format(brw
, src_format
, false), src_isl_swizzle
,
375 &dst_surf
, dst_level
, dst_layer
,
376 brw_blorp_to_isl_format(brw
, dst_format
, true),
377 ISL_SWIZZLE_IDENTITY
,
378 src_x0
, src_y0
, src_x1
, src_y1
,
379 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
380 filter
, mirror_x
, mirror_y
);
381 blorp_batch_finish(&batch
);
385 brw_blorp_copy_miptrees(struct brw_context
*brw
,
386 struct intel_mipmap_tree
*src_mt
,
387 unsigned src_level
, unsigned src_layer
,
388 struct intel_mipmap_tree
*dst_mt
,
389 unsigned dst_level
, unsigned dst_layer
,
390 unsigned src_x
, unsigned src_y
,
391 unsigned dst_x
, unsigned dst_y
,
392 unsigned src_width
, unsigned src_height
)
394 DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
395 "to %dx %s mt %p %d %d (%d,%d)\n",
397 src_mt
->num_samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
398 src_level
, src_layer
, src_x
, src_y
, src_width
, src_height
,
399 dst_mt
->num_samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
400 dst_level
, dst_layer
, dst_x
, dst_y
);
402 struct isl_surf tmp_surfs
[4];
403 struct blorp_surf src_surf
, dst_surf
;
404 blorp_surf_for_miptree(brw
, &src_surf
, src_mt
, false,
405 (1 << ISL_AUX_USAGE_MCS
) |
406 (1 << ISL_AUX_USAGE_CCS_E
),
407 &src_level
, src_layer
, 1, &tmp_surfs
[0]);
408 blorp_surf_for_miptree(brw
, &dst_surf
, dst_mt
, true,
409 (1 << ISL_AUX_USAGE_MCS
) |
410 (1 << ISL_AUX_USAGE_CCS_E
),
411 &dst_level
, dst_layer
, 1, &tmp_surfs
[2]);
413 struct blorp_batch batch
;
414 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
415 blorp_copy(&batch
, &src_surf
, src_level
, src_layer
,
416 &dst_surf
, dst_level
, dst_layer
,
417 src_x
, src_y
, dst_x
, dst_y
, src_width
, src_height
);
418 blorp_batch_finish(&batch
);
421 static struct intel_mipmap_tree
*
422 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
424 struct intel_mipmap_tree
*mt
= irb
->mt
;
425 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
431 blorp_get_texture_swizzle(const struct intel_renderbuffer
*irb
)
433 return irb
->Base
.Base
._BaseFormat
== GL_RGB
?
434 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ONE
) :
439 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
440 struct intel_renderbuffer
*src_irb
, mesa_format src_format
,
441 struct intel_renderbuffer
*dst_irb
, mesa_format dst_format
,
442 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
443 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
444 GLenum filter
, bool mirror_x
, bool mirror_y
)
446 const struct gl_context
*ctx
= &brw
->ctx
;
448 /* Find source/dst miptrees */
449 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
450 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
452 const bool do_srgb
= ctx
->Color
.sRGBEnabled
;
455 brw_blorp_blit_miptrees(brw
,
456 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
457 src_format
, blorp_get_texture_swizzle(src_irb
),
458 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
460 srcX0
, srcY0
, srcX1
, srcY1
,
461 dstX0
, dstY0
, dstX1
, dstY1
,
462 filter
, mirror_x
, mirror_y
,
465 dst_irb
->need_downsample
= true;
469 try_blorp_blit(struct brw_context
*brw
,
470 const struct gl_framebuffer
*read_fb
,
471 const struct gl_framebuffer
*draw_fb
,
472 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
473 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
474 GLenum filter
, GLbitfield buffer_bit
)
476 struct gl_context
*ctx
= &brw
->ctx
;
478 /* Sync up the state of window system buffers. We need to do this before
479 * we go looking for the buffers.
481 intel_prepare_render(brw
);
483 bool mirror_x
, mirror_y
;
484 if (brw_meta_mirror_clip_and_scissor(ctx
, read_fb
, draw_fb
,
485 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
486 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
487 &mirror_x
, &mirror_y
))
491 struct intel_renderbuffer
*src_irb
;
492 struct intel_renderbuffer
*dst_irb
;
493 struct intel_mipmap_tree
*src_mt
;
494 struct intel_mipmap_tree
*dst_mt
;
495 switch (buffer_bit
) {
496 case GL_COLOR_BUFFER_BIT
:
497 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
498 for (unsigned i
= 0; i
< draw_fb
->_NumColorDrawBuffers
; ++i
) {
499 dst_irb
= intel_renderbuffer(draw_fb
->_ColorDrawBuffers
[i
]);
501 do_blorp_blit(brw
, buffer_bit
,
502 src_irb
, src_irb
->Base
.Base
.Format
,
503 dst_irb
, dst_irb
->Base
.Base
.Format
,
504 srcX0
, srcY0
, srcX1
, srcY1
,
505 dstX0
, dstY0
, dstX1
, dstY1
,
506 filter
, mirror_x
, mirror_y
);
509 case GL_DEPTH_BUFFER_BIT
:
511 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
513 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
514 src_mt
= find_miptree(buffer_bit
, src_irb
);
515 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
517 /* We can't handle format conversions between Z24 and other formats
518 * since we have to lie about the surface format. See the comments in
519 * brw_blorp_surface_info::set().
521 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
522 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
))
525 /* We also can't handle any combined depth-stencil formats because we
526 * have to reinterpret as a color format.
528 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
529 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
532 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
533 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
534 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
535 filter
, mirror_x
, mirror_y
);
537 case GL_STENCIL_BUFFER_BIT
:
538 /* Blorp doesn't support combined depth stencil which is all we have
545 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
547 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
548 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
549 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
550 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
551 filter
, mirror_x
, mirror_y
);
554 unreachable("not reached");
561 brw_blorp_copytexsubimage(struct brw_context
*brw
,
562 struct gl_renderbuffer
*src_rb
,
563 struct gl_texture_image
*dst_image
,
565 int srcX0
, int srcY0
,
566 int dstX0
, int dstY0
,
567 int width
, int height
)
569 struct gl_context
*ctx
= &brw
->ctx
;
570 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
571 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
573 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
574 if (brw
->ctx
._ImageTransferState
)
577 /* Sync up the state of window system buffers. We need to do this before
578 * we go looking at the src renderbuffer's miptree.
580 intel_prepare_render(brw
);
582 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
583 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
585 /* There is support for only up to eight samples. */
586 if (src_mt
->num_samples
> 8 || dst_mt
->num_samples
> 8)
589 if (_mesa_get_format_base_format(src_rb
->Format
) !=
590 _mesa_get_format_base_format(dst_image
->TexFormat
)) {
594 /* We can't handle format conversions between Z24 and other formats since
595 * we have to lie about the surface format. See the comments in
596 * brw_blorp_surface_info::set().
598 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
599 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
)) {
603 /* We also can't handle any combined depth-stencil formats because we
604 * have to reinterpret as a color format.
606 if (_mesa_get_format_base_format(src_mt
->format
) == GL_DEPTH_STENCIL
||
607 _mesa_get_format_base_format(dst_mt
->format
) == GL_DEPTH_STENCIL
)
610 if (!brw
->format_supported_as_render_target
[dst_image
->TexFormat
])
613 /* Source clipping shouldn't be necessary, since copytexsubimage (in
614 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
617 * Destination clipping shouldn't be necessary since the restrictions on
618 * glCopyTexSubImage prevent the user from specifying a destination rectangle
619 * that falls outside the bounds of the destination texture.
620 * See error_check_subtexture_dimensions().
623 int srcY1
= srcY0
+ height
;
624 int srcX1
= srcX0
+ width
;
625 int dstX1
= dstX0
+ width
;
626 int dstY1
= dstY0
+ height
;
628 /* Account for the fact that in the system framebuffer, the origin is at
631 bool mirror_y
= false;
632 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
633 GLint tmp
= src_rb
->Height
- srcY0
;
634 srcY0
= src_rb
->Height
- srcY1
;
639 /* Account for face selection and texture view MinLayer */
640 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
641 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
643 brw_blorp_blit_miptrees(brw
,
644 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
645 src_rb
->Format
, blorp_get_texture_swizzle(src_irb
),
646 dst_mt
, dst_level
, dst_slice
,
647 dst_image
->TexFormat
,
648 srcX0
, srcY0
, srcX1
, srcY1
,
649 dstX0
, dstY0
, dstX1
, dstY1
,
650 GL_NEAREST
, false, mirror_y
,
653 /* If we're copying to a packed depth stencil texture and the source
654 * framebuffer has separate stencil, we need to also copy the stencil data
657 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
658 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
660 src_irb
= intel_renderbuffer(src_rb
);
661 src_mt
= src_irb
->mt
;
663 if (src_mt
->stencil_mt
)
664 src_mt
= src_mt
->stencil_mt
;
665 if (dst_mt
->stencil_mt
)
666 dst_mt
= dst_mt
->stencil_mt
;
668 if (src_mt
!= dst_mt
) {
669 brw_blorp_blit_miptrees(brw
,
670 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
672 blorp_get_texture_swizzle(src_irb
),
673 dst_mt
, dst_level
, dst_slice
,
675 srcX0
, srcY0
, srcX1
, srcY1
,
676 dstX0
, dstY0
, dstX1
, dstY1
,
677 GL_NEAREST
, false, mirror_y
,
687 brw_blorp_framebuffer(struct brw_context
*brw
,
688 struct gl_framebuffer
*readFb
,
689 struct gl_framebuffer
*drawFb
,
690 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
691 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
692 GLbitfield mask
, GLenum filter
)
694 static GLbitfield buffer_bits
[] = {
697 GL_STENCIL_BUFFER_BIT
,
700 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
701 if ((mask
& buffer_bits
[i
]) &&
702 try_blorp_blit(brw
, readFb
, drawFb
,
703 srcX0
, srcY0
, srcX1
, srcY1
,
704 dstX0
, dstY0
, dstX1
, dstY1
,
705 filter
, buffer_bits
[i
])) {
706 mask
&= ~buffer_bits
[i
];
714 set_write_disables(const struct intel_renderbuffer
*irb
,
715 const GLubyte
*color_mask
, bool *color_write_disable
)
717 /* Format information in the renderbuffer represents the requirements
718 * given by the client. There are cases where the backing miptree uses,
719 * for example, RGBA to represent RGBX. Since the client is only expecting
720 * RGB we can treat alpha as not used and write whatever we like into it.
722 const GLenum base_format
= irb
->Base
.Base
._BaseFormat
;
723 const int components
= _mesa_base_format_component_count(base_format
);
724 bool disables
= false;
726 assert(components
> 0);
728 for (int i
= 0; i
< components
; i
++) {
729 color_write_disable
[i
] = !color_mask
[i
];
730 disables
= disables
|| !color_mask
[i
];
737 irb_logical_mt_layer(struct intel_renderbuffer
*irb
)
739 return physical_to_logical_layer(irb
->mt
, irb
->mt_layer
);
743 do_single_blorp_clear(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
744 struct gl_renderbuffer
*rb
, unsigned buf
,
745 bool partial_clear
, bool encode_srgb
)
747 struct gl_context
*ctx
= &brw
->ctx
;
748 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
749 mesa_format format
= irb
->mt
->format
;
750 uint32_t x0
, x1
, y0
, y1
;
752 if (!encode_srgb
&& _mesa_get_format_color_encoding(format
) == GL_SRGB
)
753 format
= _mesa_get_srgb_format_linear(format
);
761 y0
= rb
->Height
- fb
->_Ymax
;
762 y1
= rb
->Height
- fb
->_Ymin
;
765 /* If the clear region is empty, just return. */
766 if (x0
== x1
|| y0
== y1
)
769 bool can_fast_clear
= !partial_clear
;
771 bool color_write_disable
[4] = { false, false, false, false };
772 if (set_write_disables(irb
, ctx
->Color
.ColorMask
[buf
], color_write_disable
))
773 can_fast_clear
= false;
775 if (irb
->mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
||
776 !brw_is_color_fast_clear_compatible(brw
, irb
->mt
, &ctx
->Color
.ClearColor
))
777 can_fast_clear
= false;
779 const unsigned logical_layer
= irb_logical_mt_layer(irb
);
780 const enum intel_fast_clear_state fast_clear_state
=
781 intel_miptree_get_fast_clear_state(irb
->mt
, irb
->mt_level
,
784 /* Surface state can only record one fast clear color value. Therefore
785 * unless different levels/layers agree on the color it can be used to
786 * represent only single level/layer. Here it will be reserved for the
787 * first slice (level 0, layer 0).
789 if (irb
->layer_count
> 1 || irb
->mt_level
|| irb
->mt_layer
)
790 can_fast_clear
= false;
792 if (can_fast_clear
) {
793 union isl_color_value clear_color
=
794 brw_meta_convert_fast_clear_color(brw
, irb
->mt
,
795 &ctx
->Color
.ClearColor
);
797 /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
798 * is redundant and can be skipped.
800 if (fast_clear_state
== INTEL_FAST_CLEAR_STATE_CLEAR
&&
801 memcmp(&irb
->mt
->fast_clear_color
,
802 &clear_color
, sizeof(clear_color
)) == 0)
805 irb
->mt
->fast_clear_color
= clear_color
;
807 /* If the MCS buffer hasn't been allocated yet, we need to allocate
810 if (!irb
->mt
->mcs_buf
) {
811 assert(!intel_miptree_is_lossless_compressed(brw
, irb
->mt
));
812 if (!intel_miptree_alloc_non_msrt_mcs(brw
, irb
->mt
, false)) {
813 /* MCS allocation failed--probably this will only happen in
814 * out-of-memory conditions. But in any case, try to recover
815 * by falling back to a non-blorp clear technique.
822 const unsigned num_layers
= fb
->MaxNumLayers
? irb
->layer_count
: 1;
824 /* We can't setup the blorp_surf until we've allocated the MCS above */
825 struct isl_surf isl_tmp
[2];
826 struct blorp_surf surf
;
827 unsigned level
= irb
->mt_level
;
828 blorp_surf_for_miptree(brw
, &surf
, irb
->mt
, true,
829 (1 << ISL_AUX_USAGE_MCS
) |
830 (1 << ISL_AUX_USAGE_CCS_E
) |
831 (1 << ISL_AUX_USAGE_CCS_D
),
832 &level
, logical_layer
, num_layers
, isl_tmp
);
834 if (can_fast_clear
) {
835 DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__
,
836 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
838 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
840 * "Any transition from any value in {Clear, Render, Resolve} to a
841 * different value in {Clear, Render, Resolve} requires end of pipe
844 * In other words, fast clear ops are not properly synchronized with
845 * other drawing. We need to use a PIPE_CONTROL to ensure that the
846 * contents of the previous draw hit the render target before we resolve
847 * and again afterwards to ensure that the resolve is complete before we
848 * do any more regular drawing.
850 brw_emit_pipe_control_flush(brw
,
851 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
852 PIPE_CONTROL_CS_STALL
);
854 struct blorp_batch batch
;
855 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
856 blorp_fast_clear(&batch
, &surf
,
857 brw
->render_target_format
[format
],
858 level
, logical_layer
, num_layers
,
860 blorp_batch_finish(&batch
);
862 brw_emit_pipe_control_flush(brw
,
863 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
864 PIPE_CONTROL_CS_STALL
);
866 /* Now that the fast clear has occurred, put the buffer in
867 * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
870 intel_miptree_set_fast_clear_state(brw
, irb
->mt
, irb
->mt_level
,
871 logical_layer
, num_layers
,
872 INTEL_FAST_CLEAR_STATE_CLEAR
);
874 DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__
,
875 irb
->mt
, irb
->mt_level
, irb
->mt_layer
, num_layers
);
877 union isl_color_value clear_color
;
878 memcpy(clear_color
.f32
, ctx
->Color
.ClearColor
.f
, sizeof(float) * 4);
880 struct blorp_batch batch
;
881 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
882 blorp_clear(&batch
, &surf
,
883 brw
->render_target_format
[format
],
884 ISL_SWIZZLE_IDENTITY
,
885 level
, irb_logical_mt_layer(irb
), num_layers
,
887 clear_color
, color_write_disable
);
888 blorp_batch_finish(&batch
);
895 brw_blorp_clear_color(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
896 GLbitfield mask
, bool partial_clear
, bool encode_srgb
)
898 for (unsigned buf
= 0; buf
< fb
->_NumColorDrawBuffers
; buf
++) {
899 struct gl_renderbuffer
*rb
= fb
->_ColorDrawBuffers
[buf
];
900 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
902 /* Only clear the buffers present in the provided mask */
903 if (((1 << fb
->_ColorDrawBufferIndexes
[buf
]) & mask
) == 0)
906 /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
907 * the framebuffer can be complete with some attachments missing. In
908 * this case the _ColorDrawBuffers pointer will be NULL.
913 if (!do_single_blorp_clear(brw
, fb
, rb
, buf
, partial_clear
,
918 irb
->need_downsample
= true;
925 brw_blorp_resolve_color(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
926 unsigned level
, unsigned layer
)
928 DBG("%s to mt %p level %u layer %u\n", __FUNCTION__
, mt
, level
, layer
);
930 const mesa_format format
= _mesa_get_srgb_format_linear(mt
->format
);
932 struct isl_surf isl_tmp
[2];
933 struct blorp_surf surf
;
934 blorp_surf_for_miptree(brw
, &surf
, mt
, true,
935 (1 << ISL_AUX_USAGE_CCS_E
) |
936 (1 << ISL_AUX_USAGE_CCS_D
),
937 &level
, layer
, 1 /* num_layers */,
940 enum blorp_fast_clear_op resolve_op
;
942 if (surf
.aux_usage
== ISL_AUX_USAGE_CCS_E
)
943 resolve_op
= BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
945 resolve_op
= BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
947 assert(surf
.aux_usage
== ISL_AUX_USAGE_CCS_D
);
948 /* Broadwell and earlier do not have a partial resolve */
949 resolve_op
= BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
952 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
954 * "Any transition from any value in {Clear, Render, Resolve} to a
955 * different value in {Clear, Render, Resolve} requires end of pipe
958 * In other words, fast clear ops are not properly synchronized with
959 * other drawing. We need to use a PIPE_CONTROL to ensure that the
960 * contents of the previous draw hit the render target before we resolve
961 * and again afterwards to ensure that the resolve is complete before we
962 * do any more regular drawing.
964 brw_emit_pipe_control_flush(brw
,
965 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
966 PIPE_CONTROL_CS_STALL
);
969 struct blorp_batch batch
;
970 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
971 blorp_ccs_resolve(&batch
, &surf
, level
, layer
,
972 brw_blorp_to_isl_format(brw
, format
, true),
974 blorp_batch_finish(&batch
);
976 /* See comment above */
977 brw_emit_pipe_control_flush(brw
,
978 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
979 PIPE_CONTROL_CS_STALL
);
983 * Perform a HiZ or depth resolve operation.
985 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
986 * PRM, Volume 1, Part 2:
987 * - 7.5.3.1 Depth Buffer Clear
988 * - 7.5.3.2 Depth Buffer Resolve
989 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
992 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
993 unsigned int level
, unsigned int start_layer
,
994 unsigned int num_layers
, enum blorp_hiz_op op
)
996 const char *opname
= NULL
;
999 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
1000 opname
= "depth resolve";
1002 case BLORP_HIZ_OP_HIZ_RESOLVE
:
1003 opname
= "hiz ambiguate";
1005 case BLORP_HIZ_OP_DEPTH_CLEAR
:
1006 opname
= "depth clear";
1008 case BLORP_HIZ_OP_NONE
:
1013 DBG("%s %s to mt %p level %d layers %d-%d\n",
1014 __func__
, opname
, mt
, level
, start_layer
, start_layer
+ num_layers
- 1);
1016 /* The following stalls and flushes are only documented to be required for
1017 * HiZ clear operations. However, they also seem to be required for the
1018 * HiZ resolve operation which is basically the same as a fast clear only a
1019 * different value is written into the HiZ surface.
1021 if (op
== BLORP_HIZ_OP_DEPTH_CLEAR
|| op
== BLORP_HIZ_OP_HIZ_RESOLVE
) {
1022 if (brw
->gen
== 6) {
1023 /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
1025 * "If other rendering operations have preceded this clear, a
1026 * PIPE_CONTROL with write cache flush enabled and Z-inhibit
1027 * disabled must be issued before the rectangle primitive used for
1028 * the depth buffer clear operation.
1030 brw_emit_pipe_control_flush(brw
,
1031 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1032 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1033 PIPE_CONTROL_CS_STALL
);
1034 } else if (brw
->gen
>= 7) {
1036 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
1038 * If other rendering operations have preceded this clear, a
1039 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
1040 * enabled must be issued before the rectangle primitive used for
1041 * the depth buffer clear operation.
1043 * Same applies for Gen8 and Gen9.
1045 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
1046 * PIPE_CONTROL, Depth Cache Flush Enable:
1048 * This bit must not be set when Depth Stall Enable bit is set in
1051 * This is confirmed to hold for real, HSW gets immediate gpu hangs.
1053 * Therefore issue two pipe control flushes, one for cache flush and
1054 * another for depth stall.
1056 brw_emit_pipe_control_flush(brw
,
1057 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1058 PIPE_CONTROL_CS_STALL
);
1060 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
1064 if (brw
->gen
>= 8) {
1065 for (unsigned a
= 0; a
< num_layers
; a
++)
1066 gen8_hiz_exec(brw
, mt
, level
, start_layer
+ a
, op
);
1068 assert(intel_miptree_level_has_hiz(mt
, level
));
1070 struct isl_surf isl_tmp
[2];
1071 struct blorp_surf surf
;
1072 blorp_surf_for_miptree(brw
, &surf
, mt
, true, (1 << ISL_AUX_USAGE_HIZ
),
1073 &level
, start_layer
, num_layers
, isl_tmp
);
1075 struct blorp_batch batch
;
1076 blorp_batch_init(&brw
->blorp
, &batch
, brw
, 0);
1077 blorp_hiz_op(&batch
, &surf
, level
, start_layer
, num_layers
, op
);
1078 blorp_batch_finish(&batch
);
1082 /* The following stalls and flushes are only documented to be required for
1083 * HiZ clear operations. However, they also seem to be required for the
1084 * HiZ resolve operation which is basically the same as a fast clear only a
1085 * different value is written into the HiZ surface.
1087 if (op
== BLORP_HIZ_OP_DEPTH_CLEAR
|| op
== BLORP_HIZ_OP_HIZ_RESOLVE
) {
1088 if (brw
->gen
== 6) {
1089 /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
1091 * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be
1092 * followed by a PIPE_CONTROL command with DEPTH_STALL bit set
1093 * and Then followed by Depth FLUSH'
1095 brw_emit_pipe_control_flush(brw
,
1096 PIPE_CONTROL_DEPTH_STALL
);
1098 brw_emit_pipe_control_flush(brw
,
1099 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1100 PIPE_CONTROL_CS_STALL
);