2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_batchbuffer.h"
26 #include "intel_fbo.h"
28 #include "brw_blorp.h"
29 #include "brw_defines.h"
30 #include "brw_state.h"
31 #include "gen6_blorp.h"
32 #include "gen7_blorp.h"
34 #define FILE_DEBUG_FLAG DEBUG_BLORP
36 brw_blorp_mip_info::brw_blorp_mip_info()
47 brw_blorp_surface_info::brw_blorp_surface_info()
48 : map_stencil_as_y_tiled(false),
54 brw_blorp_mip_info::set(struct intel_mipmap_tree
*mt
,
55 unsigned int level
, unsigned int layer
)
57 intel_miptree_check_level_layer(mt
, level
, layer
);
62 this->width
= mt
->level
[level
].width
;
63 this->height
= mt
->level
[level
].height
;
65 intel_miptree_get_image_offset(mt
, level
, layer
, &x_offset
, &y_offset
);
69 brw_blorp_surface_info::set(struct brw_context
*brw
,
70 struct intel_mipmap_tree
*mt
,
71 unsigned int level
, unsigned int layer
,
72 bool is_render_target
)
74 brw_blorp_mip_info::set(mt
, level
, layer
);
75 this->num_samples
= mt
->num_samples
;
76 this->array_spacing_lod0
= mt
->array_spacing_lod0
;
77 this->map_stencil_as_y_tiled
= false;
78 this->msaa_layout
= mt
->msaa_layout
;
82 /* The miptree is a W-tiled stencil buffer. Surface states can't be set
83 * up for W tiling, so we'll need to use Y tiling and have the WM
84 * program swizzle the coordinates.
86 this->map_stencil_as_y_tiled
= true;
87 this->brw_surfaceformat
= BRW_SURFACEFORMAT_R8_UNORM
;
89 case MESA_FORMAT_X8_Z24
:
90 /* It would make sense to use BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
91 * here, but unfortunately it isn't supported as a render target, which
92 * would prevent us from blitting to 24-bit depth.
94 * The miptree consists of 32 bits per pixel, arranged as 24-bit depth
95 * values interleaved with 8 "don't care" bits. Since depth values don't
96 * require any blending, it doesn't matter how we interpret the bit
97 * pattern as long as we copy the right amount of data, so just map it
100 this->brw_surfaceformat
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
102 case MESA_FORMAT_Z32_FLOAT
:
103 this->brw_surfaceformat
= BRW_SURFACEFORMAT_R32_FLOAT
;
105 case MESA_FORMAT_Z16
:
106 this->brw_surfaceformat
= BRW_SURFACEFORMAT_R16_UNORM
;
109 gl_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
110 if (is_render_target
) {
111 assert(brw
->format_supported_as_render_target
[linear_format
]);
112 this->brw_surfaceformat
= brw
->render_target_format
[linear_format
];
114 this->brw_surfaceformat
= brw_format_for_mesa_format(linear_format
);
123 * Split x_offset and y_offset into a base offset (in bytes) and a remaining
124 * x/y offset (in pixels). Note: we can't do this by calling
125 * intel_renderbuffer_tile_offsets(), because the offsets may have been
126 * adjusted to account for Y vs. W tiling differences. So we compute it
127 * directly from the adjusted offsets.
130 brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x
,
131 uint32_t *tile_y
) const
133 struct intel_region
*region
= mt
->region
;
134 uint32_t mask_x
, mask_y
;
136 intel_region_get_tile_masks(region
, &mask_x
, &mask_y
,
137 map_stencil_as_y_tiled
);
139 *tile_x
= x_offset
& mask_x
;
140 *tile_y
= y_offset
& mask_y
;
142 return intel_region_get_aligned_offset(region
, x_offset
& ~mask_x
,
144 map_stencil_as_y_tiled
);
148 brw_blorp_params::brw_blorp_params()
154 hiz_op(GEN6_HIZ_OP_NONE
),
155 fast_clear_op(GEN7_FAST_CLEAR_OP_NONE
),
159 color_write_disable
[0] = false;
160 color_write_disable
[1] = false;
161 color_write_disable
[2] = false;
162 color_write_disable
[3] = false;
167 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
168 unsigned int level
, unsigned int layer
, gen6_hiz_op op
)
170 const char *opname
= NULL
;
173 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
174 opname
= "depth resolve";
176 case GEN6_HIZ_OP_HIZ_RESOLVE
:
177 opname
= "hiz ambiguate";
179 case GEN6_HIZ_OP_DEPTH_CLEAR
:
180 opname
= "depth clear";
182 case GEN6_HIZ_OP_NONE
:
187 DBG("%s %s to mt %p level %d layer %d\n",
188 __FUNCTION__
, opname
, mt
, level
, layer
);
190 brw_hiz_op_params
params(mt
, level
, layer
, op
);
191 brw_blorp_exec(brw
, ¶ms
);
197 brw_blorp_exec(struct brw_context
*brw
, const brw_blorp_params
*params
)
199 struct gl_context
*ctx
= &brw
->ctx
;
200 uint32_t estimated_max_batch_usage
= 1500;
201 bool check_aperture_failed_once
= false;
203 /* Flush the sampler and render caches. We definitely need to flush the
204 * sampler cache so that we get updated contents from the render cache for
205 * the glBlitFramebuffer() source. Also, we are sometimes warned in the
206 * docs to flush the cache between reinterpretations of the same surface
207 * data with different formats, which blorp does for stencil and depth
210 intel_batchbuffer_emit_mi_flush(brw
);
213 intel_batchbuffer_require_space(brw
, estimated_max_batch_usage
, false);
214 intel_batchbuffer_save_state(brw
);
215 drm_intel_bo
*saved_bo
= brw
->batch
.bo
;
216 uint32_t saved_used
= brw
->batch
.used
;
217 uint32_t saved_state_batch_offset
= brw
->batch
.state_batch_offset
;
221 gen6_blorp_exec(brw
, params
);
224 gen7_blorp_exec(brw
, params
);
227 /* BLORP is not supported before Gen6. */
232 /* Make sure we didn't wrap the batch unintentionally, and make sure we
233 * reserved enough space that a wrap will never happen.
235 assert(brw
->batch
.bo
== saved_bo
);
236 assert((brw
->batch
.used
- saved_used
) * 4 +
237 (saved_state_batch_offset
- brw
->batch
.state_batch_offset
) <
238 estimated_max_batch_usage
);
239 /* Shut up compiler warnings on release build */
242 (void)saved_state_batch_offset
;
244 /* Check if the blorp op we just did would make our batch likely to fail to
245 * map all the BOs into the GPU at batch exec time later. If so, flush the
246 * batch and try again with nothing else in the batch.
248 if (dri_bufmgr_check_aperture_space(&brw
->batch
.bo
, 1)) {
249 if (!check_aperture_failed_once
) {
250 check_aperture_failed_once
= true;
251 intel_batchbuffer_reset_to_saved(brw
);
252 intel_batchbuffer_flush(brw
);
255 int ret
= intel_batchbuffer_flush(brw
);
256 WARN_ONCE(ret
== -ENOSPC
,
257 "i965: blorp emit exceeded available aperture space\n");
261 if (unlikely(brw
->always_flush_batch
))
262 intel_batchbuffer_flush(brw
);
264 /* We've smashed all state compared to what the normal 3D pipeline
265 * rendering tracks for GL.
267 brw
->state
.dirty
.brw
= ~0;
268 brw
->state
.dirty
.cache
= ~0;
269 brw
->state_batch_count
= 0;
270 brw
->batch
.need_workaround_flush
= true;
272 intel_batchbuffer_clear_cache(brw
);
274 /* Flush the sampler cache so any texturing from the destination is
277 intel_batchbuffer_emit_mi_flush(brw
);
280 brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree
*mt
,
287 depth
.set(mt
, level
, layer
);
289 /* Align the rectangle primitive to 8x4 pixels.
291 * During fast depth clears, the emitted rectangle primitive must be
292 * aligned to 8x4 pixels. From the Ivybridge PRM, Vol 2 Part 1 Section
293 * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
295 * If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
296 * aligned to an 8x4 pixel block relative to the upper left corner
297 * of the depth buffer [...]
299 * For hiz resolves, the rectangle must also be 8x4 aligned. Item
300 * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
301 * Ivybridge simulator require the alignment.
303 * To be safe, let's just align the rect for all hiz operations and all
304 * hardware generations.
306 * However, for some miptree slices of a Z24 texture, emitting an 8x4
307 * aligned rectangle that covers the slice may clobber adjacent slices if
308 * we strictly adhered to the texture alignments specified in the PRM. The
309 * Ivybridge PRM, Section "Alignment Unit Size", states that
310 * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
311 * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
312 * prevents the clobbering.
314 depth
.width
= ALIGN(depth
.width
, 8);
315 depth
.height
= ALIGN(depth
.height
, 4);
320 assert(intel_miptree_slice_has_hiz(mt
, level
, layer
));
322 switch (mt
->format
) {
323 case MESA_FORMAT_Z16
: depth_format
= BRW_DEPTHFORMAT_D16_UNORM
; break;
324 case MESA_FORMAT_Z32_FLOAT
: depth_format
= BRW_DEPTHFORMAT_D32_FLOAT
; break;
325 case MESA_FORMAT_X8_Z24
: depth_format
= BRW_DEPTHFORMAT_D24_UNORM_X8_UINT
; break;
326 default: assert(0); break;
331 brw_hiz_op_params::get_wm_prog(struct brw_context
*brw
,
332 brw_blorp_prog_data
**prog_data
) const