src/mesa/drivers/dri/i965/brw_blorp.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <errno.h>
  25 #include "intel_batchbuffer.h"
  26 #include "intel_fbo.h"
  27
  28 #include "brw_blorp.h"
  29 #include "brw_state.h"
  30
  31 #define FILE_DEBUG_FLAG DEBUG_BLORP
  32
  33 brw_blorp_mip_info::brw_blorp_mip_info()
  34    : mt(NULL),
  35      level(0),
  36      layer(0),
  37      width(0),
  38      height(0),
  39      x_offset(0),
  40      y_offset(0)
  41 {
  42 }
  43
  44 brw_blorp_surface_info::brw_blorp_surface_info()
  45    : map_stencil_as_y_tiled(false),
  46      num_samples(0),
  47      swizzle(SWIZZLE_XYZW)
  48 {
  49 }
  50
  51 void
  52 brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
  53                         unsigned int level, unsigned int layer)
  54 {
  55    /* Layer is a physical layer, so if this is a 2D multisample array texture
  56     * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it had better
  57     * be a multiple of num_samples.
  58     */
  59    if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
  60        mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
  61       assert(layer % mt->num_samples == 0);
  62    }
  63
  64    intel_miptree_check_level_layer(mt, level, layer);
  65
  66    this->mt = mt;
  67    this->level = level;
  68    this->layer = layer;
  69    this->width = minify(mt->physical_width0, level - mt->first_level);
  70    this->height = minify(mt->physical_height0, level - mt->first_level);
  71
  72    intel_miptree_get_image_offset(mt, level, layer, &x_offset, &y_offset);
  73 }
  74
  75 void
  76 brw_blorp_surface_info::set(struct brw_context *brw,
  77                             struct intel_mipmap_tree *mt,
  78                             unsigned int level, unsigned int layer,
  79                             mesa_format format, bool is_render_target)
  80 {
  81    brw_blorp_mip_info::set(mt, level, layer);
  82    this->num_samples = mt->num_samples;
  83    this->array_layout = mt->array_layout;
  84    this->map_stencil_as_y_tiled = false;
  85    this->msaa_layout = mt->msaa_layout;
  86
  87    if (format == MESA_FORMAT_NONE)
  88       format = mt->format;
  89
  90    switch (format) {
  91    case MESA_FORMAT_S_UINT8:
  92       /* The miptree is a W-tiled stencil buffer.  Surface states can't be set
  93        * up for W tiling, so we'll need to use Y tiling and have the WM
  94        * program swizzle the coordinates.
  95        */
  96       this->map_stencil_as_y_tiled = true;
  97       this->brw_surfaceformat = brw->gen >= 8 ? BRW_SURFACEFORMAT_R8_UINT :
  98                                                 BRW_SURFACEFORMAT_R8_UNORM;
  99       break;
 100    case MESA_FORMAT_Z24_UNORM_X8_UINT:
 101       /* It would make sense to use BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
 102        * here, but unfortunately it isn't supported as a render target, which
 103        * would prevent us from blitting to 24-bit depth.
 104        *
 105        * The miptree consists of 32 bits per pixel, arranged as 24-bit depth
 106        * values interleaved with 8 "don't care" bits.  Since depth values don't
 107        * require any blending, it doesn't matter how we interpret the bit
 108        * pattern as long as we copy the right amount of data, so just map it
 109        * as 8-bit BGRA.
 110        */
 111       this->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 112       break;
 113    case MESA_FORMAT_Z_FLOAT32:
 114       this->brw_surfaceformat = BRW_SURFACEFORMAT_R32_FLOAT;
 115       break;
 116    case MESA_FORMAT_Z_UNORM16:
 117       this->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
 118       break;
 119    default: {
 120       if (is_render_target) {
 121          assert(brw->format_supported_as_render_target[format]);
 122          this->brw_surfaceformat = brw->render_target_format[format];
 123       } else {
 124          this->brw_surfaceformat = brw_format_for_mesa_format(format);
 125       }
 126       break;
 127    }
 128    }
 129 }
 130
 131
 132 /**
 133  * Split x_offset and y_offset into a base offset (in bytes) and a remaining
 134  * x/y offset (in pixels).  Note: we can't do this by calling
 135  * intel_renderbuffer_tile_offsets(), because the offsets may have been
 136  * adjusted to account for Y vs. W tiling differences.  So we compute it
 137  * directly from the adjusted offsets.
 138  */
 139 uint32_t
 140 brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
 141                                              uint32_t *tile_y) const
 142 {
 143    uint32_t mask_x, mask_y;
 144
 145    intel_get_tile_masks(mt->tiling, mt->tr_mode, mt->cpp,
 146                         map_stencil_as_y_tiled,
 147                         &mask_x, &mask_y);
 148
 149    *tile_x = x_offset & mask_x;
 150    *tile_y = y_offset & mask_y;
 151
 152    return intel_miptree_get_aligned_offset(mt, x_offset & ~mask_x,
 153                                            y_offset & ~mask_y,
 154                                            map_stencil_as_y_tiled);
 155 }
 156
 157
 158 brw_blorp_params::brw_blorp_params(unsigned num_varyings,
 159                                    unsigned num_draw_buffers,
 160                                    unsigned num_layers)
 161    : x0(0),
 162      y0(0),
 163      x1(0),
 164      y1(0),
 165      depth_format(0),
 166      hiz_op(GEN6_HIZ_OP_NONE),
 167      fast_clear_op(0),
 168      use_wm_prog(false),
 169      num_varyings(num_varyings),
 170      num_draw_buffers(num_draw_buffers),
 171      num_layers(num_layers)
 172 {
 173    color_write_disable[0] = false;
 174    color_write_disable[1] = false;
 175    color_write_disable[2] = false;
 176    color_write_disable[3] = false;
 177 }
 178
 179 extern "C" {
 180 void
 181 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 182                unsigned int level, unsigned int layer, gen6_hiz_op op)
 183 {
 184    const char *opname = NULL;
 185
 186    switch (op) {
 187    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 188       opname = "depth resolve";
 189       break;
 190    case GEN6_HIZ_OP_HIZ_RESOLVE:
 191       opname = "hiz ambiguate";
 192       break;
 193    case GEN6_HIZ_OP_DEPTH_CLEAR:
 194       opname = "depth clear";
 195       break;
 196    case GEN6_HIZ_OP_NONE:
 197       opname = "noop?";
 198       break;
 199    }
 200
 201    DBG("%s %s to mt %p level %d layer %d\n",
 202        __func__, opname, mt, level, layer);
 203
 204    if (brw->gen >= 8) {
 205       gen8_hiz_exec(brw, mt, level, layer, op);
 206    } else {
 207       brw_hiz_op_params params(mt, level, layer, op);
 208       brw_blorp_exec(brw, &params);
 209    }
 210 }
 211
 212 } /* extern "C" */
 213
 214 void
 215 brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params)
 216 {
 217    struct gl_context *ctx = &brw->ctx;
 218    const uint32_t estimated_max_batch_usage = brw->gen >= 8 ? 1800 : 1500;
 219    bool check_aperture_failed_once = false;
 220
 221    /* Flush the sampler and render caches.  We definitely need to flush the
 222     * sampler cache so that we get updated contents from the render cache for
 223     * the glBlitFramebuffer() source.  Also, we are sometimes warned in the
 224     * docs to flush the cache between reinterpretations of the same surface
 225     * data with different formats, which blorp does for stencil and depth
 226     * data.
 227     */
 228    brw_emit_mi_flush(brw);
 229
 230 retry:
 231    intel_batchbuffer_require_space(brw, estimated_max_batch_usage, RENDER_RING);
 232    intel_batchbuffer_save_state(brw);
 233    drm_intel_bo *saved_bo = brw->batch.bo;
 234    uint32_t saved_used = USED_BATCH(brw->batch);
 235    uint32_t saved_state_batch_offset = brw->batch.state_batch_offset;
 236
 237    switch (brw->gen) {
 238    case 6:
 239       gen6_blorp_exec(brw, params);
 240       break;
 241    case 7:
 242       gen7_blorp_exec(brw, params);
 243       break;
 244    case 8:
 245    case 9:
 246       gen8_blorp_exec(brw, params);
 247       break;
 248    default:
 249       /* BLORP is not supported before Gen6. */
 250       unreachable("not reached");
 251    }
 252
 253    /* Make sure we didn't wrap the batch unintentionally, and make sure we
 254     * reserved enough space that a wrap will never happen.
 255     */
 256    assert(brw->batch.bo == saved_bo);
 257    assert((USED_BATCH(brw->batch) - saved_used) * 4 +
 258           (saved_state_batch_offset - brw->batch.state_batch_offset) <
 259           estimated_max_batch_usage);
 260    /* Shut up compiler warnings on release build */
 261    (void)saved_bo;
 262    (void)saved_used;
 263    (void)saved_state_batch_offset;
 264
 265    /* Check if the blorp op we just did would make our batch likely to fail to
 266     * map all the BOs into the GPU at batch exec time later.  If so, flush the
 267     * batch and try again with nothing else in the batch.
 268     */
 269    if (dri_bufmgr_check_aperture_space(&brw->batch.bo, 1)) {
 270       if (!check_aperture_failed_once) {
 271          check_aperture_failed_once = true;
 272          intel_batchbuffer_reset_to_saved(brw);
 273          intel_batchbuffer_flush(brw);
 274          goto retry;
 275       } else {
 276          int ret = intel_batchbuffer_flush(brw);
 277          WARN_ONCE(ret == -ENOSPC,
 278                    "i965: blorp emit exceeded available aperture space\n");
 279       }
 280    }
 281
 282    if (unlikely(brw->always_flush_batch))
 283       intel_batchbuffer_flush(brw);
 284
 285    /* We've smashed all state compared to what the normal 3D pipeline
 286     * rendering tracks for GL.
 287     */
 288    brw->ctx.NewDriverState = ~0ull;
 289    brw->no_depth_or_stencil = false;
 290    brw->ib.type = -1;
 291
 292    /* Flush the sampler cache so any texturing from the destination is
 293     * coherent.
 294     */
 295    brw_emit_mi_flush(brw);
 296 }
 297
 298 brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
 299                                      unsigned int level,
 300                                      unsigned int layer,
 301                                      gen6_hiz_op op)
 302 {
 303    this->hiz_op = op;
 304
 305    depth.set(mt, level, layer);
 306
 307    /* Align the rectangle primitive to 8x4 pixels.
 308     *
 309     * During fast depth clears, the emitted rectangle primitive  must be
 310     * aligned to 8x4 pixels.  From the Ivybridge PRM, Vol 2 Part 1 Section
 311     * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
 312     * PRM):
 313     *     If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
 314     *     aligned to an 8x4 pixel block relative to the upper left corner
 315     *     of the depth buffer [...]
 316     *
 317     * For hiz resolves, the rectangle must also be 8x4 aligned. Item
 318     * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
 319     * Ivybridge simulator require the alignment.
 320     *
 321     * To be safe, let's just align the rect for all hiz operations and all
 322     * hardware generations.
 323     *
 324     * However, for some miptree slices of a Z24 texture, emitting an 8x4
 325     * aligned rectangle that covers the slice may clobber adjacent slices if
 326     * we strictly adhered to the texture alignments specified in the PRM.  The
 327     * Ivybridge PRM, Section "Alignment Unit Size", states that
 328     * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
 329     * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
 330     * prevents the clobbering.
 331     */
 332    dst.num_samples = mt->num_samples;
 333    if (dst.num_samples > 1) {
 334       depth.width = ALIGN(mt->logical_width0, 8);
 335       depth.height = ALIGN(mt->logical_height0, 4);
 336    } else {
 337       depth.width = ALIGN(depth.width, 8);
 338       depth.height = ALIGN(depth.height, 4);
 339    }
 340
 341    x1 = depth.width;
 342    y1 = depth.height;
 343
 344    assert(intel_miptree_level_has_hiz(mt, level));
 345
 346    switch (mt->format) {
 347    case MESA_FORMAT_Z_UNORM16:       depth_format = BRW_DEPTHFORMAT_D16_UNORM; break;
 348    case MESA_FORMAT_Z_FLOAT32: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break;
 349    case MESA_FORMAT_Z24_UNORM_X8_UINT:    depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break;
 350    default:                    unreachable("not reached");
 351    }
 352 }
 353
 354 uint32_t
 355 brw_hiz_op_params::get_wm_prog(struct brw_context *brw,
 356                                brw_blorp_prog_data **prog_data) const
 357 {
 358    return 0;
 359 }