src/mesa/drivers/dri/i965/brw_blorp.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_batchbuffer.h"
  25 #include "intel_fbo.h"
  26
  27 #include "brw_blorp.h"
  28 #include "brw_defines.h"
  29 #include "brw_state.h"
  30 #include "gen6_blorp.h"
  31 #include "gen7_blorp.h"
  32
  33 #define FILE_DEBUG_FLAG DEBUG_BLORP
  34
  35 brw_blorp_mip_info::brw_blorp_mip_info()
  36    : mt(NULL),
  37      level(0),
  38      layer(0),
  39      width(0),
  40      height(0),
  41      x_offset(0),
  42      y_offset(0)
  43 {
  44 }
  45
  46 brw_blorp_surface_info::brw_blorp_surface_info()
  47    : map_stencil_as_y_tiled(false),
  48      num_samples(0)
  49 {
  50 }
  51
  52 void
  53 brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
  54                         unsigned int level, unsigned int layer)
  55 {
  56    intel_miptree_check_level_layer(mt, level, layer);
  57
  58    this->mt = mt;
  59    this->level = level;
  60    this->layer = layer;
  61    this->width = mt->level[level].width;
  62    this->height = mt->level[level].height;
  63
  64    intel_miptree_get_image_offset(mt, level, layer, &x_offset, &y_offset);
  65 }
  66
  67 void
  68 brw_blorp_surface_info::set(struct brw_context *brw,
  69                             struct intel_mipmap_tree *mt,
  70                             unsigned int level, unsigned int layer,
  71                             bool is_render_target)
  72 {
  73    brw_blorp_mip_info::set(mt, level, layer);
  74    this->num_samples = mt->num_samples;
  75    this->array_spacing_lod0 = mt->array_spacing_lod0;
  76    this->map_stencil_as_y_tiled = false;
  77    this->msaa_layout = mt->msaa_layout;
  78
  79    switch (mt->format) {
  80    case MESA_FORMAT_S8:
  81       /* The miptree is a W-tiled stencil buffer.  Surface states can't be set
  82        * up for W tiling, so we'll need to use Y tiling and have the WM
  83        * program swizzle the coordinates.
  84        */
  85       this->map_stencil_as_y_tiled = true;
  86       this->brw_surfaceformat = BRW_SURFACEFORMAT_R8_UNORM;
  87       break;
  88    case MESA_FORMAT_X8_Z24:
  89       /* It would make sense to use BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
  90        * here, but unfortunately it isn't supported as a render target, which
  91        * would prevent us from blitting to 24-bit depth.
  92        *
  93        * The miptree consists of 32 bits per pixel, arranged as 24-bit depth
  94        * values interleaved with 8 "don't care" bits.  Since depth values don't
  95        * require any blending, it doesn't matter how we interpret the bit
  96        * pattern as long as we copy the right amount of data, so just map it
  97        * as 8-bit BGRA.
  98        */
  99       this->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 100       break;
 101    case MESA_FORMAT_Z32_FLOAT:
 102       this->brw_surfaceformat = BRW_SURFACEFORMAT_R32_FLOAT;
 103       break;
 104    case MESA_FORMAT_Z16:
 105       this->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
 106       break;
 107    default: {
 108       gl_format linear_format = _mesa_get_srgb_format_linear(mt->format);
 109       if (is_render_target) {
 110          assert(brw->format_supported_as_render_target[linear_format]);
 111          this->brw_surfaceformat = brw->render_target_format[linear_format];
 112       } else {
 113          this->brw_surfaceformat = brw_format_for_mesa_format(linear_format);
 114       }
 115       break;
 116    }
 117    }
 118 }
 119
 120
 121 /**
 122  * Split x_offset and y_offset into a base offset (in bytes) and a remaining
 123  * x/y offset (in pixels).  Note: we can't do this by calling
 124  * intel_renderbuffer_tile_offsets(), because the offsets may have been
 125  * adjusted to account for Y vs. W tiling differences.  So we compute it
 126  * directly from the adjusted offsets.
 127  */
 128 uint32_t
 129 brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
 130                                              uint32_t *tile_y) const
 131 {
 132    struct intel_region *region = mt->region;
 133    uint32_t mask_x, mask_y;
 134
 135    intel_region_get_tile_masks(region, &mask_x, &mask_y,
 136                                map_stencil_as_y_tiled);
 137
 138    *tile_x = x_offset & mask_x;
 139    *tile_y = y_offset & mask_y;
 140
 141    return intel_region_get_aligned_offset(region, x_offset & ~mask_x,
 142                                           y_offset & ~mask_y,
 143                                           map_stencil_as_y_tiled);
 144 }
 145
 146
 147 brw_blorp_params::brw_blorp_params()
 148    : x0(0),
 149      y0(0),
 150      x1(0),
 151      y1(0),
 152      depth_format(0),
 153      hiz_op(GEN6_HIZ_OP_NONE),
 154      fast_clear_op(GEN7_FAST_CLEAR_OP_NONE),
 155      num_samples(0),
 156      use_wm_prog(false)
 157 {
 158    color_write_disable[0] = false;
 159    color_write_disable[1] = false;
 160    color_write_disable[2] = false;
 161    color_write_disable[3] = false;
 162 }
 163
 164 extern "C" {
 165 void
 166 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 167                unsigned int level, unsigned int layer, gen6_hiz_op op)
 168 {
 169    const char *opname = NULL;
 170
 171    switch (op) {
 172    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 173       opname = "depth resolve";
 174       break;
 175    case GEN6_HIZ_OP_HIZ_RESOLVE:
 176       opname = "hiz ambiguate";
 177       break;
 178    case GEN6_HIZ_OP_DEPTH_CLEAR:
 179       opname = "depth clear";
 180       break;
 181    case GEN6_HIZ_OP_NONE:
 182       opname = "noop?";
 183       break;
 184    }
 185
 186    DBG("%s %s to mt %p level %d layer %d\n",
 187        __FUNCTION__, opname, mt, level, layer);
 188
 189    brw_hiz_op_params params(mt, level, layer, op);
 190    brw_blorp_exec(brw, &params);
 191 }
 192
 193 } /* extern "C" */
 194
 195 void
 196 brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params)
 197 {
 198    switch (brw->gen) {
 199    case 6:
 200       gen6_blorp_exec(brw, params);
 201       break;
 202    case 7:
 203       gen7_blorp_exec(brw, params);
 204       break;
 205    default:
 206       /* BLORP is not supported before Gen6. */
 207       assert(false);
 208       break;
 209    }
 210
 211    if (unlikely(brw->always_flush_batch))
 212       intel_batchbuffer_flush(brw);
 213
 214    /* We've smashed all state compared to what the normal 3D pipeline
 215     * rendering tracks for GL.
 216     */
 217    brw->state.dirty.brw = ~0;
 218    brw->state.dirty.cache = ~0;
 219    brw->state_batch_count = 0;
 220    brw->batch.need_workaround_flush = true;
 221    brw->ib.type = -1;
 222    intel_batchbuffer_clear_cache(brw);
 223
 224    /* Flush the sampler cache so any texturing from the destination is
 225     * coherent.
 226     */
 227    intel_batchbuffer_emit_mi_flush(brw);
 228 }
 229
 230 brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
 231                                      unsigned int level,
 232                                      unsigned int layer,
 233                                      gen6_hiz_op op)
 234 {
 235    this->hiz_op = op;
 236
 237    depth.set(mt, level, layer);
 238
 239    /* Align the rectangle primitive to 8x4 pixels.
 240     *
 241     * During fast depth clears, the emitted rectangle primitive  must be
 242     * aligned to 8x4 pixels.  From the Ivybridge PRM, Vol 2 Part 1 Section
 243     * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
 244     * PRM):
 245     *     If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
 246     *     aligned to an 8x4 pixel block relative to the upper left corner
 247     *     of the depth buffer [...]
 248     *
 249     * For hiz resolves, the rectangle must also be 8x4 aligned. Item
 250     * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
 251     * Ivybridge simulator require the alignment.
 252     *
 253     * To be safe, let's just align the rect for all hiz operations and all
 254     * hardware generations.
 255     *
 256     * However, for some miptree slices of a Z24 texture, emitting an 8x4
 257     * aligned rectangle that covers the slice may clobber adjacent slices if
 258     * we strictly adhered to the texture alignments specified in the PRM.  The
 259     * Ivybridge PRM, Section "Alignment Unit Size", states that
 260     * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
 261     * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
 262     * prevents the clobbering.
 263     */
 264    depth.width = ALIGN(depth.width, 8);
 265    depth.height = ALIGN(depth.height, 4);
 266
 267    x1 = depth.width;
 268    y1 = depth.height;
 269
 270    assert(intel_miptree_slice_has_hiz(mt, level, layer));
 271
 272    switch (mt->format) {
 273    case MESA_FORMAT_Z16:       depth_format = BRW_DEPTHFORMAT_D16_UNORM; break;
 274    case MESA_FORMAT_Z32_FLOAT: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break;
 275    case MESA_FORMAT_X8_Z24:    depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break;
 276    default:                    assert(0); break;
 277    }
 278 }
 279
 280 uint32_t
 281 brw_hiz_op_params::get_wm_prog(struct brw_context *brw,
 282                                brw_blorp_prog_data **prog_data) const
 283 {
 284    return 0;
 285 }