src/mesa/drivers/dri/i965/brw_blorp.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_fbo.h"
  25
  26 #include "brw_blorp.h"
  27 #include "brw_defines.h"
  28 #include "gen6_blorp.h"
  29 #include "gen7_blorp.h"
  30
  31 brw_blorp_mip_info::brw_blorp_mip_info()
  32    : mt(NULL),
  33      level(0),
  34      layer(0),
  35      width(0),
  36      height(0),
  37      x_offset(0),
  38      y_offset(0)
  39 {
  40 }
  41
  42 brw_blorp_surface_info::brw_blorp_surface_info()
  43    : map_stencil_as_y_tiled(false),
  44      num_samples(0)
  45 {
  46 }
  47
  48 void
  49 brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
  50                         unsigned int level, unsigned int layer)
  51 {
  52    intel_miptree_check_level_layer(mt, level, layer);
  53
  54    this->mt = mt;
  55    this->level = level;
  56    this->layer = layer;
  57    this->width = mt->level[level].width;
  58    this->height = mt->level[level].height;
  59
  60    intel_miptree_get_image_offset(mt, level, layer, &x_offset, &y_offset);
  61 }
  62
  63 void
  64 brw_blorp_surface_info::set(struct brw_context *brw,
  65                             struct intel_mipmap_tree *mt,
  66                             unsigned int level, unsigned int layer)
  67 {
  68    brw_blorp_mip_info::set(mt, level, layer);
  69    this->num_samples = mt->num_samples;
  70    this->array_spacing_lod0 = mt->array_spacing_lod0;
  71    this->map_stencil_as_y_tiled = false;
  72    this->msaa_layout = mt->msaa_layout;
  73
  74    switch (mt->format) {
  75    case MESA_FORMAT_S8:
  76       /* The miptree is a W-tiled stencil buffer.  Surface states can't be set
  77        * up for W tiling, so we'll need to use Y tiling and have the WM
  78        * program swizzle the coordinates.
  79        */
  80       this->map_stencil_as_y_tiled = true;
  81       this->brw_surfaceformat = BRW_SURFACEFORMAT_R8_UNORM;
  82       break;
  83    case MESA_FORMAT_X8_Z24:
  84    case MESA_FORMAT_Z32_FLOAT:
  85       /* The miptree consists of 32 bits per pixel, arranged either as 24-bit
  86        * depth values interleaved with 8 "don't care" bits, or as 32-bit
  87        * floating point depth values.  Since depth values don't require any
  88        * blending, it doesn't matter how we interpret the bit pattern as long
  89        * as we copy the right amount of data, so just map it as 8-bit BGRA.
  90        */
  91       this->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
  92       break;
  93    case MESA_FORMAT_Z16:
  94       /* The miptree consists of 16 bits per pixel of depth data.  Since depth
  95        * values don't require any blending, it doesn't matter how we interpret
  96        * the bit pattern as long as we copy the right amount of data, so just
  97        * map is as 8-bit RG.
  98        */
  99       this->brw_surfaceformat = BRW_SURFACEFORMAT_R8G8_UNORM;
 100       break;
 101    default:
 102       /* Blorp blits don't support any sort of format conversion (except
 103        * between sRGB and linear), so we can safely assume that the format is
 104        * supported as a render target, even if this is the source image.  So
 105        * we can convert to a surface format using brw->render_target_format.
 106        */
 107       assert(brw->format_supported_as_render_target[mt->format]);
 108       this->brw_surfaceformat = brw->render_target_format[mt->format];
 109       break;
 110    }
 111 }
 112
 113
 114 /**
 115  * Split x_offset and y_offset into a base offset (in bytes) and a remaining
 116  * x/y offset (in pixels).  Note: we can't do this by calling
 117  * intel_renderbuffer_tile_offsets(), because the offsets may have been
 118  * adjusted to account for Y vs. W tiling differences.  So we compute it
 119  * directly from the adjusted offsets.
 120  */
 121 uint32_t
 122 brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
 123                                              uint32_t *tile_y) const
 124 {
 125    struct intel_region *region = mt->region;
 126    uint32_t mask_x, mask_y;
 127
 128    intel_region_get_tile_masks(region, &mask_x, &mask_y,
 129                                map_stencil_as_y_tiled);
 130
 131    *tile_x = x_offset & mask_x;
 132    *tile_y = y_offset & mask_y;
 133
 134    return intel_region_get_aligned_offset(region, x_offset & ~mask_x,
 135                                           y_offset & ~mask_y,
 136                                           map_stencil_as_y_tiled);
 137 }
 138
 139
 140 brw_blorp_params::brw_blorp_params()
 141    : x0(0),
 142      y0(0),
 143      x1(0),
 144      y1(0),
 145      depth_format(0),
 146      hiz_op(GEN6_HIZ_OP_NONE),
 147      num_samples(0),
 148      use_wm_prog(false)
 149 {
 150 }
 151
 152 extern "C" {
 153 void
 154 intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt,
 155                unsigned int level, unsigned int layer, gen6_hiz_op op)
 156 {
 157    brw_hiz_op_params params(mt, level, layer, op);
 158    brw_blorp_exec(intel, &params);
 159 }
 160
 161 } /* extern "C" */
 162
 163 void
 164 brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params)
 165 {
 166    switch (intel->gen) {
 167    case 6:
 168       gen6_blorp_exec(intel, params);
 169       break;
 170    case 7:
 171       gen7_blorp_exec(intel, params);
 172       break;
 173    default:
 174       /* BLORP is not supported before Gen6. */
 175       assert(false);
 176       break;
 177    }
 178 }
 179
 180 brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
 181                                      unsigned int level,
 182                                      unsigned int layer,
 183                                      gen6_hiz_op op)
 184 {
 185    this->hiz_op = op;
 186
 187    depth.set(mt, level, layer);
 188
 189    /* Align the rectangle primitive to 8x4 pixels.
 190     *
 191     * During fast depth clears, the emitted rectangle primitive  must be
 192     * aligned to 8x4 pixels.  From the Ivybridge PRM, Vol 2 Part 1 Section
 193     * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
 194     * PRM):
 195     *     If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
 196     *     aligned to an 8x4 pixel block relative to the upper left corner
 197     *     of the depth buffer [...]
 198     *
 199     * For hiz resolves, the rectangle must also be 8x4 aligned. Item
 200     * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
 201     * Ivybridge simulator require the alignment.
 202     *
 203     * To be safe, let's just align the rect for all hiz operations and all
 204     * hardware generations.
 205     *
 206     * However, for some miptree slices of a Z24 texture, emitting an 8x4
 207     * aligned rectangle that covers the slice may clobber adjacent slices if
 208     * we strictly adhered to the texture alignments specified in the PRM.  The
 209     * Ivybridge PRM, Section "Alignment Unit Size", states that
 210     * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
 211     * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
 212     * prevents the clobbering.
 213     */
 214    depth.width = ALIGN(depth.width, 8);
 215    depth.height = ALIGN(depth.height, 4);
 216
 217    x1 = depth.width;
 218    y1 = depth.height;
 219
 220    assert(mt->hiz_mt != NULL);
 221
 222    switch (mt->format) {
 223    case MESA_FORMAT_Z16:       depth_format = BRW_DEPTHFORMAT_D16_UNORM; break;
 224    case MESA_FORMAT_Z32_FLOAT: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break;
 225    case MESA_FORMAT_X8_Z24:    depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break;
 226    default:                    assert(0); break;
 227    }
 228 }
 229
 230 uint32_t
 231 brw_hiz_op_params::get_wm_prog(struct brw_context *brw,
 232                                brw_blorp_prog_data **prog_data) const
 233 {
 234    return 0;
 235 }