src/mesa/drivers/dri/i965/brw_blorp.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_batchbuffer.h"
  25 #include "intel_fbo.h"
  26
  27 #include "brw_blorp.h"
  28 #include "brw_defines.h"
  29 #include "gen6_blorp.h"
  30 #include "gen7_blorp.h"
  31
  32 brw_blorp_mip_info::brw_blorp_mip_info()
  33    : mt(NULL),
  34      level(0),
  35      layer(0),
  36      width(0),
  37      height(0),
  38      x_offset(0),
  39      y_offset(0)
  40 {
  41 }
  42
  43 brw_blorp_surface_info::brw_blorp_surface_info()
  44    : map_stencil_as_y_tiled(false),
  45      num_samples(0)
  46 {
  47 }
  48
  49 void
  50 brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
  51                         unsigned int level, unsigned int layer)
  52 {
  53    intel_miptree_check_level_layer(mt, level, layer);
  54
  55    this->mt = mt;
  56    this->level = level;
  57    this->layer = layer;
  58    this->width = mt->level[level].width;
  59    this->height = mt->level[level].height;
  60
  61    intel_miptree_get_image_offset(mt, level, layer, &x_offset, &y_offset);
  62 }
  63
  64 void
  65 brw_blorp_surface_info::set(struct brw_context *brw,
  66                             struct intel_mipmap_tree *mt,
  67                             unsigned int level, unsigned int layer)
  68 {
  69    brw_blorp_mip_info::set(mt, level, layer);
  70    this->num_samples = mt->num_samples;
  71    this->array_spacing_lod0 = mt->array_spacing_lod0;
  72    this->map_stencil_as_y_tiled = false;
  73    this->msaa_layout = mt->msaa_layout;
  74
  75    switch (mt->format) {
  76    case MESA_FORMAT_S8:
  77       /* The miptree is a W-tiled stencil buffer.  Surface states can't be set
  78        * up for W tiling, so we'll need to use Y tiling and have the WM
  79        * program swizzle the coordinates.
  80        */
  81       this->map_stencil_as_y_tiled = true;
  82       this->brw_surfaceformat = BRW_SURFACEFORMAT_R8_UNORM;
  83       break;
  84    case MESA_FORMAT_X8_Z24:
  85    case MESA_FORMAT_Z32_FLOAT:
  86       /* The miptree consists of 32 bits per pixel, arranged either as 24-bit
  87        * depth values interleaved with 8 "don't care" bits, or as 32-bit
  88        * floating point depth values.  Since depth values don't require any
  89        * blending, it doesn't matter how we interpret the bit pattern as long
  90        * as we copy the right amount of data, so just map it as 8-bit BGRA.
  91        */
  92       this->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
  93       break;
  94    case MESA_FORMAT_Z16:
  95       /* The miptree consists of 16 bits per pixel of depth data.  Since depth
  96        * values don't require any blending, it doesn't matter how we interpret
  97        * the bit pattern as long as we copy the right amount of data, so just
  98        * map is as 8-bit RG.
  99        */
 100       this->brw_surfaceformat = BRW_SURFACEFORMAT_R8G8_UNORM;
 101       break;
 102    default:
 103       /* Blorp blits don't support any sort of format conversion (except
 104        * between sRGB and linear), so we can safely assume that the format is
 105        * supported as a render target, even if this is the source image.  So
 106        * we can convert to a surface format using brw->render_target_format.
 107        */
 108       assert(brw->format_supported_as_render_target[mt->format]);
 109       this->brw_surfaceformat = brw->render_target_format[mt->format];
 110       break;
 111    }
 112 }
 113
 114
 115 /**
 116  * Split x_offset and y_offset into a base offset (in bytes) and a remaining
 117  * x/y offset (in pixels).  Note: we can't do this by calling
 118  * intel_renderbuffer_tile_offsets(), because the offsets may have been
 119  * adjusted to account for Y vs. W tiling differences.  So we compute it
 120  * directly from the adjusted offsets.
 121  */
 122 uint32_t
 123 brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
 124                                              uint32_t *tile_y) const
 125 {
 126    struct intel_region *region = mt->region;
 127    uint32_t mask_x, mask_y;
 128
 129    intel_region_get_tile_masks(region, &mask_x, &mask_y,
 130                                map_stencil_as_y_tiled);
 131
 132    *tile_x = x_offset & mask_x;
 133    *tile_y = y_offset & mask_y;
 134
 135    return intel_region_get_aligned_offset(region, x_offset & ~mask_x,
 136                                           y_offset & ~mask_y,
 137                                           map_stencil_as_y_tiled);
 138 }
 139
 140
 141 brw_blorp_params::brw_blorp_params()
 142    : x0(0),
 143      y0(0),
 144      x1(0),
 145      y1(0),
 146      depth_format(0),
 147      hiz_op(GEN6_HIZ_OP_NONE),
 148      num_samples(0),
 149      use_wm_prog(false)
 150 {
 151    color_write_disable[0] = false;
 152    color_write_disable[1] = false;
 153    color_write_disable[2] = false;
 154    color_write_disable[3] = false;
 155 }
 156
 157 extern "C" {
 158 void
 159 intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt,
 160                unsigned int level, unsigned int layer, gen6_hiz_op op)
 161 {
 162    brw_hiz_op_params params(mt, level, layer, op);
 163    brw_blorp_exec(intel, &params);
 164 }
 165
 166 } /* extern "C" */
 167
 168 void
 169 brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params)
 170 {
 171    struct brw_context *brw = brw_context(&intel->ctx);
 172
 173    switch (intel->gen) {
 174    case 6:
 175       gen6_blorp_exec(intel, params);
 176       break;
 177    case 7:
 178       gen7_blorp_exec(intel, params);
 179       break;
 180    default:
 181       /* BLORP is not supported before Gen6. */
 182       assert(false);
 183       break;
 184    }
 185
 186    if (unlikely(intel->always_flush_batch))
 187       intel_batchbuffer_flush(intel);
 188
 189    /* We've smashed all state compared to what the normal 3D pipeline
 190     * rendering tracks for GL.
 191     */
 192    brw->state.dirty.brw = ~0;
 193    brw->state.dirty.cache = ~0;
 194    brw->state_batch_count = 0;
 195    intel->batch.need_workaround_flush = true;
 196
 197    /* Flush the sampler cache so any texturing from the destination is
 198     * coherent.
 199     */
 200    intel_batchbuffer_emit_mi_flush(intel);
 201 }
 202
 203 brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
 204                                      unsigned int level,
 205                                      unsigned int layer,
 206                                      gen6_hiz_op op)
 207 {
 208    this->hiz_op = op;
 209
 210    depth.set(mt, level, layer);
 211
 212    /* Align the rectangle primitive to 8x4 pixels.
 213     *
 214     * During fast depth clears, the emitted rectangle primitive  must be
 215     * aligned to 8x4 pixels.  From the Ivybridge PRM, Vol 2 Part 1 Section
 216     * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
 217     * PRM):
 218     *     If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
 219     *     aligned to an 8x4 pixel block relative to the upper left corner
 220     *     of the depth buffer [...]
 221     *
 222     * For hiz resolves, the rectangle must also be 8x4 aligned. Item
 223     * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
 224     * Ivybridge simulator require the alignment.
 225     *
 226     * To be safe, let's just align the rect for all hiz operations and all
 227     * hardware generations.
 228     *
 229     * However, for some miptree slices of a Z24 texture, emitting an 8x4
 230     * aligned rectangle that covers the slice may clobber adjacent slices if
 231     * we strictly adhered to the texture alignments specified in the PRM.  The
 232     * Ivybridge PRM, Section "Alignment Unit Size", states that
 233     * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
 234     * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
 235     * prevents the clobbering.
 236     */
 237    depth.width = ALIGN(depth.width, 8);
 238    depth.height = ALIGN(depth.height, 4);
 239
 240    x1 = depth.width;
 241    y1 = depth.height;
 242
 243    assert(intel_miptree_slice_has_hiz(mt, level, layer));
 244
 245    switch (mt->format) {
 246    case MESA_FORMAT_Z16:       depth_format = BRW_DEPTHFORMAT_D16_UNORM; break;
 247    case MESA_FORMAT_Z32_FLOAT: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break;
 248    case MESA_FORMAT_X8_Z24:    depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break;
 249    default:                    assert(0); break;
 250    }
 251 }
 252
 253 uint32_t
 254 brw_hiz_op_params::get_wm_prog(struct brw_context *brw,
 255                                brw_blorp_prog_data **prog_data) const
 256 {
 257    return 0;
 258 }