2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_batchbuffer.h"
26 #include "intel_fbo.h"
28 #include "brw_blorp.h"
29 #include "brw_defines.h"
30 #include "brw_state.h"
31 #include "gen6_blorp.h"
32 #include "gen7_blorp.h"
34 #define FILE_DEBUG_FLAG DEBUG_BLORP
36 brw_blorp_mip_info::brw_blorp_mip_info()
47 brw_blorp_surface_info::brw_blorp_surface_info()
48 : map_stencil_as_y_tiled(false),
54 brw_blorp_mip_info::set(struct intel_mipmap_tree
*mt
,
55 unsigned int level
, unsigned int layer
)
57 /* Layer is a physical layer, so if this is a 2D multisample array texture
58 * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it had better
59 * be a multiple of num_samples.
61 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
62 mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
63 assert(layer
% mt
->num_samples
== 0);
66 intel_miptree_check_level_layer(mt
, level
, layer
);
71 this->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
72 this->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
74 intel_miptree_get_image_offset(mt
, level
, layer
, &x_offset
, &y_offset
);
78 brw_blorp_surface_info::set(struct brw_context
*brw
,
79 struct intel_mipmap_tree
*mt
,
80 unsigned int level
, unsigned int layer
,
81 mesa_format format
, bool is_render_target
)
83 brw_blorp_mip_info::set(mt
, level
, layer
);
84 this->num_samples
= mt
->num_samples
;
85 this->array_layout
= mt
->array_layout
;
86 this->map_stencil_as_y_tiled
= false;
87 this->msaa_layout
= mt
->msaa_layout
;
89 if (format
== MESA_FORMAT_NONE
)
93 case MESA_FORMAT_S_UINT8
:
94 /* The miptree is a W-tiled stencil buffer. Surface states can't be set
95 * up for W tiling, so we'll need to use Y tiling and have the WM
96 * program swizzle the coordinates.
98 this->map_stencil_as_y_tiled
= true;
99 this->brw_surfaceformat
= BRW_SURFACEFORMAT_R8_UNORM
;
101 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
102 /* It would make sense to use BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
103 * here, but unfortunately it isn't supported as a render target, which
104 * would prevent us from blitting to 24-bit depth.
106 * The miptree consists of 32 bits per pixel, arranged as 24-bit depth
107 * values interleaved with 8 "don't care" bits. Since depth values don't
108 * require any blending, it doesn't matter how we interpret the bit
109 * pattern as long as we copy the right amount of data, so just map it
112 this->brw_surfaceformat
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
114 case MESA_FORMAT_Z_FLOAT32
:
115 this->brw_surfaceformat
= BRW_SURFACEFORMAT_R32_FLOAT
;
117 case MESA_FORMAT_Z_UNORM16
:
118 this->brw_surfaceformat
= BRW_SURFACEFORMAT_R16_UNORM
;
121 mesa_format linear_format
= _mesa_get_srgb_format_linear(format
);
122 if (is_render_target
) {
123 assert(brw
->format_supported_as_render_target
[linear_format
]);
124 this->brw_surfaceformat
= brw
->render_target_format
[linear_format
];
126 this->brw_surfaceformat
= brw_format_for_mesa_format(linear_format
);
135 * Split x_offset and y_offset into a base offset (in bytes) and a remaining
136 * x/y offset (in pixels). Note: we can't do this by calling
137 * intel_renderbuffer_tile_offsets(), because the offsets may have been
138 * adjusted to account for Y vs. W tiling differences. So we compute it
139 * directly from the adjusted offsets.
142 brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x
,
143 uint32_t *tile_y
) const
145 uint32_t mask_x
, mask_y
;
147 intel_miptree_get_tile_masks(mt
, &mask_x
, &mask_y
, map_stencil_as_y_tiled
);
149 *tile_x
= x_offset
& mask_x
;
150 *tile_y
= y_offset
& mask_y
;
152 return intel_miptree_get_aligned_offset(mt
, x_offset
& ~mask_x
,
154 map_stencil_as_y_tiled
);
158 brw_blorp_params::brw_blorp_params(unsigned num_varyings
,
159 unsigned num_draw_buffers
,
166 hiz_op(GEN6_HIZ_OP_NONE
),
168 num_varyings(num_varyings
),
169 num_draw_buffers(num_draw_buffers
),
170 num_layers(num_layers
)
176 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
177 unsigned int level
, unsigned int layer
, gen6_hiz_op op
)
179 const char *opname
= NULL
;
182 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
183 opname
= "depth resolve";
185 case GEN6_HIZ_OP_HIZ_RESOLVE
:
186 opname
= "hiz ambiguate";
188 case GEN6_HIZ_OP_DEPTH_CLEAR
:
189 opname
= "depth clear";
191 case GEN6_HIZ_OP_NONE
:
196 DBG("%s %s to mt %p level %d layer %d\n",
197 __func__
, opname
, mt
, level
, layer
);
200 gen8_hiz_exec(brw
, mt
, level
, layer
, op
);
202 brw_hiz_op_params
params(mt
, level
, layer
, op
);
203 brw_blorp_exec(brw
, ¶ms
);
210 brw_blorp_exec(struct brw_context
*brw
, const brw_blorp_params
*params
)
212 struct gl_context
*ctx
= &brw
->ctx
;
213 uint32_t estimated_max_batch_usage
= 1500;
214 bool check_aperture_failed_once
= false;
216 /* Flush the sampler and render caches. We definitely need to flush the
217 * sampler cache so that we get updated contents from the render cache for
218 * the glBlitFramebuffer() source. Also, we are sometimes warned in the
219 * docs to flush the cache between reinterpretations of the same surface
220 * data with different formats, which blorp does for stencil and depth
223 brw_emit_mi_flush(brw
);
226 intel_batchbuffer_require_space(brw
, estimated_max_batch_usage
, RENDER_RING
);
227 intel_batchbuffer_save_state(brw
);
228 drm_intel_bo
*saved_bo
= brw
->batch
.bo
;
229 uint32_t saved_used
= USED_BATCH(brw
->batch
);
230 uint32_t saved_state_batch_offset
= brw
->batch
.state_batch_offset
;
234 gen6_blorp_exec(brw
, params
);
237 gen7_blorp_exec(brw
, params
);
240 /* BLORP is not supported before Gen6. */
241 unreachable("not reached");
244 /* Make sure we didn't wrap the batch unintentionally, and make sure we
245 * reserved enough space that a wrap will never happen.
247 assert(brw
->batch
.bo
== saved_bo
);
248 assert((USED_BATCH(brw
->batch
) - saved_used
) * 4 +
249 (saved_state_batch_offset
- brw
->batch
.state_batch_offset
) <
250 estimated_max_batch_usage
);
251 /* Shut up compiler warnings on release build */
254 (void)saved_state_batch_offset
;
256 /* Check if the blorp op we just did would make our batch likely to fail to
257 * map all the BOs into the GPU at batch exec time later. If so, flush the
258 * batch and try again with nothing else in the batch.
260 if (dri_bufmgr_check_aperture_space(&brw
->batch
.bo
, 1)) {
261 if (!check_aperture_failed_once
) {
262 check_aperture_failed_once
= true;
263 intel_batchbuffer_reset_to_saved(brw
);
264 intel_batchbuffer_flush(brw
);
267 int ret
= intel_batchbuffer_flush(brw
);
268 WARN_ONCE(ret
== -ENOSPC
,
269 "i965: blorp emit exceeded available aperture space\n");
273 if (unlikely(brw
->always_flush_batch
))
274 intel_batchbuffer_flush(brw
);
276 /* We've smashed all state compared to what the normal 3D pipeline
277 * rendering tracks for GL.
279 brw
->ctx
.NewDriverState
= ~0ull;
280 brw
->no_depth_or_stencil
= false;
283 /* Flush the sampler cache so any texturing from the destination is
286 brw_emit_mi_flush(brw
);
289 brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree
*mt
,
296 depth
.set(mt
, level
, layer
);
298 /* Align the rectangle primitive to 8x4 pixels.
300 * During fast depth clears, the emitted rectangle primitive must be
301 * aligned to 8x4 pixels. From the Ivybridge PRM, Vol 2 Part 1 Section
302 * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
304 * If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
305 * aligned to an 8x4 pixel block relative to the upper left corner
306 * of the depth buffer [...]
308 * For hiz resolves, the rectangle must also be 8x4 aligned. Item
309 * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
310 * Ivybridge simulator require the alignment.
312 * To be safe, let's just align the rect for all hiz operations and all
313 * hardware generations.
315 * However, for some miptree slices of a Z24 texture, emitting an 8x4
316 * aligned rectangle that covers the slice may clobber adjacent slices if
317 * we strictly adhered to the texture alignments specified in the PRM. The
318 * Ivybridge PRM, Section "Alignment Unit Size", states that
319 * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
320 * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
321 * prevents the clobbering.
323 depth
.width
= ALIGN(depth
.width
, 8);
324 depth
.height
= ALIGN(depth
.height
, 4);
329 assert(intel_miptree_level_has_hiz(mt
, level
));
331 switch (mt
->format
) {
332 case MESA_FORMAT_Z_UNORM16
: depth_format
= BRW_DEPTHFORMAT_D16_UNORM
; break;
333 case MESA_FORMAT_Z_FLOAT32
: depth_format
= BRW_DEPTHFORMAT_D32_FLOAT
; break;
334 case MESA_FORMAT_Z24_UNORM_X8_UINT
: depth_format
= BRW_DEPTHFORMAT_D24_UNORM_X8_UINT
; break;
335 default: unreachable("not reached");
340 brw_hiz_op_params::get_wm_prog(struct brw_context
*brw
,
341 brw_blorp_prog_data
**prog_data
) const