src/mesa/drivers/dri/i965/brw_blorp.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_fbo.h"
  25
  26 #include "brw_blorp.h"
  27 #include "brw_defines.h"
  28 #include "gen6_blorp.h"
  29 #include "gen7_blorp.h"
  30
  31 brw_blorp_mip_info::brw_blorp_mip_info()
  32    : mt(NULL),
  33      level(0),
  34      layer(0)
  35 {
  36 }
  37
  38 brw_blorp_surface_info::brw_blorp_surface_info()
  39    : map_stencil_as_y_tiled(false),
  40      num_samples(0)
  41 {
  42 }
  43
  44 void
  45 brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
  46                         unsigned int level, unsigned int layer)
  47 {
  48    intel_miptree_check_level_layer(mt, level, layer);
  49
  50    this->mt = mt;
  51    this->level = level;
  52    this->layer = layer;
  53 }
  54
  55 void
  56 brw_blorp_surface_info::set(struct intel_mipmap_tree *mt,
  57                             unsigned int level, unsigned int layer)
  58 {
  59    brw_blorp_mip_info::set(mt, level, layer);
  60    this->num_samples = mt->num_samples;
  61    this->array_spacing_lod0 = mt->array_spacing_lod0;
  62
  63    if (mt->format == MESA_FORMAT_S8) {
  64       /* The miptree is a W-tiled stencil buffer.  Surface states can't be set
  65        * up for W tiling, so we'll need to use Y tiling and have the WM
  66        * program swizzle the coordinates.
  67        */
  68       this->map_stencil_as_y_tiled = true;
  69       this->brw_surfaceformat = BRW_SURFACEFORMAT_R8_UNORM;
  70    } else {
  71       this->map_stencil_as_y_tiled = false;
  72       this->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
  73    }
  74 }
  75
  76 void
  77 brw_blorp_mip_info::get_draw_offsets(uint32_t *draw_x, uint32_t *draw_y) const
  78 {
  79    /* Construct a dummy renderbuffer just to extract tile offsets. */
  80    struct intel_renderbuffer rb;
  81    rb.mt = mt;
  82    rb.mt_level = level;
  83    rb.mt_layer = layer;
  84    intel_renderbuffer_set_draw_offset(&rb);
  85    *draw_x = rb.draw_x;
  86    *draw_y = rb.draw_y;
  87 }
  88
  89 brw_blorp_params::brw_blorp_params()
  90    : x0(0),
  91      y0(0),
  92      x1(0),
  93      y1(0),
  94      depth_format(0),
  95      hiz_op(GEN6_HIZ_OP_NONE),
  96      num_samples(0),
  97      use_wm_prog(false)
  98 {
  99 }
 100
 101 extern "C" {
 102 void
 103 intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt,
 104                unsigned int level, unsigned int layer, gen6_hiz_op op)
 105 {
 106    brw_hiz_op_params params(mt, level, layer, op);
 107    brw_blorp_exec(intel, &params);
 108 }
 109
 110 } /* extern "C" */
 111
 112 void
 113 brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params)
 114 {
 115    switch (intel->gen) {
 116    case 6:
 117       gen6_blorp_exec(intel, params);
 118       break;
 119    case 7:
 120       gen7_blorp_exec(intel, params);
 121       break;
 122    default:
 123       /* BLORP is not supported before Gen6. */
 124       assert(false);
 125       break;
 126    }
 127 }
 128
 129 brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
 130                                      unsigned int level,
 131                                      unsigned int layer,
 132                                      gen6_hiz_op op)
 133 {
 134    this->hiz_op = op;
 135
 136    depth.set(mt, level, layer);
 137    depth.get_miplevel_dims(&x1, &y1);
 138
 139    assert(mt->hiz_mt != NULL);
 140
 141    switch (mt->format) {
 142    case MESA_FORMAT_Z16:       depth_format = BRW_DEPTHFORMAT_D16_UNORM; break;
 143    case MESA_FORMAT_Z32_FLOAT: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break;
 144    case MESA_FORMAT_X8_Z24:    depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break;
 145    default:                    assert(0); break;
 146    }
 147 }
 148
 149 uint32_t
 150 brw_hiz_op_params::get_wm_prog(struct brw_context *brw,
 151                                brw_blorp_prog_data **prog_data) const
 152 {
 153    return 0;
 154 }