src/mesa/drivers/dri/i965/brw_blorp.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_fbo.h"
  25
  26 #include "brw_blorp.h"
  27 #include "brw_defines.h"
  28 #include "gen6_blorp.h"
  29 #include "gen7_blorp.h"
  30
  31 brw_blorp_mip_info::brw_blorp_mip_info()
  32    : mt(NULL),
  33      level(0),
  34      layer(0)
  35 {
  36 }
  37
  38 brw_blorp_surface_info::brw_blorp_surface_info()
  39    : map_stencil_as_y_tiled(false),
  40      num_samples(0)
  41 {
  42 }
  43
  44 void
  45 brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
  46                         unsigned int level, unsigned int layer)
  47 {
  48    intel_miptree_check_level_layer(mt, level, layer);
  49
  50    this->mt = mt;
  51    this->level = level;
  52    this->layer = layer;
  53 }
  54
  55 void
  56 brw_blorp_surface_info::set(struct intel_mipmap_tree *mt,
  57                             unsigned int level, unsigned int layer)
  58 {
  59    brw_blorp_mip_info::set(mt, level, layer);
  60    this->num_samples = mt->num_samples;
  61    this->array_spacing_lod0 = mt->array_spacing_lod0;
  62
  63    if (mt->format == MESA_FORMAT_S8) {
  64       /* The miptree is a W-tiled stencil buffer.  Surface states can't be set
  65        * up for W tiling, so we'll need to use Y tiling and have the WM
  66        * program swizzle the coordinates.
  67        */
  68       this->map_stencil_as_y_tiled = true;
  69    } else {
  70       this->map_stencil_as_y_tiled = false;
  71    }
  72 }
  73
  74 void
  75 brw_blorp_mip_info::get_draw_offsets(uint32_t *draw_x, uint32_t *draw_y) const
  76 {
  77    /* Construct a dummy renderbuffer just to extract tile offsets. */
  78    struct intel_renderbuffer rb;
  79    rb.mt = mt;
  80    rb.mt_level = level;
  81    rb.mt_layer = layer;
  82    intel_renderbuffer_set_draw_offset(&rb);
  83    *draw_x = rb.draw_x;
  84    *draw_y = rb.draw_y;
  85 }
  86
  87 brw_blorp_params::brw_blorp_params()
  88    : x0(0),
  89      y0(0),
  90      x1(0),
  91      y1(0),
  92      depth_format(0),
  93      hiz_op(GEN6_HIZ_OP_NONE),
  94      num_samples(0),
  95      use_wm_prog(false)
  96 {
  97 }
  98
  99 extern "C" {
 100 void
 101 intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt,
 102                unsigned int level, unsigned int layer, gen6_hiz_op op)
 103 {
 104    brw_hiz_op_params params(mt, level, layer, op);
 105    brw_blorp_exec(intel, &params);
 106 }
 107
 108 } /* extern "C" */
 109
 110 void
 111 brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params)
 112 {
 113    switch (intel->gen) {
 114    case 6:
 115       gen6_blorp_exec(intel, params);
 116       break;
 117    case 7:
 118       gen7_blorp_exec(intel, params);
 119       break;
 120    default:
 121       /* BLORP is not supported before Gen6. */
 122       assert(false);
 123       break;
 124    }
 125 }
 126
 127 brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
 128                                      unsigned int level,
 129                                      unsigned int layer,
 130                                      gen6_hiz_op op)
 131 {
 132    this->hiz_op = op;
 133
 134    depth.set(mt, level, layer);
 135    depth.get_miplevel_dims(&x1, &y1);
 136
 137    assert(mt->hiz_mt != NULL);
 138
 139    switch (mt->format) {
 140    case MESA_FORMAT_Z16:       depth_format = BRW_DEPTHFORMAT_D16_UNORM; break;
 141    case MESA_FORMAT_Z32_FLOAT: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break;
 142    case MESA_FORMAT_X8_Z24:    depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break;
 143    default:                    assert(0); break;
 144    }
 145 }
 146
 147 uint32_t
 148 brw_hiz_op_params::get_wm_prog(struct brw_context *brw,
 149                                brw_blorp_prog_data **prog_data) const
 150 {
 151    return 0;
 152 }