src/mesa/drivers/dri/i965/brw_blorp.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_batchbuffer.h"
  25 #include "intel_fbo.h"
  26
  27 #include "brw_blorp.h"
  28 #include "brw_defines.h"
  29 #include "gen6_blorp.h"
  30 #include "gen7_blorp.h"
  31
  32 #define FILE_DEBUG_FLAG DEBUG_BLORP
  33
  34 brw_blorp_mip_info::brw_blorp_mip_info()
  35    : mt(NULL),
  36      level(0),
  37      layer(0),
  38      width(0),
  39      height(0),
  40      x_offset(0),
  41      y_offset(0)
  42 {
  43 }
  44
  45 brw_blorp_surface_info::brw_blorp_surface_info()
  46    : map_stencil_as_y_tiled(false),
  47      num_samples(0)
  48 {
  49 }
  50
  51 void
  52 brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
  53                         unsigned int level, unsigned int layer)
  54 {
  55    intel_miptree_check_level_layer(mt, level, layer);
  56
  57    this->mt = mt;
  58    this->level = level;
  59    this->layer = layer;
  60    this->width = mt->level[level].width;
  61    this->height = mt->level[level].height;
  62
  63    intel_miptree_get_image_offset(mt, level, layer, &x_offset, &y_offset);
  64 }
  65
  66 void
  67 brw_blorp_surface_info::set(struct brw_context *brw,
  68                             struct intel_mipmap_tree *mt,
  69                             unsigned int level, unsigned int layer)
  70 {
  71    brw_blorp_mip_info::set(mt, level, layer);
  72    this->num_samples = mt->num_samples;
  73    this->array_spacing_lod0 = mt->array_spacing_lod0;
  74    this->map_stencil_as_y_tiled = false;
  75    this->msaa_layout = mt->msaa_layout;
  76
  77    switch (mt->format) {
  78    case MESA_FORMAT_S8:
  79       /* The miptree is a W-tiled stencil buffer.  Surface states can't be set
  80        * up for W tiling, so we'll need to use Y tiling and have the WM
  81        * program swizzle the coordinates.
  82        */
  83       this->map_stencil_as_y_tiled = true;
  84       this->brw_surfaceformat = BRW_SURFACEFORMAT_R8_UNORM;
  85       break;
  86    case MESA_FORMAT_X8_Z24:
  87    case MESA_FORMAT_Z32_FLOAT:
  88       /* The miptree consists of 32 bits per pixel, arranged either as 24-bit
  89        * depth values interleaved with 8 "don't care" bits, or as 32-bit
  90        * floating point depth values.  Since depth values don't require any
  91        * blending, it doesn't matter how we interpret the bit pattern as long
  92        * as we copy the right amount of data, so just map it as 8-bit BGRA.
  93        */
  94       this->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
  95       break;
  96    case MESA_FORMAT_Z16:
  97       /* The miptree consists of 16 bits per pixel of depth data.  Since depth
  98        * values don't require any blending, it doesn't matter how we interpret
  99        * the bit pattern as long as we copy the right amount of data, so just
 100        * map is as 8-bit RG.
 101        */
 102       this->brw_surfaceformat = BRW_SURFACEFORMAT_R8G8_UNORM;
 103       break;
 104    default:
 105       /* Blorp blits don't support any sort of format conversion (except
 106        * between sRGB and linear), so we can safely assume that the format is
 107        * supported as a render target, even if this is the source image.  So
 108        * we can convert to a surface format using brw->render_target_format.
 109        */
 110       assert(brw->format_supported_as_render_target[mt->format]);
 111       this->brw_surfaceformat = brw->render_target_format[mt->format];
 112       break;
 113    }
 114 }
 115
 116
 117 /**
 118  * Split x_offset and y_offset into a base offset (in bytes) and a remaining
 119  * x/y offset (in pixels).  Note: we can't do this by calling
 120  * intel_renderbuffer_tile_offsets(), because the offsets may have been
 121  * adjusted to account for Y vs. W tiling differences.  So we compute it
 122  * directly from the adjusted offsets.
 123  */
 124 uint32_t
 125 brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
 126                                              uint32_t *tile_y) const
 127 {
 128    struct intel_region *region = mt->region;
 129    uint32_t mask_x, mask_y;
 130
 131    intel_region_get_tile_masks(region, &mask_x, &mask_y,
 132                                map_stencil_as_y_tiled);
 133
 134    *tile_x = x_offset & mask_x;
 135    *tile_y = y_offset & mask_y;
 136
 137    return intel_region_get_aligned_offset(region, x_offset & ~mask_x,
 138                                           y_offset & ~mask_y,
 139                                           map_stencil_as_y_tiled);
 140 }
 141
 142
 143 brw_blorp_params::brw_blorp_params()
 144    : x0(0),
 145      y0(0),
 146      x1(0),
 147      y1(0),
 148      depth_format(0),
 149      hiz_op(GEN6_HIZ_OP_NONE),
 150      fast_clear_op(GEN7_FAST_CLEAR_OP_NONE),
 151      num_samples(0),
 152      use_wm_prog(false)
 153 {
 154    color_write_disable[0] = false;
 155    color_write_disable[1] = false;
 156    color_write_disable[2] = false;
 157    color_write_disable[3] = false;
 158 }
 159
 160 extern "C" {
 161 void
 162 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 163                unsigned int level, unsigned int layer, gen6_hiz_op op)
 164 {
 165    const char *opname = NULL;
 166
 167    switch (op) {
 168    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 169       opname = "depth resolve";
 170       break;
 171    case GEN6_HIZ_OP_HIZ_RESOLVE:
 172       opname = "hiz ambiguate";
 173       break;
 174    case GEN6_HIZ_OP_DEPTH_CLEAR:
 175       opname = "depth clear";
 176       break;
 177    case GEN6_HIZ_OP_NONE:
 178       opname = "noop?";
 179       break;
 180    }
 181
 182    DBG("%s %s to mt %p level %d layer %d\n",
 183        __FUNCTION__, opname, mt, level, layer);
 184
 185    brw_hiz_op_params params(mt, level, layer, op);
 186    brw_blorp_exec(brw, &params);
 187 }
 188
 189 } /* extern "C" */
 190
 191 void
 192 brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params)
 193 {
 194    switch (brw->gen) {
 195    case 6:
 196       gen6_blorp_exec(brw, params);
 197       break;
 198    case 7:
 199       gen7_blorp_exec(brw, params);
 200       break;
 201    default:
 202       /* BLORP is not supported before Gen6. */
 203       assert(false);
 204       break;
 205    }
 206
 207    if (unlikely(brw->always_flush_batch))
 208       intel_batchbuffer_flush(brw);
 209
 210    /* We've smashed all state compared to what the normal 3D pipeline
 211     * rendering tracks for GL.
 212     */
 213    brw->state.dirty.brw = ~0;
 214    brw->state.dirty.cache = ~0;
 215    brw->state_batch_count = 0;
 216    brw->batch.need_workaround_flush = true;
 217
 218    /* Flush the sampler cache so any texturing from the destination is
 219     * coherent.
 220     */
 221    intel_batchbuffer_emit_mi_flush(brw);
 222 }
 223
 224 brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
 225                                      unsigned int level,
 226                                      unsigned int layer,
 227                                      gen6_hiz_op op)
 228 {
 229    this->hiz_op = op;
 230
 231    depth.set(mt, level, layer);
 232
 233    /* Align the rectangle primitive to 8x4 pixels.
 234     *
 235     * During fast depth clears, the emitted rectangle primitive  must be
 236     * aligned to 8x4 pixels.  From the Ivybridge PRM, Vol 2 Part 1 Section
 237     * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
 238     * PRM):
 239     *     If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
 240     *     aligned to an 8x4 pixel block relative to the upper left corner
 241     *     of the depth buffer [...]
 242     *
 243     * For hiz resolves, the rectangle must also be 8x4 aligned. Item
 244     * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
 245     * Ivybridge simulator require the alignment.
 246     *
 247     * To be safe, let's just align the rect for all hiz operations and all
 248     * hardware generations.
 249     *
 250     * However, for some miptree slices of a Z24 texture, emitting an 8x4
 251     * aligned rectangle that covers the slice may clobber adjacent slices if
 252     * we strictly adhered to the texture alignments specified in the PRM.  The
 253     * Ivybridge PRM, Section "Alignment Unit Size", states that
 254     * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
 255     * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
 256     * prevents the clobbering.
 257     */
 258    depth.width = ALIGN(depth.width, 8);
 259    depth.height = ALIGN(depth.height, 4);
 260
 261    x1 = depth.width;
 262    y1 = depth.height;
 263
 264    assert(intel_miptree_slice_has_hiz(mt, level, layer));
 265
 266    switch (mt->format) {
 267    case MESA_FORMAT_Z16:       depth_format = BRW_DEPTHFORMAT_D16_UNORM; break;
 268    case MESA_FORMAT_Z32_FLOAT: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break;
 269    case MESA_FORMAT_X8_Z24:    depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break;
 270    default:                    assert(0); break;
 271    }
 272 }
 273
 274 uint32_t
 275 brw_hiz_op_params::get_wm_prog(struct brw_context *brw,
 276                                brw_blorp_prog_data **prog_data) const
 277 {
 278    return 0;
 279 }