2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_batchbuffer.h"
26 #include "intel_fbo.h"
28 #include "brw_blorp.h"
29 #include "brw_defines.h"
30 #include "brw_state.h"
31 #include "gen6_blorp.h"
32 #include "gen7_blorp.h"
34 #define FILE_DEBUG_FLAG DEBUG_BLORP
36 brw_blorp_mip_info::brw_blorp_mip_info()
47 brw_blorp_surface_info::brw_blorp_surface_info()
48 : map_stencil_as_y_tiled(false),
54 brw_blorp_mip_info::set(struct intel_mipmap_tree
*mt
,
55 unsigned int level
, unsigned int layer
)
57 /* Layer is a physical layer, so if this is a 2D multisample array texture
58 * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it had better
59 * be a multiple of num_samples.
61 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
62 mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
63 assert(layer
% mt
->num_samples
== 0);
66 intel_miptree_check_level_layer(mt
, level
, layer
);
71 this->width
= mt
->level
[level
].width
;
72 this->height
= mt
->level
[level
].height
;
74 intel_miptree_get_image_offset(mt
, level
, layer
, &x_offset
, &y_offset
);
78 brw_blorp_surface_info::set(struct brw_context
*brw
,
79 struct intel_mipmap_tree
*mt
,
80 unsigned int level
, unsigned int layer
,
81 bool is_render_target
)
83 brw_blorp_mip_info::set(mt
, level
, layer
);
84 this->num_samples
= mt
->num_samples
;
85 this->array_spacing_lod0
= mt
->array_spacing_lod0
;
86 this->map_stencil_as_y_tiled
= false;
87 this->msaa_layout
= mt
->msaa_layout
;
91 /* The miptree is a W-tiled stencil buffer. Surface states can't be set
92 * up for W tiling, so we'll need to use Y tiling and have the WM
93 * program swizzle the coordinates.
95 this->map_stencil_as_y_tiled
= true;
96 this->brw_surfaceformat
= BRW_SURFACEFORMAT_R8_UNORM
;
98 case MESA_FORMAT_X8_Z24
:
99 /* It would make sense to use BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
100 * here, but unfortunately it isn't supported as a render target, which
101 * would prevent us from blitting to 24-bit depth.
103 * The miptree consists of 32 bits per pixel, arranged as 24-bit depth
104 * values interleaved with 8 "don't care" bits. Since depth values don't
105 * require any blending, it doesn't matter how we interpret the bit
106 * pattern as long as we copy the right amount of data, so just map it
109 this->brw_surfaceformat
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
111 case MESA_FORMAT_Z32_FLOAT
:
112 this->brw_surfaceformat
= BRW_SURFACEFORMAT_R32_FLOAT
;
114 case MESA_FORMAT_Z16
:
115 this->brw_surfaceformat
= BRW_SURFACEFORMAT_R16_UNORM
;
118 gl_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
119 if (is_render_target
) {
120 assert(brw
->format_supported_as_render_target
[linear_format
]);
121 this->brw_surfaceformat
= brw
->render_target_format
[linear_format
];
123 this->brw_surfaceformat
= brw_format_for_mesa_format(linear_format
);
132 * Split x_offset and y_offset into a base offset (in bytes) and a remaining
133 * x/y offset (in pixels). Note: we can't do this by calling
134 * intel_renderbuffer_tile_offsets(), because the offsets may have been
135 * adjusted to account for Y vs. W tiling differences. So we compute it
136 * directly from the adjusted offsets.
139 brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x
,
140 uint32_t *tile_y
) const
142 struct intel_region
*region
= mt
->region
;
143 uint32_t mask_x
, mask_y
;
145 intel_region_get_tile_masks(region
, &mask_x
, &mask_y
,
146 map_stencil_as_y_tiled
);
148 *tile_x
= x_offset
& mask_x
;
149 *tile_y
= y_offset
& mask_y
;
151 return intel_region_get_aligned_offset(region
, x_offset
& ~mask_x
,
153 map_stencil_as_y_tiled
);
157 brw_blorp_params::brw_blorp_params()
163 hiz_op(GEN6_HIZ_OP_NONE
),
164 fast_clear_op(GEN7_FAST_CLEAR_OP_NONE
),
167 color_write_disable
[0] = false;
168 color_write_disable
[1] = false;
169 color_write_disable
[2] = false;
170 color_write_disable
[3] = false;
175 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
176 unsigned int level
, unsigned int layer
, gen6_hiz_op op
)
178 const char *opname
= NULL
;
181 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
182 opname
= "depth resolve";
184 case GEN6_HIZ_OP_HIZ_RESOLVE
:
185 opname
= "hiz ambiguate";
187 case GEN6_HIZ_OP_DEPTH_CLEAR
:
188 opname
= "depth clear";
190 case GEN6_HIZ_OP_NONE
:
195 DBG("%s %s to mt %p level %d layer %d\n",
196 __FUNCTION__
, opname
, mt
, level
, layer
);
198 brw_hiz_op_params
params(mt
, level
, layer
, op
);
199 brw_blorp_exec(brw
, ¶ms
);
205 brw_blorp_exec(struct brw_context
*brw
, const brw_blorp_params
*params
)
207 struct gl_context
*ctx
= &brw
->ctx
;
208 uint32_t estimated_max_batch_usage
= 1500;
209 bool check_aperture_failed_once
= false;
211 /* Flush the sampler and render caches. We definitely need to flush the
212 * sampler cache so that we get updated contents from the render cache for
213 * the glBlitFramebuffer() source. Also, we are sometimes warned in the
214 * docs to flush the cache between reinterpretations of the same surface
215 * data with different formats, which blorp does for stencil and depth
218 intel_batchbuffer_emit_mi_flush(brw
);
221 intel_batchbuffer_require_space(brw
, estimated_max_batch_usage
, RENDER_RING
);
222 intel_batchbuffer_save_state(brw
);
223 drm_intel_bo
*saved_bo
= brw
->batch
.bo
;
224 uint32_t saved_used
= brw
->batch
.used
;
225 uint32_t saved_state_batch_offset
= brw
->batch
.state_batch_offset
;
229 gen6_blorp_exec(brw
, params
);
232 gen7_blorp_exec(brw
, params
);
235 /* BLORP is not supported before Gen6. */
240 /* Make sure we didn't wrap the batch unintentionally, and make sure we
241 * reserved enough space that a wrap will never happen.
243 assert(brw
->batch
.bo
== saved_bo
);
244 assert((brw
->batch
.used
- saved_used
) * 4 +
245 (saved_state_batch_offset
- brw
->batch
.state_batch_offset
) <
246 estimated_max_batch_usage
);
247 /* Shut up compiler warnings on release build */
250 (void)saved_state_batch_offset
;
252 /* Check if the blorp op we just did would make our batch likely to fail to
253 * map all the BOs into the GPU at batch exec time later. If so, flush the
254 * batch and try again with nothing else in the batch.
256 if (dri_bufmgr_check_aperture_space(&brw
->batch
.bo
, 1)) {
257 if (!check_aperture_failed_once
) {
258 check_aperture_failed_once
= true;
259 intel_batchbuffer_reset_to_saved(brw
);
260 intel_batchbuffer_flush(brw
);
263 int ret
= intel_batchbuffer_flush(brw
);
264 WARN_ONCE(ret
== -ENOSPC
,
265 "i965: blorp emit exceeded available aperture space\n");
269 if (unlikely(brw
->always_flush_batch
))
270 intel_batchbuffer_flush(brw
);
272 /* We've smashed all state compared to what the normal 3D pipeline
273 * rendering tracks for GL.
275 brw
->state
.dirty
.brw
= ~0;
276 brw
->state
.dirty
.cache
= ~0;
277 brw
->batch
.need_workaround_flush
= true;
279 intel_batchbuffer_clear_cache(brw
);
281 /* Flush the sampler cache so any texturing from the destination is
284 intel_batchbuffer_emit_mi_flush(brw
);
287 brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree
*mt
,
294 depth
.set(mt
, level
, layer
);
296 /* Align the rectangle primitive to 8x4 pixels.
298 * During fast depth clears, the emitted rectangle primitive must be
299 * aligned to 8x4 pixels. From the Ivybridge PRM, Vol 2 Part 1 Section
300 * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
302 * If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
303 * aligned to an 8x4 pixel block relative to the upper left corner
304 * of the depth buffer [...]
306 * For hiz resolves, the rectangle must also be 8x4 aligned. Item
307 * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
308 * Ivybridge simulator require the alignment.
310 * To be safe, let's just align the rect for all hiz operations and all
311 * hardware generations.
313 * However, for some miptree slices of a Z24 texture, emitting an 8x4
314 * aligned rectangle that covers the slice may clobber adjacent slices if
315 * we strictly adhered to the texture alignments specified in the PRM. The
316 * Ivybridge PRM, Section "Alignment Unit Size", states that
317 * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
318 * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
319 * prevents the clobbering.
321 depth
.width
= ALIGN(depth
.width
, 8);
322 depth
.height
= ALIGN(depth
.height
, 4);
327 assert(intel_miptree_slice_has_hiz(mt
, level
, layer
));
329 switch (mt
->format
) {
330 case MESA_FORMAT_Z16
: depth_format
= BRW_DEPTHFORMAT_D16_UNORM
; break;
331 case MESA_FORMAT_Z32_FLOAT
: depth_format
= BRW_DEPTHFORMAT_D32_FLOAT
; break;
332 case MESA_FORMAT_X8_Z24
: depth_format
= BRW_DEPTHFORMAT_D24_UNORM_X8_UINT
; break;
333 default: assert(0); break;
338 brw_hiz_op_params::get_wm_prog(struct brw_context
*brw
,
339 brw_blorp_prog_data
**prog_data
) const