src/mesa/drivers/dri/i965/brw_blorp.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_fbo.h"
  25
  26 #include "brw_blorp.h"
  27 #include "brw_defines.h"
  28 #include "gen6_blorp.h"
  29 #include "gen7_blorp.h"
  30
  31 brw_blorp_mip_info::brw_blorp_mip_info()
  32    : mt(NULL),
  33      width(0),
  34      height(0),
  35      x_offset(0),
  36      y_offset(0)
  37 {
  38 }
  39
  40 brw_blorp_surface_info::brw_blorp_surface_info()
  41    : map_stencil_as_y_tiled(false),
  42      num_samples(0)
  43 {
  44 }
  45
  46 void
  47 brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
  48                         unsigned int level, unsigned int layer)
  49 {
  50    intel_miptree_check_level_layer(mt, level, layer);
  51
  52    this->mt = mt;
  53    this->width = mt->level[level].width;
  54    this->height = mt->level[level].height;
  55
  56    intel_miptree_get_image_offset(mt, level, layer, &x_offset, &y_offset);
  57 }
  58
  59 void
  60 brw_blorp_surface_info::set(struct brw_context *brw,
  61                             struct intel_mipmap_tree *mt,
  62                             unsigned int level, unsigned int layer)
  63 {
  64    brw_blorp_mip_info::set(mt, level, layer);
  65    this->num_samples = mt->num_samples;
  66    this->array_spacing_lod0 = mt->array_spacing_lod0;
  67    this->map_stencil_as_y_tiled = false;
  68    this->msaa_layout = mt->msaa_layout;
  69
  70    switch (mt->format) {
  71    case MESA_FORMAT_S8:
  72       /* The miptree is a W-tiled stencil buffer.  Surface states can't be set
  73        * up for W tiling, so we'll need to use Y tiling and have the WM
  74        * program swizzle the coordinates.
  75        */
  76       this->map_stencil_as_y_tiled = true;
  77       this->brw_surfaceformat = BRW_SURFACEFORMAT_R8_UNORM;
  78       break;
  79    case MESA_FORMAT_X8_Z24:
  80    case MESA_FORMAT_Z32_FLOAT:
  81       /* The miptree consists of 32 bits per pixel, arranged either as 24-bit
  82        * depth values interleaved with 8 "don't care" bits, or as 32-bit
  83        * floating point depth values.  Since depth values don't require any
  84        * blending, it doesn't matter how we interpret the bit pattern as long
  85        * as we copy the right amount of data, so just map it as 8-bit BGRA.
  86        */
  87       this->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
  88       break;
  89    case MESA_FORMAT_Z16:
  90       /* The miptree consists of 16 bits per pixel of depth data.  Since depth
  91        * values don't require any blending, it doesn't matter how we interpret
  92        * the bit pattern as long as we copy the right amount of data, so just
  93        * map is as 8-bit RG.
  94        */
  95       this->brw_surfaceformat = BRW_SURFACEFORMAT_R8G8_UNORM;
  96       break;
  97    default:
  98       /* Blorp blits don't support any sort of format conversion (except
  99        * between sRGB and linear), so we can safely assume that the format is
 100        * supported as a render target, even if this is the source image.  So
 101        * we can convert to a surface format using brw->render_target_format.
 102        */
 103       assert(brw->format_supported_as_render_target[mt->format]);
 104       this->brw_surfaceformat = brw->render_target_format[mt->format];
 105       break;
 106    }
 107 }
 108
 109
 110 /**
 111  * Split x_offset and y_offset into a base offset (in bytes) and a remaining
 112  * x/y offset (in pixels).  Note: we can't do this by calling
 113  * intel_renderbuffer_tile_offsets(), because the offsets may have been
 114  * adjusted to account for Y vs. W tiling differences.  So we compute it
 115  * directly from the adjusted offsets.
 116  */
 117 uint32_t
 118 brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
 119                                              uint32_t *tile_y) const
 120 {
 121    struct intel_region *region = mt->region;
 122    uint32_t mask_x, mask_y;
 123
 124    intel_region_get_tile_masks(region, &mask_x, &mask_y,
 125                                map_stencil_as_y_tiled);
 126
 127    *tile_x = x_offset & mask_x;
 128    *tile_y = y_offset & mask_y;
 129
 130    return intel_region_get_aligned_offset(region, x_offset & ~mask_x,
 131                                           y_offset & ~mask_y,
 132                                           map_stencil_as_y_tiled);
 133 }
 134
 135
 136 brw_blorp_params::brw_blorp_params()
 137    : x0(0),
 138      y0(0),
 139      x1(0),
 140      y1(0),
 141      depth_format(0),
 142      hiz_op(GEN6_HIZ_OP_NONE),
 143      num_samples(0),
 144      use_wm_prog(false)
 145 {
 146 }
 147
 148 extern "C" {
 149 void
 150 intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt,
 151                unsigned int level, unsigned int layer, gen6_hiz_op op)
 152 {
 153    brw_hiz_op_params params(mt, level, layer, op);
 154    brw_blorp_exec(intel, &params);
 155 }
 156
 157 } /* extern "C" */
 158
 159 void
 160 brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params)
 161 {
 162    switch (intel->gen) {
 163    case 6:
 164       gen6_blorp_exec(intel, params);
 165       break;
 166    case 7:
 167       gen7_blorp_exec(intel, params);
 168       break;
 169    default:
 170       /* BLORP is not supported before Gen6. */
 171       assert(false);
 172       break;
 173    }
 174 }
 175
 176 brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
 177                                      unsigned int level,
 178                                      unsigned int layer,
 179                                      gen6_hiz_op op)
 180 {
 181    this->hiz_op = op;
 182
 183    depth.set(mt, level, layer);
 184    x1 = depth.width;
 185    y1 = depth.height;
 186
 187    assert(mt->hiz_mt != NULL);
 188
 189    switch (mt->format) {
 190    case MESA_FORMAT_Z16:       depth_format = BRW_DEPTHFORMAT_D16_UNORM; break;
 191    case MESA_FORMAT_Z32_FLOAT: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break;
 192    case MESA_FORMAT_X8_Z24:    depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break;
 193    default:                    assert(0); break;
 194    }
 195 }
 196
 197 uint32_t
 198 brw_hiz_op_params::get_wm_prog(struct brw_context *brw,
 199                                brw_blorp_prog_data **prog_data) const
 200 {
 201    return 0;
 202 }