src/mesa/drivers/dri/i965/brw_blorp.h

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #pragma once
  25
  26 #include <stdint.h>
  27
  28 #include "brw_context.h"
  29 #include "intel_mipmap_tree.h"
  30
  31 struct brw_context;
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 void
  38 brw_blorp_blit_miptrees(struct intel_context *intel,
  39                         struct intel_mipmap_tree *src_mt,
  40                         unsigned src_level, unsigned src_layer,
  41                         struct intel_mipmap_tree *dst_mt,
  42                         unsigned dst_level, unsigned dst_layer,
  43                         float src_x0, float src_y0,
  44                         float src_x1, float src_y1,
  45                         float dst_x0, float dst_y0,
  46                         float dst_x1, float dst_y1,
  47                         bool mirror_x, bool mirror_y);
  48
  49 bool
  50 brw_blorp_clear_color(struct intel_context *intel, struct gl_framebuffer *fb,
  51                       bool partial_clear);
  52
  53 #ifdef __cplusplus
  54 } /* end extern "C" */
  55
  56 /**
  57  * Binding table indices used by BLORP.
  58  */
  59 enum {
  60    BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX,
  61    BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
  62    BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
  63 };
  64
  65
  66 class brw_blorp_mip_info
  67 {
  68 public:
  69    brw_blorp_mip_info();
  70
  71    void set(struct intel_mipmap_tree *mt,
  72             unsigned int level, unsigned int layer);
  73
  74    struct intel_mipmap_tree *mt;
  75
  76    /**
  77     * The miplevel to use.
  78     */
  79    uint32_t level;
  80
  81    /**
  82     * The 2D layer within the miplevel. Combined, level and layer define the
  83     * 2D miptree slice to use.
  84     */
  85    uint32_t layer;
  86
  87    /**
  88     * Width of the miplevel to be used.  For surfaces using
  89     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
  90     */
  91    uint32_t width;
  92
  93    /**
  94     * Height of the miplevel to be used.  For surfaces using
  95     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
  96     */
  97    uint32_t height;
  98
  99    /**
 100     * X offset within the surface to texture from (or render to).  For
 101     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
 102     * pixels.
 103     */
 104    uint32_t x_offset;
 105
 106    /**
 107     * Y offset within the surface to texture from (or render to).  For
 108     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
 109     * pixels.
 110     */
 111    uint32_t y_offset;
 112 };
 113
 114 class brw_blorp_surface_info : public brw_blorp_mip_info
 115 {
 116 public:
 117    brw_blorp_surface_info();
 118
 119    void set(struct brw_context *brw,
 120             struct intel_mipmap_tree *mt,
 121             unsigned int level, unsigned int layer);
 122
 123    uint32_t compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const;
 124
 125    /* Setting this flag indicates that the buffer's contents are W-tiled
 126     * stencil data, but the surface state should be set up for Y tiled
 127     * MESA_FORMAT_R8 data (this is necessary because surface states don't
 128     * support W tiling).
 129     *
 130     * Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of
 131     * MESA_FORMAT_R8 data are 128 pixels wide by 32 pixels high, the width and
 132     * pitch stored in the surface state will be multiplied by 2, and the
 133     * height will be halved.  Also, since W and Y tiles store their data in a
 134     * different order, the width and height will be rounded up to a multiple
 135     * of the tile size, to ensure that the WM program can access the full
 136     * width and height of the buffer.
 137     */
 138    bool map_stencil_as_y_tiled;
 139
 140    unsigned num_samples;
 141
 142    /* Setting this flag indicates that the surface should be set up in
 143     * ARYSPC_LOD0 mode.  Ignored prior to Gen7.
 144     */
 145    bool array_spacing_lod0;
 146
 147    /**
 148     * Format that should be used when setting up the surface state for this
 149     * surface.  Should correspond to one of the BRW_SURFACEFORMAT_* enums.
 150     */
 151    uint32_t brw_surfaceformat;
 152
 153    /**
 154     * For MSAA surfaces, MSAA layout that should be used when setting up the
 155     * surface state for this surface.
 156     */
 157    intel_msaa_layout msaa_layout;
 158 };
 159
 160
 161 struct brw_blorp_coord_transform_params
 162 {
 163    void setup(GLfloat src0, GLfloat src1, GLfloat dst0, GLfloat dst1,
 164               bool mirror);
 165
 166    float multiplier;
 167    float offset;
 168 };
 169
 170
 171 struct brw_blorp_wm_push_constants
 172 {
 173    uint32_t dst_x0;
 174    uint32_t dst_x1;
 175    uint32_t dst_y0;
 176    uint32_t dst_y1;
 177    brw_blorp_coord_transform_params x_transform;
 178    brw_blorp_coord_transform_params y_transform;
 179 };
 180
 181 /* Every 32 bytes of push constant data constitutes one GEN register. */
 182 const unsigned int BRW_BLORP_NUM_PUSH_CONST_REGS =
 183    sizeof(brw_blorp_wm_push_constants) / 32;
 184
 185 struct brw_blorp_prog_data
 186 {
 187    unsigned int first_curbe_grf;
 188
 189    /**
 190     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 191     * than one sample per pixel.
 192     */
 193    bool persample_msaa_dispatch;
 194 };
 195
 196
 197 enum gen7_fast_clear_op {
 198    GEN7_FAST_CLEAR_OP_NONE,
 199    GEN7_FAST_CLEAR_OP_FAST_CLEAR,
 200 };
 201
 202
 203 class brw_blorp_params
 204 {
 205 public:
 206    brw_blorp_params();
 207
 208    virtual uint32_t get_wm_prog(struct brw_context *brw,
 209                                 brw_blorp_prog_data **prog_data) const = 0;
 210
 211    uint32_t x0;
 212    uint32_t y0;
 213    uint32_t x1;
 214    uint32_t y1;
 215    brw_blorp_mip_info depth;
 216    uint32_t depth_format;
 217    brw_blorp_surface_info src;
 218    brw_blorp_surface_info dst;
 219    enum gen6_hiz_op hiz_op;
 220    enum gen7_fast_clear_op fast_clear_op;
 221    unsigned num_samples;
 222    bool use_wm_prog;
 223    brw_blorp_wm_push_constants wm_push_consts;
 224    bool color_write_disable[4];
 225 };
 226
 227
 228 void
 229 brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params);
 230
 231
 232 /**
 233  * Parameters for a HiZ or depth resolve operation.
 234  *
 235  * For an overview of HiZ ops, see the following sections of the Sandy Bridge
 236  * PRM, Volume 1, Part 2:
 237  *   - 7.5.3.1 Depth Buffer Clear
 238  *   - 7.5.3.2 Depth Buffer Resolve
 239  *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
 240  */
 241 class brw_hiz_op_params : public brw_blorp_params
 242 {
 243 public:
 244    brw_hiz_op_params(struct intel_mipmap_tree *mt,
 245                      unsigned int level, unsigned int layer,
 246                      gen6_hiz_op op);
 247
 248    virtual uint32_t get_wm_prog(struct brw_context *brw,
 249                                 brw_blorp_prog_data **prog_data) const;
 250 };
 251
 252 struct brw_blorp_blit_prog_key
 253 {
 254    /* Number of samples per pixel that have been configured in the surface
 255     * state for texturing from.
 256     */
 257    unsigned tex_samples;
 258
 259    /* MSAA layout that has been configured in the surface state for texturing
 260     * from.
 261     */
 262    intel_msaa_layout tex_layout;
 263
 264    /* Actual number of samples per pixel in the source image. */
 265    unsigned src_samples;
 266
 267    /* Actual MSAA layout used by the source image. */
 268    intel_msaa_layout src_layout;
 269
 270    /* Number of samples per pixel that have been configured in the render
 271     * target.
 272     */
 273    unsigned rt_samples;
 274
 275    /* MSAA layout that has been configured in the render target. */
 276    intel_msaa_layout rt_layout;
 277
 278    /* Actual number of samples per pixel in the destination image. */
 279    unsigned dst_samples;
 280
 281    /* Actual MSAA layout used by the destination image. */
 282    intel_msaa_layout dst_layout;
 283
 284    /* Type of the data to be read from the texture (one of
 285     * BRW_REGISTER_TYPE_{UD,D,F}).
 286     */
 287    unsigned texture_data_type;
 288
 289    /* True if the source image is W tiled.  If true, the surface state for the
 290     * source image must be configured as Y tiled, and tex_samples must be 0.
 291     */
 292    bool src_tiled_w;
 293
 294    /* True if the destination image is W tiled.  If true, the surface state
 295     * for the render target must be configured as Y tiled, and rt_samples must
 296     * be 0.
 297     */
 298    bool dst_tiled_w;
 299
 300    /* True if all source samples should be blended together to produce each
 301     * destination pixel.  If true, src_tiled_w must be false, tex_samples must
 302     * equal src_samples, and tex_samples must be nonzero.
 303     */
 304    bool blend;
 305
 306    /* True if the rectangle being sent through the rendering pipeline might be
 307     * larger than the destination rectangle, so the WM program should kill any
 308     * pixels that are outside the destination rectangle.
 309     */
 310    bool use_kill;
 311
 312    /**
 313     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 314     * than one sample per pixel.
 315     */
 316    bool persample_msaa_dispatch;
 317 };
 318
 319 class brw_blorp_blit_params : public brw_blorp_params
 320 {
 321 public:
 322    brw_blorp_blit_params(struct brw_context *brw,
 323                          struct intel_mipmap_tree *src_mt,
 324                          unsigned src_level, unsigned src_layer,
 325                          struct intel_mipmap_tree *dst_mt,
 326                          unsigned dst_level, unsigned dst_layer,
 327                          GLfloat src_x0, GLfloat src_y0,
 328                          GLfloat src_x1, GLfloat src_y1,
 329                          GLfloat dst_x0, GLfloat dst_y0,
 330                          GLfloat dst_x1, GLfloat dst_y1,
 331                          bool mirror_x, bool mirror_y);
 332
 333    virtual uint32_t get_wm_prog(struct brw_context *brw,
 334                                 brw_blorp_prog_data **prog_data) const;
 335
 336 private:
 337    brw_blorp_blit_prog_key wm_prog_key;
 338 };
 339
 340 /**
 341  * \name BLORP internals
 342  * \{
 343  *
 344  * Used internally by gen6_blorp_exec() and gen7_blorp_exec().
 345  */
 346
 347 void
 348 gen6_blorp_init(struct brw_context *brw);
 349
 350 void
 351 gen6_blorp_emit_batch_head(struct brw_context *brw,
 352                            const brw_blorp_params *params);
 353
 354 void
 355 gen6_blorp_emit_state_base_address(struct brw_context *brw,
 356                                    const brw_blorp_params *params);
 357
 358 void
 359 gen6_blorp_emit_vertices(struct brw_context *brw,
 360                          const brw_blorp_params *params);
 361
 362 uint32_t
 363 gen6_blorp_emit_blend_state(struct brw_context *brw,
 364                             const brw_blorp_params *params);
 365
 366 uint32_t
 367 gen6_blorp_emit_cc_state(struct brw_context *brw,
 368                          const brw_blorp_params *params);
 369
 370 uint32_t
 371 gen6_blorp_emit_wm_constants(struct brw_context *brw,
 372                              const brw_blorp_params *params);
 373
 374 void
 375 gen6_blorp_emit_vs_disable(struct brw_context *brw,
 376                            const brw_blorp_params *params);
 377
 378 uint32_t
 379 gen6_blorp_emit_binding_table(struct brw_context *brw,
 380                               const brw_blorp_params *params,
 381                               uint32_t wm_surf_offset_renderbuffer,
 382                               uint32_t wm_surf_offset_texture);
 383
 384 uint32_t
 385 gen6_blorp_emit_depth_stencil_state(struct brw_context *brw,
 386                                     const brw_blorp_params *params);
 387
 388 void
 389 gen6_blorp_emit_gs_disable(struct brw_context *brw,
 390                            const brw_blorp_params *params);
 391
 392 void
 393 gen6_blorp_emit_clip_disable(struct brw_context *brw,
 394                              const brw_blorp_params *params);
 395
 396 void
 397 gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
 398                                   const brw_blorp_params *params);
 399 /** \} */
 400
 401 #endif /* __cplusplus */