src/mesa/drivers/dri/i965/brw_blorp.h

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #pragma once
  25
  26 #include <stdint.h>
  27
  28 #include "brw_reg.h"
  29 #include "intel_mipmap_tree.h"
  30
  31 struct brw_context;
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 void
  38 brw_blorp_blit_miptrees(struct brw_context *brw,
  39                         struct intel_mipmap_tree *src_mt,
  40                         unsigned src_level, unsigned src_layer,
  41                         mesa_format src_format, int src_swizzle,
  42                         struct intel_mipmap_tree *dst_mt,
  43                         unsigned dst_level, unsigned dst_layer,
  44                         mesa_format dst_format,
  45                         float src_x0, float src_y0,
  46                         float src_x1, float src_y1,
  47                         float dst_x0, float dst_y0,
  48                         float dst_x1, float dst_y1,
  49                         GLenum filter, bool mirror_x, bool mirror_y,
  50                         bool decode_srgb, bool encode_srgb);
  51
  52 bool
  53 brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb,
  54                       GLbitfield mask, bool partial_clear, bool encode_srgb);
  55
  56 void
  57 brw_blorp_resolve_color(struct brw_context *brw,
  58                         struct intel_mipmap_tree *mt);
  59
  60 #ifdef __cplusplus
  61 } /* end extern "C" */
  62
  63 /**
  64  * Binding table indices used by BLORP.
  65  */
  66 enum {
  67    BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
  68    BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX,
  69    BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
  70 };
  71
  72
  73 class brw_blorp_mip_info
  74 {
  75 public:
  76    brw_blorp_mip_info();
  77
  78    void set(struct intel_mipmap_tree *mt,
  79             unsigned int level, unsigned int layer);
  80
  81    struct intel_mipmap_tree *mt;
  82
  83    /**
  84     * The miplevel to use.
  85     */
  86    uint32_t level;
  87
  88    /**
  89     * The 2D layer within the miplevel. Combined, level and layer define the
  90     * 2D miptree slice to use.
  91     *
  92     * Note: if mt is a 2D multisample array texture on Gen7+ using
  93     * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, layer is the physical
  94     * layer holding sample 0.  So, for example, if mt->num_samples == 4, then
  95     * logical layer n corresponds to layer == 4*n.
  96     */
  97    uint32_t layer;
  98
  99    /**
 100     * Width of the miplevel to be used.  For surfaces using
 101     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
 102     */
 103    uint32_t width;
 104
 105    /**
 106     * Height of the miplevel to be used.  For surfaces using
 107     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
 108     */
 109    uint32_t height;
 110
 111    /**
 112     * X offset within the surface to texture from (or render to).  For
 113     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
 114     * pixels.
 115     */
 116    uint32_t x_offset;
 117
 118    /**
 119     * Y offset within the surface to texture from (or render to).  For
 120     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
 121     * pixels.
 122     */
 123    uint32_t y_offset;
 124 };
 125
 126 class brw_blorp_surface_info : public brw_blorp_mip_info
 127 {
 128 public:
 129    brw_blorp_surface_info();
 130
 131    void set(struct brw_context *brw,
 132             struct intel_mipmap_tree *mt,
 133             unsigned int level, unsigned int layer,
 134             mesa_format format, bool is_render_target);
 135
 136    uint32_t compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const;
 137
 138    /* Setting this flag indicates that the buffer's contents are W-tiled
 139     * stencil data, but the surface state should be set up for Y tiled
 140     * MESA_FORMAT_R_UNORM8 data (this is necessary because surface states don't
 141     * support W tiling).
 142     *
 143     * Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of
 144     * MESA_FORMAT_R_UNORM8 data are 128 pixels wide by 32 pixels high, the width and
 145     * pitch stored in the surface state will be multiplied by 2, and the
 146     * height will be halved.  Also, since W and Y tiles store their data in a
 147     * different order, the width and height will be rounded up to a multiple
 148     * of the tile size, to ensure that the WM program can access the full
 149     * width and height of the buffer.
 150     */
 151    bool map_stencil_as_y_tiled;
 152
 153    unsigned num_samples;
 154
 155    /**
 156     * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
 157     * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
 158     *
 159     * If ALL_SLICES_AT_EACH_LOD is set, then ARYSPC_LOD0 can be used. Ignored
 160     * prior to Gen7.
 161     */
 162    enum miptree_array_layout array_layout;
 163
 164    /**
 165     * Format that should be used when setting up the surface state for this
 166     * surface.  Should correspond to one of the BRW_SURFACEFORMAT_* enums.
 167     */
 168    uint32_t brw_surfaceformat;
 169
 170    /**
 171     * For MSAA surfaces, MSAA layout that should be used when setting up the
 172     * surface state for this surface.
 173     */
 174    intel_msaa_layout msaa_layout;
 175
 176    /**
 177     * In order to support cases where RGBA format is backing client requested
 178     * RGB, one needs to have means to force alpha channel to one when user
 179     * requested RGB surface is used as blit source. This is possible by
 180     * setting source swizzle for the texture surface.
 181     */
 182    int swizzle;
 183 };
 184
 185
 186 struct brw_blorp_coord_transform_params
 187 {
 188    void setup(GLfloat src0, GLfloat src1, GLfloat dst0, GLfloat dst1,
 189               bool mirror);
 190
 191    float multiplier;
 192    float offset;
 193 };
 194
 195
 196 struct brw_blorp_wm_push_constants
 197 {
 198    uint32_t dst_x0;
 199    uint32_t dst_x1;
 200    uint32_t dst_y0;
 201    uint32_t dst_y1;
 202    /* Top right coordinates of the rectangular grid used for scaled blitting */
 203    float rect_grid_x1;
 204    float rect_grid_y1;
 205    brw_blorp_coord_transform_params x_transform;
 206    brw_blorp_coord_transform_params y_transform;
 207
 208    /* Minimum layer setting works for all the textures types but texture_3d
 209     * for which the setting has no effect. Use the z-coordinate instead.
 210     */
 211    uint32_t src_z;
 212
 213    /* Pad out to an integral number of registers */
 214    uint32_t pad[5];
 215 };
 216
 217 /* Every 32 bytes of push constant data constitutes one GEN register. */
 218 const unsigned int BRW_BLORP_NUM_PUSH_CONST_REGS =
 219    sizeof(brw_blorp_wm_push_constants) / 32;
 220
 221 struct brw_blorp_prog_data
 222 {
 223    unsigned int first_curbe_grf;
 224
 225    /**
 226     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 227     * than one sample per pixel.
 228     */
 229    bool persample_msaa_dispatch;
 230 };
 231
 232
 233 class brw_blorp_params
 234 {
 235 public:
 236    brw_blorp_params(unsigned num_varyings = 0,
 237                     unsigned num_draw_buffers = 1,
 238                     unsigned num_layers = 1);
 239
 240    virtual uint32_t get_wm_prog(struct brw_context *brw,
 241                                 brw_blorp_prog_data **prog_data) const = 0;
 242
 243    uint32_t x0;
 244    uint32_t y0;
 245    uint32_t x1;
 246    uint32_t y1;
 247    brw_blorp_mip_info depth;
 248    uint32_t depth_format;
 249    brw_blorp_surface_info src;
 250    brw_blorp_surface_info dst;
 251    enum gen6_hiz_op hiz_op;
 252    unsigned fast_clear_op;
 253    bool color_write_disable[4];
 254    bool use_wm_prog;
 255    brw_blorp_wm_push_constants wm_push_consts;
 256    const unsigned num_varyings;
 257    const unsigned num_draw_buffers;
 258    const unsigned num_layers;
 259 };
 260
 261
 262 void
 263 brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params);
 264
 265 void
 266 gen6_blorp_exec(struct brw_context *brw,
 267                 const brw_blorp_params *params);
 268
 269 void
 270 gen7_blorp_exec(struct brw_context *brw,
 271                 const brw_blorp_params *params);
 272
 273 void
 274 gen8_blorp_exec(struct brw_context *brw, const brw_blorp_params *params);
 275
 276 /**
 277  * Parameters for a HiZ or depth resolve operation.
 278  *
 279  * For an overview of HiZ ops, see the following sections of the Sandy Bridge
 280  * PRM, Volume 1, Part 2:
 281  *   - 7.5.3.1 Depth Buffer Clear
 282  *   - 7.5.3.2 Depth Buffer Resolve
 283  *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
 284  */
 285 class brw_hiz_op_params : public brw_blorp_params
 286 {
 287 public:
 288    brw_hiz_op_params(struct intel_mipmap_tree *mt,
 289                      unsigned int level, unsigned int layer,
 290                      gen6_hiz_op op);
 291
 292    virtual uint32_t get_wm_prog(struct brw_context *brw,
 293                                 brw_blorp_prog_data **prog_data) const;
 294 };
 295
 296 struct brw_blorp_blit_prog_key
 297 {
 298    /* Number of samples per pixel that have been configured in the surface
 299     * state for texturing from.
 300     */
 301    unsigned tex_samples;
 302
 303    /* MSAA layout that has been configured in the surface state for texturing
 304     * from.
 305     */
 306    intel_msaa_layout tex_layout;
 307
 308    /* Actual number of samples per pixel in the source image. */
 309    unsigned src_samples;
 310
 311    /* Actual MSAA layout used by the source image. */
 312    intel_msaa_layout src_layout;
 313
 314    /* Number of samples per pixel that have been configured in the render
 315     * target.
 316     */
 317    unsigned rt_samples;
 318
 319    /* MSAA layout that has been configured in the render target. */
 320    intel_msaa_layout rt_layout;
 321
 322    /* Actual number of samples per pixel in the destination image. */
 323    unsigned dst_samples;
 324
 325    /* Actual MSAA layout used by the destination image. */
 326    intel_msaa_layout dst_layout;
 327
 328    /* Type of the data to be read from the texture (one of
 329     * BRW_REGISTER_TYPE_{UD,D,F}).
 330     */
 331    enum brw_reg_type texture_data_type;
 332
 333    /* True if the source image is W tiled.  If true, the surface state for the
 334     * source image must be configured as Y tiled, and tex_samples must be 0.
 335     */
 336    bool src_tiled_w;
 337
 338    /* True if the destination image is W tiled.  If true, the surface state
 339     * for the render target must be configured as Y tiled, and rt_samples must
 340     * be 0.
 341     */
 342    bool dst_tiled_w;
 343
 344    /* True if all source samples should be blended together to produce each
 345     * destination pixel.  If true, src_tiled_w must be false, tex_samples must
 346     * equal src_samples, and tex_samples must be nonzero.
 347     */
 348    bool blend;
 349
 350    /* True if the rectangle being sent through the rendering pipeline might be
 351     * larger than the destination rectangle, so the WM program should kill any
 352     * pixels that are outside the destination rectangle.
 353     */
 354    bool use_kill;
 355
 356    /**
 357     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 358     * than one sample per pixel.
 359     */
 360    bool persample_msaa_dispatch;
 361
 362    /* True for scaled blitting. */
 363    bool blit_scaled;
 364
 365    /* Scale factors between the pixel grid and the grid of samples. We're
 366     * using grid of samples for bilinear filetring in multisample scaled blits.
 367     */
 368    float x_scale;
 369    float y_scale;
 370
 371    /* True for blits with filter = GL_LINEAR. */
 372    bool bilinear_filter;
 373 };
 374
 375 class brw_blorp_blit_params : public brw_blorp_params
 376 {
 377 public:
 378    brw_blorp_blit_params(struct brw_context *brw,
 379                          struct intel_mipmap_tree *src_mt,
 380                          unsigned src_level, unsigned src_layer,
 381                          mesa_format src_format,
 382                          struct intel_mipmap_tree *dst_mt,
 383                          unsigned dst_level, unsigned dst_layer,
 384                          mesa_format dst_format,
 385                          GLfloat src_x0, GLfloat src_y0,
 386                          GLfloat src_x1, GLfloat src_y1,
 387                          GLfloat dst_x0, GLfloat dst_y0,
 388                          GLfloat dst_x1, GLfloat dst_y1,
 389                          GLenum filter, bool mirror_x, bool mirror_y);
 390
 391    virtual uint32_t get_wm_prog(struct brw_context *brw,
 392                                 brw_blorp_prog_data **prog_data) const;
 393
 394 private:
 395    brw_blorp_blit_prog_key wm_prog_key;
 396 };
 397
 398 /**
 399  * \name BLORP internals
 400  * \{
 401  *
 402  * Used internally by gen6_blorp_exec() and gen7_blorp_exec().
 403  */
 404
 405 void
 406 gen6_blorp_init(struct brw_context *brw);
 407
 408 void
 409 gen6_blorp_emit_state_base_address(struct brw_context *brw,
 410                                    const brw_blorp_params *params);
 411
 412 void
 413 gen6_blorp_emit_vertices(struct brw_context *brw,
 414                          const brw_blorp_params *params);
 415
 416 uint32_t
 417 gen6_blorp_emit_blend_state(struct brw_context *brw,
 418                             const brw_blorp_params *params);
 419
 420 uint32_t
 421 gen6_blorp_emit_cc_state(struct brw_context *brw);
 422
 423 uint32_t
 424 gen6_blorp_emit_wm_constants(struct brw_context *brw,
 425                              const brw_blorp_params *params);
 426
 427 void
 428 gen6_blorp_emit_vs_disable(struct brw_context *brw,
 429                            const brw_blorp_params *params);
 430
 431 uint32_t
 432 gen6_blorp_emit_binding_table(struct brw_context *brw,
 433                               uint32_t wm_surf_offset_renderbuffer,
 434                               uint32_t wm_surf_offset_texture);
 435
 436 uint32_t
 437 gen6_blorp_emit_depth_stencil_state(struct brw_context *brw,
 438                                     const brw_blorp_params *params);
 439
 440 void
 441 gen6_blorp_emit_gs_disable(struct brw_context *brw,
 442                            const brw_blorp_params *params);
 443
 444 void
 445 gen6_blorp_emit_clip_disable(struct brw_context *brw);
 446
 447 void
 448 gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
 449                                   const brw_blorp_params *params);
 450
 451 uint32_t
 452 gen6_blorp_emit_sampler_state(struct brw_context *brw,
 453                               unsigned tex_filter, unsigned max_lod,
 454                               bool non_normalized_coords);
 455 void
 456 gen7_blorp_emit_urb_config(struct brw_context *brw);
 457
 458 void
 459 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
 460                                     uint32_t cc_blend_state_offset);
 461
 462 void
 463 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
 464                                  uint32_t cc_state_offset);
 465
 466 void
 467 gen7_blorp_emit_cc_viewport(struct brw_context *brw);
 468
 469 void
 470 gen7_blorp_emit_te_disable(struct brw_context *brw);
 471
 472 void
 473 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 474                                           uint32_t wm_bind_bo_offset);
 475
 476 void
 477 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 478                                           uint32_t sampler_offset);
 479
 480 void
 481 gen7_blorp_emit_clear_params(struct brw_context *brw,
 482                              const brw_blorp_params *params);
 483
 484 void
 485 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 486                             uint32_t wm_push_const_offset);
 487
 488 void
 489 gen7_blorp_emit_constant_ps_disable(struct brw_context *brw);
 490
 491 void
 492 gen7_blorp_emit_primitive(struct brw_context *brw,
 493                           const brw_blorp_params *params);
 494
 495 /** \} */
 496
 497 #endif /* __cplusplus */