src/mesa/drivers/dri/i965/brw_blorp.h

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #pragma once
  25
  26 #include <stdint.h>
  27
  28 #include "brw_reg.h"
  29 #include "intel_mipmap_tree.h"
  30
  31 struct brw_context;
  32 struct brw_wm_prog_key;
  33
  34 #ifdef __cplusplus
  35 extern "C" {
  36 #endif
  37
  38 void
  39 brw_blorp_blit_miptrees(struct brw_context *brw,
  40                         struct intel_mipmap_tree *src_mt,
  41                         unsigned src_level, unsigned src_layer,
  42                         mesa_format src_format, int src_swizzle,
  43                         struct intel_mipmap_tree *dst_mt,
  44                         unsigned dst_level, unsigned dst_layer,
  45                         mesa_format dst_format,
  46                         float src_x0, float src_y0,
  47                         float src_x1, float src_y1,
  48                         float dst_x0, float dst_y0,
  49                         float dst_x1, float dst_y1,
  50                         GLenum filter, bool mirror_x, bool mirror_y,
  51                         bool decode_srgb, bool encode_srgb);
  52
  53 bool
  54 brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb,
  55                       GLbitfield mask, bool partial_clear, bool encode_srgb);
  56
  57 void
  58 brw_blorp_resolve_color(struct brw_context *brw,
  59                         struct intel_mipmap_tree *mt);
  60
  61 /**
  62  * Binding table indices used by BLORP.
  63  */
  64 enum {
  65    BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
  66    BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX,
  67    BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
  68 };
  69
  70 struct brw_blorp_surface_info
  71 {
  72    struct intel_mipmap_tree *mt;
  73
  74    /**
  75     * The miplevel to use.
  76     */
  77    uint32_t level;
  78
  79    /**
  80     * The 2D layer within the miplevel. Combined, level and layer define the
  81     * 2D miptree slice to use.
  82     *
  83     * Note: if mt is a 2D multisample array texture on Gen7+ using
  84     * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, layer is the physical
  85     * layer holding sample 0.  So, for example, if mt->num_samples == 4, then
  86     * logical layer n corresponds to layer == 4*n.
  87     */
  88    uint32_t layer;
  89
  90    /**
  91     * Width of the miplevel to be used.  For surfaces using
  92     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
  93     */
  94    uint32_t width;
  95
  96    /**
  97     * Height of the miplevel to be used.  For surfaces using
  98     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
  99     */
 100    uint32_t height;
 101
 102    /**
 103     * X offset within the surface to texture from (or render to).  For
 104     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
 105     * pixels.
 106     */
 107    uint32_t x_offset;
 108
 109    /**
 110     * Y offset within the surface to texture from (or render to).  For
 111     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
 112     * pixels.
 113     */
 114    uint32_t y_offset;
 115
 116    /* Setting this flag indicates that the buffer's contents are W-tiled
 117     * stencil data, but the surface state should be set up for Y tiled
 118     * MESA_FORMAT_R_UNORM8 data (this is necessary because surface states don't
 119     * support W tiling).
 120     *
 121     * Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of
 122     * MESA_FORMAT_R_UNORM8 data are 128 pixels wide by 32 pixels high, the width and
 123     * pitch stored in the surface state will be multiplied by 2, and the
 124     * height will be halved.  Also, since W and Y tiles store their data in a
 125     * different order, the width and height will be rounded up to a multiple
 126     * of the tile size, to ensure that the WM program can access the full
 127     * width and height of the buffer.
 128     */
 129    bool map_stencil_as_y_tiled;
 130
 131    unsigned num_samples;
 132
 133    /**
 134     * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
 135     * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
 136     *
 137     * If ALL_SLICES_AT_EACH_LOD is set, then ARYSPC_LOD0 can be used. Ignored
 138     * prior to Gen7.
 139     */
 140    enum miptree_array_layout array_layout;
 141
 142    /**
 143     * Format that should be used when setting up the surface state for this
 144     * surface.  Should correspond to one of the BRW_SURFACEFORMAT_* enums.
 145     */
 146    uint32_t brw_surfaceformat;
 147
 148    /**
 149     * For MSAA surfaces, MSAA layout that should be used when setting up the
 150     * surface state for this surface.
 151     */
 152    enum intel_msaa_layout msaa_layout;
 153
 154    /**
 155     * In order to support cases where RGBA format is backing client requested
 156     * RGB, one needs to have means to force alpha channel to one when user
 157     * requested RGB surface is used as blit source. This is possible by
 158     * setting source swizzle for the texture surface.
 159     */
 160    int swizzle;
 161 };
 162
 163 void
 164 brw_blorp_surface_info_init(struct brw_context *brw,
 165                             struct brw_blorp_surface_info *info,
 166                             struct intel_mipmap_tree *mt,
 167                             unsigned int level, unsigned int layer,
 168                             mesa_format format, bool is_render_target);
 169
 170 uint32_t
 171 brw_blorp_compute_tile_offsets(const struct brw_blorp_surface_info *info,
 172                                uint32_t *tile_x, uint32_t *tile_y);
 173
 174
 175
 176 struct brw_blorp_coord_transform
 177 {
 178    float multiplier;
 179    float offset;
 180 };
 181
 182 struct brw_blorp_wm_push_constants
 183 {
 184    uint32_t dst_x0;
 185    uint32_t dst_x1;
 186    uint32_t dst_y0;
 187    uint32_t dst_y1;
 188    /* Top right coordinates of the rectangular grid used for scaled blitting */
 189    float rect_grid_x1;
 190    float rect_grid_y1;
 191    struct brw_blorp_coord_transform x_transform;
 192    struct brw_blorp_coord_transform y_transform;
 193
 194    /* Minimum layer setting works for all the textures types but texture_3d
 195     * for which the setting has no effect. Use the z-coordinate instead.
 196     */
 197    uint32_t src_z;
 198
 199    /* Pad out to an integral number of registers */
 200    uint32_t pad[5];
 201 };
 202
 203 #define BRW_BLORP_NUM_PUSH_CONSTANT_DWORDS \
 204    (sizeof(struct brw_blorp_wm_push_constants) / 4)
 205
 206 /* Every 32 bytes of push constant data constitutes one GEN register. */
 207 static const unsigned int BRW_BLORP_NUM_PUSH_CONST_REGS =
 208    sizeof(struct brw_blorp_wm_push_constants) / 32;
 209
 210 struct brw_blorp_prog_data
 211 {
 212    bool dispatch_8;
 213    bool dispatch_16;
 214
 215    uint8_t first_curbe_grf_0;
 216    uint8_t first_curbe_grf_2;
 217
 218    uint32_t ksp_offset_2;
 219
 220    /**
 221     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 222     * than one sample per pixel.
 223     */
 224    bool persample_msaa_dispatch;
 225
 226    /* The compiler will re-arrange push constants and store the upload order
 227     * here. Given an index 'i' in the final upload buffer, param[i] gives the
 228     * index in the uniform store. In other words, the value to be uploaded can
 229     * be found by brw_blorp_params::wm_push_consts[param[i]].
 230     */
 231    uint8_t nr_params;
 232    uint8_t param[BRW_BLORP_NUM_PUSH_CONSTANT_DWORDS];
 233 };
 234
 235 struct brw_blorp_params
 236 {
 237    uint32_t x0;
 238    uint32_t y0;
 239    uint32_t x1;
 240    uint32_t y1;
 241    struct brw_blorp_surface_info depth;
 242    uint32_t depth_format;
 243    struct brw_blorp_surface_info src;
 244    struct brw_blorp_surface_info dst;
 245    enum gen6_hiz_op hiz_op;
 246    union {
 247       unsigned fast_clear_op;
 248       unsigned resolve_type;
 249    };
 250    bool color_write_disable[4];
 251    struct brw_blorp_wm_push_constants wm_push_consts;
 252    unsigned num_varyings;
 253    unsigned num_draw_buffers;
 254    unsigned num_layers;
 255    uint32_t wm_prog_kernel;
 256    struct brw_blorp_prog_data *wm_prog_data;
 257 };
 258
 259 void
 260 brw_blorp_params_init(struct brw_blorp_params *params);
 261
 262 void
 263 brw_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params);
 264
 265 void
 266 gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 267                     unsigned level, unsigned layer, enum gen6_hiz_op op);
 268
 269 void
 270 gen6_blorp_exec(struct brw_context *brw,
 271                 const struct brw_blorp_params *params);
 272
 273 void
 274 gen7_blorp_exec(struct brw_context *brw,
 275                 const struct brw_blorp_params *params);
 276
 277 void
 278 gen8_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params);
 279
 280 struct brw_blorp_blit_prog_key
 281 {
 282    /* Number of samples per pixel that have been configured in the surface
 283     * state for texturing from.
 284     */
 285    unsigned tex_samples;
 286
 287    /* MSAA layout that has been configured in the surface state for texturing
 288     * from.
 289     */
 290    enum intel_msaa_layout tex_layout;
 291
 292    /* Actual number of samples per pixel in the source image. */
 293    unsigned src_samples;
 294
 295    /* Actual MSAA layout used by the source image. */
 296    enum intel_msaa_layout src_layout;
 297
 298    /* Number of samples per pixel that have been configured in the render
 299     * target.
 300     */
 301    unsigned rt_samples;
 302
 303    /* MSAA layout that has been configured in the render target. */
 304    enum intel_msaa_layout rt_layout;
 305
 306    /* Actual number of samples per pixel in the destination image. */
 307    unsigned dst_samples;
 308
 309    /* Actual MSAA layout used by the destination image. */
 310    enum intel_msaa_layout dst_layout;
 311
 312    /* Type of the data to be read from the texture (one of
 313     * BRW_REGISTER_TYPE_{UD,D,F}).
 314     */
 315    enum brw_reg_type texture_data_type;
 316
 317    /* True if the source image is W tiled.  If true, the surface state for the
 318     * source image must be configured as Y tiled, and tex_samples must be 0.
 319     */
 320    bool src_tiled_w;
 321
 322    /* True if the destination image is W tiled.  If true, the surface state
 323     * for the render target must be configured as Y tiled, and rt_samples must
 324     * be 0.
 325     */
 326    bool dst_tiled_w;
 327
 328    /* True if all source samples should be blended together to produce each
 329     * destination pixel.  If true, src_tiled_w must be false, tex_samples must
 330     * equal src_samples, and tex_samples must be nonzero.
 331     */
 332    bool blend;
 333
 334    /* True if the rectangle being sent through the rendering pipeline might be
 335     * larger than the destination rectangle, so the WM program should kill any
 336     * pixels that are outside the destination rectangle.
 337     */
 338    bool use_kill;
 339
 340    /**
 341     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 342     * than one sample per pixel.
 343     */
 344    bool persample_msaa_dispatch;
 345
 346    /* True for scaled blitting. */
 347    bool blit_scaled;
 348
 349    /* Scale factors between the pixel grid and the grid of samples. We're
 350     * using grid of samples for bilinear filetring in multisample scaled blits.
 351     */
 352    float x_scale;
 353    float y_scale;
 354
 355    /* True for blits with filter = GL_LINEAR. */
 356    bool bilinear_filter;
 357 };
 358
 359 /**
 360  * \name BLORP internals
 361  * \{
 362  *
 363  * Used internally by gen6_blorp_exec() and gen7_blorp_exec().
 364  */
 365
 366 void brw_blorp_init_wm_prog_key(struct brw_wm_prog_key *wm_key);
 367
 368 const unsigned *
 369 brw_blorp_compile_nir_shader(struct brw_context *brw, struct nir_shader *nir,
 370                              const struct brw_wm_prog_key *wm_key,
 371                              bool use_repclear,
 372                              struct brw_blorp_prog_data *prog_data,
 373                              unsigned *program_size);
 374
 375 void
 376 gen6_blorp_init(struct brw_context *brw);
 377
 378 void
 379 gen6_blorp_emit_vertices(struct brw_context *brw,
 380                          const struct brw_blorp_params *params);
 381
 382 uint32_t
 383 gen6_blorp_emit_blend_state(struct brw_context *brw,
 384                             const struct brw_blorp_params *params);
 385
 386 uint32_t
 387 gen6_blorp_emit_cc_state(struct brw_context *brw);
 388
 389 uint32_t
 390 gen6_blorp_emit_wm_constants(struct brw_context *brw,
 391                              const struct brw_blorp_params *params);
 392
 393 void
 394 gen6_blorp_emit_vs_disable(struct brw_context *brw,
 395                            const struct brw_blorp_params *params);
 396
 397 uint32_t
 398 gen6_blorp_emit_binding_table(struct brw_context *brw,
 399                               uint32_t wm_surf_offset_renderbuffer,
 400                               uint32_t wm_surf_offset_texture);
 401
 402 uint32_t
 403 gen6_blorp_emit_depth_stencil_state(struct brw_context *brw,
 404                                     const struct brw_blorp_params *params);
 405
 406 void
 407 gen6_blorp_emit_gs_disable(struct brw_context *brw,
 408                            const struct brw_blorp_params *params);
 409
 410 void
 411 gen6_blorp_emit_clip_disable(struct brw_context *brw);
 412
 413 void
 414 gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
 415                                   const struct brw_blorp_params *params);
 416
 417 uint32_t
 418 gen6_blorp_emit_sampler_state(struct brw_context *brw,
 419                               unsigned tex_filter, unsigned max_lod,
 420                               bool non_normalized_coords);
 421 void
 422 gen7_blorp_emit_urb_config(struct brw_context *brw);
 423
 424 void
 425 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
 426                                     uint32_t cc_blend_state_offset);
 427
 428 void
 429 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
 430                                  uint32_t cc_state_offset);
 431
 432 void
 433 gen7_blorp_emit_cc_viewport(struct brw_context *brw);
 434
 435 void
 436 gen7_blorp_emit_te_disable(struct brw_context *brw);
 437
 438 void
 439 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 440                                           uint32_t wm_bind_bo_offset);
 441
 442 void
 443 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 444                                           uint32_t sampler_offset);
 445
 446 void
 447 gen7_blorp_emit_clear_params(struct brw_context *brw,
 448                              const struct brw_blorp_params *params);
 449
 450 void
 451 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 452                             uint32_t wm_push_const_offset);
 453
 454 void
 455 gen7_blorp_emit_constant_ps_disable(struct brw_context *brw);
 456
 457 void
 458 gen7_blorp_emit_primitive(struct brw_context *brw,
 459                           const struct brw_blorp_params *params);
 460
 461 /** \} */
 462
 463 #ifdef __cplusplus
 464 } /* end extern "C" */
 465 #endif /* __cplusplus */