src/mesa/drivers/dri/i965/brw_blorp.h

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #pragma once
  25
  26 #include <stdint.h>
  27
  28 #include "brw_context.h"
  29 #include "intel_mipmap_tree.h"
  30
  31 struct brw_context;
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 void
  38 brw_blorp_blit_miptrees(struct intel_context *intel,
  39                         struct intel_mipmap_tree *src_mt,
  40                         unsigned src_level, unsigned src_layer,
  41                         struct intel_mipmap_tree *dst_mt,
  42                         unsigned dst_level, unsigned dst_layer,
  43                         int src_x0, int src_y0,
  44                         int dst_x0, int dst_y0,
  45                         int dst_x1, int dst_y1,
  46                         bool mirror_x, bool mirror_y);
  47
  48 bool
  49 brw_blorp_clear_color(struct intel_context *intel, struct gl_framebuffer *fb);
  50
  51 #ifdef __cplusplus
  52 } /* end extern "C" */
  53
  54 /**
  55  * Binding table indices used by BLORP.
  56  */
  57 enum {
  58    BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX,
  59    BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
  60    BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
  61 };
  62
  63
  64 class brw_blorp_mip_info
  65 {
  66 public:
  67    brw_blorp_mip_info();
  68
  69    void set(struct intel_mipmap_tree *mt,
  70             unsigned int level, unsigned int layer);
  71
  72    struct intel_mipmap_tree *mt;
  73
  74    /**
  75     * The miplevel to use.
  76     */
  77    uint32_t level;
  78
  79    /**
  80     * The 2D layer within the miplevel. Combined, level and layer define the
  81     * 2D miptree slice to use.
  82     */
  83    uint32_t layer;
  84
  85    /**
  86     * Width of the miplevel to be used.  For surfaces using
  87     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
  88     */
  89    uint32_t width;
  90
  91    /**
  92     * Height of the miplevel to be used.  For surfaces using
  93     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
  94     */
  95    uint32_t height;
  96
  97    /**
  98     * X offset within the surface to texture from (or render to).  For
  99     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
 100     * pixels.
 101     */
 102    uint32_t x_offset;
 103
 104    /**
 105     * Y offset within the surface to texture from (or render to).  For
 106     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
 107     * pixels.
 108     */
 109    uint32_t y_offset;
 110 };
 111
 112 class brw_blorp_surface_info : public brw_blorp_mip_info
 113 {
 114 public:
 115    brw_blorp_surface_info();
 116
 117    void set(struct brw_context *brw,
 118             struct intel_mipmap_tree *mt,
 119             unsigned int level, unsigned int layer);
 120
 121    uint32_t compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const;
 122
 123    /* Setting this flag indicates that the buffer's contents are W-tiled
 124     * stencil data, but the surface state should be set up for Y tiled
 125     * MESA_FORMAT_R8 data (this is necessary because surface states don't
 126     * support W tiling).
 127     *
 128     * Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of
 129     * MESA_FORMAT_R8 data are 128 pixels wide by 32 pixels high, the width and
 130     * pitch stored in the surface state will be multiplied by 2, and the
 131     * height will be halved.  Also, since W and Y tiles store their data in a
 132     * different order, the width and height will be rounded up to a multiple
 133     * of the tile size, to ensure that the WM program can access the full
 134     * width and height of the buffer.
 135     */
 136    bool map_stencil_as_y_tiled;
 137
 138    unsigned num_samples;
 139
 140    /* Setting this flag indicates that the surface should be set up in
 141     * ARYSPC_LOD0 mode.  Ignored prior to Gen7.
 142     */
 143    bool array_spacing_lod0;
 144
 145    /**
 146     * Format that should be used when setting up the surface state for this
 147     * surface.  Should correspond to one of the BRW_SURFACEFORMAT_* enums.
 148     */
 149    uint32_t brw_surfaceformat;
 150
 151    /**
 152     * For MSAA surfaces, MSAA layout that should be used when setting up the
 153     * surface state for this surface.
 154     */
 155    intel_msaa_layout msaa_layout;
 156 };
 157
 158
 159 struct brw_blorp_coord_transform_params
 160 {
 161    void setup(GLuint src0, GLuint dst0, GLuint dst1,
 162               bool mirror);
 163
 164    int16_t multiplier;
 165    int16_t offset;
 166 };
 167
 168
 169 struct brw_blorp_wm_push_constants
 170 {
 171    uint16_t dst_x0;
 172    uint16_t dst_x1;
 173    uint16_t dst_y0;
 174    uint16_t dst_y1;
 175    brw_blorp_coord_transform_params x_transform;
 176    brw_blorp_coord_transform_params y_transform;
 177
 178    /* Pad out to an integral number of registers */
 179    uint16_t pad[8];
 180 };
 181
 182 /* Every 32 bytes of push constant data constitutes one GEN register. */
 183 const unsigned int BRW_BLORP_NUM_PUSH_CONST_REGS =
 184    sizeof(brw_blorp_wm_push_constants) / 32;
 185
 186 struct brw_blorp_prog_data
 187 {
 188    unsigned int first_curbe_grf;
 189
 190    /**
 191     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 192     * than one sample per pixel.
 193     */
 194    bool persample_msaa_dispatch;
 195 };
 196
 197 class brw_blorp_params
 198 {
 199 public:
 200    brw_blorp_params();
 201
 202    virtual uint32_t get_wm_prog(struct brw_context *brw,
 203                                 brw_blorp_prog_data **prog_data) const = 0;
 204
 205    uint32_t x0;
 206    uint32_t y0;
 207    uint32_t x1;
 208    uint32_t y1;
 209    brw_blorp_mip_info depth;
 210    uint32_t depth_format;
 211    brw_blorp_surface_info src;
 212    brw_blorp_surface_info dst;
 213    enum gen6_hiz_op hiz_op;
 214    unsigned num_samples;
 215    bool use_wm_prog;
 216    brw_blorp_wm_push_constants wm_push_consts;
 217    bool color_write_disable[4];
 218 };
 219
 220
 221 void
 222 brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params);
 223
 224
 225 /**
 226  * Parameters for a HiZ or depth resolve operation.
 227  *
 228  * For an overview of HiZ ops, see the following sections of the Sandy Bridge
 229  * PRM, Volume 1, Part 2:
 230  *   - 7.5.3.1 Depth Buffer Clear
 231  *   - 7.5.3.2 Depth Buffer Resolve
 232  *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
 233  */
 234 class brw_hiz_op_params : public brw_blorp_params
 235 {
 236 public:
 237    brw_hiz_op_params(struct intel_mipmap_tree *mt,
 238                      unsigned int level, unsigned int layer,
 239                      gen6_hiz_op op);
 240
 241    virtual uint32_t get_wm_prog(struct brw_context *brw,
 242                                 brw_blorp_prog_data **prog_data) const;
 243 };
 244
 245 struct brw_blorp_blit_prog_key
 246 {
 247    /* Number of samples per pixel that have been configured in the surface
 248     * state for texturing from.
 249     */
 250    unsigned tex_samples;
 251
 252    /* MSAA layout that has been configured in the surface state for texturing
 253     * from.
 254     */
 255    intel_msaa_layout tex_layout;
 256
 257    /* Actual number of samples per pixel in the source image. */
 258    unsigned src_samples;
 259
 260    /* Actual MSAA layout used by the source image. */
 261    intel_msaa_layout src_layout;
 262
 263    /* Number of samples per pixel that have been configured in the render
 264     * target.
 265     */
 266    unsigned rt_samples;
 267
 268    /* MSAA layout that has been configured in the render target. */
 269    intel_msaa_layout rt_layout;
 270
 271    /* Actual number of samples per pixel in the destination image. */
 272    unsigned dst_samples;
 273
 274    /* Actual MSAA layout used by the destination image. */
 275    intel_msaa_layout dst_layout;
 276
 277    /* Type of the data to be read from the texture (one of
 278     * BRW_REGISTER_TYPE_{UD,D,F}).
 279     */
 280    unsigned texture_data_type;
 281
 282    /* True if the source image is W tiled.  If true, the surface state for the
 283     * source image must be configured as Y tiled, and tex_samples must be 0.
 284     */
 285    bool src_tiled_w;
 286
 287    /* True if the destination image is W tiled.  If true, the surface state
 288     * for the render target must be configured as Y tiled, and rt_samples must
 289     * be 0.
 290     */
 291    bool dst_tiled_w;
 292
 293    /* True if all source samples should be blended together to produce each
 294     * destination pixel.  If true, src_tiled_w must be false, tex_samples must
 295     * equal src_samples, and tex_samples must be nonzero.
 296     */
 297    bool blend;
 298
 299    /* True if the rectangle being sent through the rendering pipeline might be
 300     * larger than the destination rectangle, so the WM program should kill any
 301     * pixels that are outside the destination rectangle.
 302     */
 303    bool use_kill;
 304
 305    /**
 306     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 307     * than one sample per pixel.
 308     */
 309    bool persample_msaa_dispatch;
 310 };
 311
 312 class brw_blorp_blit_params : public brw_blorp_params
 313 {
 314 public:
 315    brw_blorp_blit_params(struct brw_context *brw,
 316                          struct intel_mipmap_tree *src_mt,
 317                          unsigned src_level, unsigned src_layer,
 318                          struct intel_mipmap_tree *dst_mt,
 319                          unsigned dst_level, unsigned dst_layer,
 320                          GLuint src_x0, GLuint src_y0,
 321                          GLuint dst_x0, GLuint dst_y0,
 322                          GLuint width, GLuint height,
 323                          bool mirror_x, bool mirror_y);
 324
 325    virtual uint32_t get_wm_prog(struct brw_context *brw,
 326                                 brw_blorp_prog_data **prog_data) const;
 327
 328 private:
 329    brw_blorp_blit_prog_key wm_prog_key;
 330 };
 331
 332 /**
 333  * \name BLORP internals
 334  * \{
 335  *
 336  * Used internally by gen6_blorp_exec() and gen7_blorp_exec().
 337  */
 338
 339 void
 340 gen6_blorp_init(struct brw_context *brw);
 341
 342 void
 343 gen6_blorp_emit_batch_head(struct brw_context *brw,
 344                            const brw_blorp_params *params);
 345
 346 void
 347 gen6_blorp_emit_state_base_address(struct brw_context *brw,
 348                                    const brw_blorp_params *params);
 349
 350 void
 351 gen6_blorp_emit_vertices(struct brw_context *brw,
 352                          const brw_blorp_params *params);
 353
 354 uint32_t
 355 gen6_blorp_emit_blend_state(struct brw_context *brw,
 356                             const brw_blorp_params *params);
 357
 358 uint32_t
 359 gen6_blorp_emit_cc_state(struct brw_context *brw,
 360                          const brw_blorp_params *params);
 361
 362 uint32_t
 363 gen6_blorp_emit_wm_constants(struct brw_context *brw,
 364                              const brw_blorp_params *params);
 365
 366 void
 367 gen6_blorp_emit_vs_disable(struct brw_context *brw,
 368                            const brw_blorp_params *params);
 369
 370 uint32_t
 371 gen6_blorp_emit_binding_table(struct brw_context *brw,
 372                               const brw_blorp_params *params,
 373                               uint32_t wm_surf_offset_renderbuffer,
 374                               uint32_t wm_surf_offset_texture);
 375
 376 uint32_t
 377 gen6_blorp_emit_depth_stencil_state(struct brw_context *brw,
 378                                     const brw_blorp_params *params);
 379
 380 void
 381 gen6_blorp_emit_gs_disable(struct brw_context *brw,
 382                            const brw_blorp_params *params);
 383
 384 void
 385 gen6_blorp_emit_clip_disable(struct brw_context *brw,
 386                              const brw_blorp_params *params);
 387
 388 void
 389 gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
 390                                   const brw_blorp_params *params);
 391 /** \} */
 392
 393 #endif /* __cplusplus */