src/mesa/drivers/dri/i965/brw_blorp.h

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #pragma once
  25
  26 #include <stdint.h>
  27
  28 #include "brw_context.h"
  29 #include "intel_mipmap_tree.h"
  30
  31 struct brw_context;
  32
  33
  34 /**
  35  * Binding table indices used by BLORP.
  36  */
  37 enum {
  38    BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX,
  39    BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
  40    BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
  41 };
  42
  43
  44 class brw_blorp_mip_info
  45 {
  46 public:
  47    brw_blorp_mip_info();
  48
  49    void set(struct intel_mipmap_tree *mt,
  50             unsigned int level, unsigned int layer);
  51    void get_draw_offsets(uint32_t *draw_x, uint32_t *draw_y) const;
  52
  53    void get_miplevel_dims(uint32_t *width, uint32_t *height) const
  54    {
  55       *width = mt->level[level].width;
  56       *height = mt->level[level].height;
  57    }
  58
  59    struct intel_mipmap_tree *mt;
  60    unsigned int level;
  61    unsigned int layer;
  62 };
  63
  64 class brw_blorp_surface_info : public brw_blorp_mip_info
  65 {
  66 public:
  67    brw_blorp_surface_info();
  68
  69 void set(struct brw_context *brw,
  70          struct intel_mipmap_tree *mt,
  71             unsigned int level, unsigned int layer);
  72
  73    /* Setting this flag indicates that the buffer's contents are W-tiled
  74     * stencil data, but the surface state should be set up for Y tiled
  75     * MESA_FORMAT_R8 data (this is necessary because surface states don't
  76     * support W tiling).
  77     *
  78     * Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of
  79     * MESA_FORMAT_R8 data are 128 pixels wide by 32 pixels high, the width and
  80     * pitch stored in the surface state will be multiplied by 2, and the
  81     * height will be halved.  Also, since W and Y tiles store their data in a
  82     * different order, the width and height will be rounded up to a multiple
  83     * of the tile size, to ensure that the WM program can access the full
  84     * width and height of the buffer.
  85     */
  86    bool map_stencil_as_y_tiled;
  87
  88    unsigned num_samples;
  89
  90    /* Setting this flag indicates that the surface should be set up in
  91     * ARYSPC_LOD0 mode.  Ignored prior to Gen7.
  92     */
  93    bool array_spacing_lod0;
  94
  95    /**
  96     * Format that should be used when setting up the surface state for this
  97     * surface.  Should correspond to one of the BRW_SURFACEFORMAT_* enums.
  98     */
  99    uint32_t brw_surfaceformat;
 100
 101    /**
 102     * For MSAA surfaces, MSAA layout that should be used when setting up the
 103     * surface state for this surface.
 104     */
 105    intel_msaa_layout msaa_layout;
 106 };
 107
 108
 109 struct brw_blorp_coord_transform_params
 110 {
 111    void setup(GLuint src0, GLuint dst0, GLuint dst1,
 112               bool mirror);
 113
 114    int16_t multiplier;
 115    int16_t offset;
 116 };
 117
 118
 119 struct brw_blorp_wm_push_constants
 120 {
 121    uint16_t dst_x0;
 122    uint16_t dst_x1;
 123    uint16_t dst_y0;
 124    uint16_t dst_y1;
 125    brw_blorp_coord_transform_params x_transform;
 126    brw_blorp_coord_transform_params y_transform;
 127
 128    /* Pad out to an integral number of registers */
 129    uint16_t pad[8];
 130 };
 131
 132 /* Every 32 bytes of push constant data constitutes one GEN register. */
 133 const unsigned int BRW_BLORP_NUM_PUSH_CONST_REGS =
 134    sizeof(brw_blorp_wm_push_constants) / 32;
 135
 136 struct brw_blorp_prog_data
 137 {
 138    unsigned int first_curbe_grf;
 139
 140    /**
 141     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 142     * than one sample per pixel.
 143     */
 144    bool persample_msaa_dispatch;
 145 };
 146
 147 class brw_blorp_params
 148 {
 149 public:
 150    brw_blorp_params();
 151
 152    virtual uint32_t get_wm_prog(struct brw_context *brw,
 153                                 brw_blorp_prog_data **prog_data) const = 0;
 154
 155    uint32_t x0;
 156    uint32_t y0;
 157    uint32_t x1;
 158    uint32_t y1;
 159    brw_blorp_mip_info depth;
 160    uint32_t depth_format;
 161    brw_blorp_surface_info src;
 162    brw_blorp_surface_info dst;
 163    enum gen6_hiz_op hiz_op;
 164    unsigned num_samples;
 165    bool use_wm_prog;
 166    brw_blorp_wm_push_constants wm_push_consts;
 167 };
 168
 169
 170 void
 171 brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params);
 172
 173
 174 /**
 175  * Parameters for a HiZ or depth resolve operation.
 176  *
 177  * For an overview of HiZ ops, see the following sections of the Sandy Bridge
 178  * PRM, Volume 1, Part 2:
 179  *   - 7.5.3.1 Depth Buffer Clear
 180  *   - 7.5.3.2 Depth Buffer Resolve
 181  *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
 182  */
 183 class brw_hiz_op_params : public brw_blorp_params
 184 {
 185 public:
 186    brw_hiz_op_params(struct intel_mipmap_tree *mt,
 187                      unsigned int level, unsigned int layer,
 188                      gen6_hiz_op op);
 189
 190    virtual uint32_t get_wm_prog(struct brw_context *brw,
 191                                 brw_blorp_prog_data **prog_data) const;
 192 };
 193
 194 struct brw_blorp_blit_prog_key
 195 {
 196    /* Number of samples per pixel that have been configured in the surface
 197     * state for texturing from.
 198     */
 199    unsigned tex_samples;
 200
 201    /* MSAA layout that has been configured in the surface state for texturing
 202     * from.
 203     */
 204    intel_msaa_layout tex_layout;
 205
 206    /* Actual number of samples per pixel in the source image. */
 207    unsigned src_samples;
 208
 209    /* Actual MSAA layout used by the source image. */
 210    intel_msaa_layout src_layout;
 211
 212    /* Number of samples per pixel that have been configured in the render
 213     * target.
 214     */
 215    unsigned rt_samples;
 216
 217    /* MSAA layout that has been configured in the render target. */
 218    intel_msaa_layout rt_layout;
 219
 220    /* Actual number of samples per pixel in the destination image. */
 221    unsigned dst_samples;
 222
 223    /* Actual MSAA layout used by the destination image. */
 224    intel_msaa_layout dst_layout;
 225
 226    /* Type of the data to be read from the texture (one of
 227     * BRW_REGISTER_TYPE_{UD,D,F}).
 228     */
 229    unsigned texture_data_type;
 230
 231    /* True if the source image is W tiled.  If true, the surface state for the
 232     * source image must be configured as Y tiled, and tex_samples must be 0.
 233     */
 234    bool src_tiled_w;
 235
 236    /* True if the destination image is W tiled.  If true, the surface state
 237     * for the render target must be configured as Y tiled, and rt_samples must
 238     * be 0.
 239     */
 240    bool dst_tiled_w;
 241
 242    /* True if all source samples should be blended together to produce each
 243     * destination pixel.  If true, src_tiled_w must be false, tex_samples must
 244     * equal src_samples, and tex_samples must be nonzero.
 245     */
 246    bool blend;
 247
 248    /* True if the rectangle being sent through the rendering pipeline might be
 249     * larger than the destination rectangle, so the WM program should kill any
 250     * pixels that are outside the destination rectangle.
 251     */
 252    bool use_kill;
 253
 254    /**
 255     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 256     * than one sample per pixel.
 257     */
 258    bool persample_msaa_dispatch;
 259 };
 260
 261 class brw_blorp_blit_params : public brw_blorp_params
 262 {
 263 public:
 264    brw_blorp_blit_params(struct brw_context *brw,
 265                          struct intel_mipmap_tree *src_mt,
 266                          struct intel_mipmap_tree *dst_mt,
 267                          GLuint src_x0, GLuint src_y0,
 268                          GLuint dst_x0, GLuint dst_y0,
 269                          GLuint width, GLuint height,
 270                          bool mirror_x, bool mirror_y);
 271
 272    virtual uint32_t get_wm_prog(struct brw_context *brw,
 273                                 brw_blorp_prog_data **prog_data) const;
 274
 275 private:
 276    brw_blorp_blit_prog_key wm_prog_key;
 277 };
 278
 279 /**
 280  * \name BLORP internals
 281  * \{
 282  *
 283  * Used internally by gen6_blorp_exec() and gen7_blorp_exec().
 284  */
 285
 286 void
 287 gen6_blorp_init(struct brw_context *brw);
 288
 289 void
 290 gen6_blorp_compute_tile_masks(const brw_blorp_params *params,
 291                               uint32_t *tile_mask_x, uint32_t *tile_mask_y);
 292
 293 void
 294 gen6_blorp_emit_batch_head(struct brw_context *brw,
 295                            const brw_blorp_params *params);
 296
 297 void
 298 gen6_blorp_emit_state_base_address(struct brw_context *brw,
 299                                    const brw_blorp_params *params);
 300
 301 void
 302 gen6_blorp_emit_vertices(struct brw_context *brw,
 303                          const brw_blorp_params *params);
 304
 305 uint32_t
 306 gen6_blorp_emit_blend_state(struct brw_context *brw,
 307                             const brw_blorp_params *params);
 308
 309 uint32_t
 310 gen6_blorp_emit_cc_state(struct brw_context *brw,
 311                          const brw_blorp_params *params);
 312
 313 uint32_t
 314 gen6_blorp_emit_wm_constants(struct brw_context *brw,
 315                              const brw_blorp_params *params);
 316
 317 void
 318 gen6_blorp_emit_vs_disable(struct brw_context *brw,
 319                            const brw_blorp_params *params);
 320
 321 uint32_t
 322 gen6_blorp_emit_binding_table(struct brw_context *brw,
 323                               const brw_blorp_params *params,
 324                               uint32_t wm_surf_offset_renderbuffer,
 325                               uint32_t wm_surf_offset_texture);
 326
 327 uint32_t
 328 gen6_blorp_emit_depth_stencil_state(struct brw_context *brw,
 329                                     const brw_blorp_params *params);
 330
 331 void
 332 gen6_blorp_emit_gs_disable(struct brw_context *brw,
 333                            const brw_blorp_params *params);
 334
 335 void
 336 gen6_blorp_emit_clip_disable(struct brw_context *brw,
 337                              const brw_blorp_params *params);
 338
 339 void
 340 gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
 341                                   const brw_blorp_params *params);
 342 /** \} */