2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_context.h"
30 #include "intel_mipmap_tree.h"
39 brw_blorp_blit_miptrees(struct brw_context
*brw
,
40 struct intel_mipmap_tree
*src_mt
,
41 unsigned src_level
, unsigned src_layer
,
42 mesa_format src_format
,
43 struct intel_mipmap_tree
*dst_mt
,
44 unsigned dst_level
, unsigned dst_layer
,
45 mesa_format dst_format
,
46 float src_x0
, float src_y0
,
47 float src_x1
, float src_y1
,
48 float dst_x0
, float dst_y0
,
49 float dst_x1
, float dst_y1
,
50 GLenum filter
, bool mirror_x
, bool mirror_y
);
53 } /* end extern "C" */
56 * Binding table indices used by BLORP.
59 BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
,
60 BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
,
61 BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
65 class brw_blorp_mip_info
70 void set(struct intel_mipmap_tree
*mt
,
71 unsigned int level
, unsigned int layer
);
73 struct intel_mipmap_tree
*mt
;
76 * The miplevel to use.
81 * The 2D layer within the miplevel. Combined, level and layer define the
82 * 2D miptree slice to use.
84 * Note: if mt is a 2D multisample array texture on Gen7+ using
85 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, layer is the physical
86 * layer holding sample 0. So, for example, if mt->num_samples == 4, then
87 * logical layer n corresponds to layer == 4*n.
92 * Width of the miplevel to be used. For surfaces using
93 * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
98 * Height of the miplevel to be used. For surfaces using
99 * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
104 * X offset within the surface to texture from (or render to). For
105 * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
111 * Y offset within the surface to texture from (or render to). For
112 * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
118 class brw_blorp_surface_info
: public brw_blorp_mip_info
121 brw_blorp_surface_info();
123 void set(struct brw_context
*brw
,
124 struct intel_mipmap_tree
*mt
,
125 unsigned int level
, unsigned int layer
,
126 mesa_format format
, bool is_render_target
);
128 uint32_t compute_tile_offsets(uint32_t *tile_x
, uint32_t *tile_y
) const;
130 /* Setting this flag indicates that the buffer's contents are W-tiled
131 * stencil data, but the surface state should be set up for Y tiled
132 * MESA_FORMAT_R_UNORM8 data (this is necessary because surface states don't
135 * Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of
136 * MESA_FORMAT_R_UNORM8 data are 128 pixels wide by 32 pixels high, the width and
137 * pitch stored in the surface state will be multiplied by 2, and the
138 * height will be halved. Also, since W and Y tiles store their data in a
139 * different order, the width and height will be rounded up to a multiple
140 * of the tile size, to ensure that the WM program can access the full
141 * width and height of the buffer.
143 bool map_stencil_as_y_tiled
;
145 unsigned num_samples
;
148 * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
149 * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
151 * If ALL_SLICES_AT_EACH_LOD is set, then ARYSPC_LOD0 can be used. Ignored
154 enum miptree_array_layout array_layout
;
157 * Format that should be used when setting up the surface state for this
158 * surface. Should correspond to one of the BRW_SURFACEFORMAT_* enums.
160 uint32_t brw_surfaceformat
;
163 * For MSAA surfaces, MSAA layout that should be used when setting up the
164 * surface state for this surface.
166 intel_msaa_layout msaa_layout
;
170 struct brw_blorp_coord_transform_params
172 void setup(GLfloat src0
, GLfloat src1
, GLfloat dst0
, GLfloat dst1
,
180 struct brw_blorp_wm_push_constants
186 /* Top right coordinates of the rectangular grid used for scaled blitting */
189 brw_blorp_coord_transform_params x_transform
;
190 brw_blorp_coord_transform_params y_transform
;
191 /* Pad out to an integral number of registers */
195 /* Every 32 bytes of push constant data constitutes one GEN register. */
196 const unsigned int BRW_BLORP_NUM_PUSH_CONST_REGS
=
197 sizeof(brw_blorp_wm_push_constants
) / 32;
199 struct brw_blorp_prog_data
201 unsigned int first_curbe_grf
;
204 * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
205 * than one sample per pixel.
207 bool persample_msaa_dispatch
;
211 class brw_blorp_params
214 brw_blorp_params(unsigned num_varyings
= 0,
215 unsigned num_draw_buffers
= 1,
216 unsigned num_layers
= 1);
218 virtual uint32_t get_wm_prog(struct brw_context
*brw
,
219 brw_blorp_prog_data
**prog_data
) const = 0;
225 brw_blorp_mip_info depth
;
226 uint32_t depth_format
;
227 brw_blorp_surface_info src
;
228 brw_blorp_surface_info dst
;
229 enum gen6_hiz_op hiz_op
;
231 brw_blorp_wm_push_constants wm_push_consts
;
232 const unsigned num_varyings
;
233 const unsigned num_draw_buffers
;
234 const unsigned num_layers
;
239 brw_blorp_exec(struct brw_context
*brw
, const brw_blorp_params
*params
);
243 * Parameters for a HiZ or depth resolve operation.
245 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
246 * PRM, Volume 1, Part 2:
247 * - 7.5.3.1 Depth Buffer Clear
248 * - 7.5.3.2 Depth Buffer Resolve
249 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
251 class brw_hiz_op_params
: public brw_blorp_params
254 brw_hiz_op_params(struct intel_mipmap_tree
*mt
,
255 unsigned int level
, unsigned int layer
,
258 virtual uint32_t get_wm_prog(struct brw_context
*brw
,
259 brw_blorp_prog_data
**prog_data
) const;
262 struct brw_blorp_blit_prog_key
264 /* Number of samples per pixel that have been configured in the surface
265 * state for texturing from.
267 unsigned tex_samples
;
269 /* MSAA layout that has been configured in the surface state for texturing
272 intel_msaa_layout tex_layout
;
274 /* Actual number of samples per pixel in the source image. */
275 unsigned src_samples
;
277 /* Actual MSAA layout used by the source image. */
278 intel_msaa_layout src_layout
;
280 /* Number of samples per pixel that have been configured in the render
285 /* MSAA layout that has been configured in the render target. */
286 intel_msaa_layout rt_layout
;
288 /* Actual number of samples per pixel in the destination image. */
289 unsigned dst_samples
;
291 /* Actual MSAA layout used by the destination image. */
292 intel_msaa_layout dst_layout
;
294 /* Type of the data to be read from the texture (one of
295 * BRW_REGISTER_TYPE_{UD,D,F}).
297 enum brw_reg_type texture_data_type
;
299 /* True if the source image is W tiled. If true, the surface state for the
300 * source image must be configured as Y tiled, and tex_samples must be 0.
304 /* True if the destination image is W tiled. If true, the surface state
305 * for the render target must be configured as Y tiled, and rt_samples must
310 /* True if all source samples should be blended together to produce each
311 * destination pixel. If true, src_tiled_w must be false, tex_samples must
312 * equal src_samples, and tex_samples must be nonzero.
316 /* True if the rectangle being sent through the rendering pipeline might be
317 * larger than the destination rectangle, so the WM program should kill any
318 * pixels that are outside the destination rectangle.
323 * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
324 * than one sample per pixel.
326 bool persample_msaa_dispatch
;
328 /* True for scaled blitting. */
331 /* Scale factors between the pixel grid and the grid of samples. We're
332 * using grid of samples for bilinear filetring in multisample scaled blits.
337 /* True for blits with filter = GL_LINEAR. */
338 bool bilinear_filter
;
341 class brw_blorp_blit_params
: public brw_blorp_params
344 brw_blorp_blit_params(struct brw_context
*brw
,
345 struct intel_mipmap_tree
*src_mt
,
346 unsigned src_level
, unsigned src_layer
,
347 mesa_format src_format
,
348 struct intel_mipmap_tree
*dst_mt
,
349 unsigned dst_level
, unsigned dst_layer
,
350 mesa_format dst_format
,
351 GLfloat src_x0
, GLfloat src_y0
,
352 GLfloat src_x1
, GLfloat src_y1
,
353 GLfloat dst_x0
, GLfloat dst_y0
,
354 GLfloat dst_x1
, GLfloat dst_y1
,
355 GLenum filter
, bool mirror_x
, bool mirror_y
);
357 virtual uint32_t get_wm_prog(struct brw_context
*brw
,
358 brw_blorp_prog_data
**prog_data
) const;
361 brw_blorp_blit_prog_key wm_prog_key
;
365 * \name BLORP internals
368 * Used internally by gen6_blorp_exec() and gen7_blorp_exec().
372 gen6_blorp_init(struct brw_context
*brw
);
375 gen6_blorp_emit_state_base_address(struct brw_context
*brw
,
376 const brw_blorp_params
*params
);
379 gen6_blorp_emit_vertices(struct brw_context
*brw
,
380 const brw_blorp_params
*params
);
383 gen6_blorp_emit_blend_state(struct brw_context
*brw
,
384 const brw_blorp_params
*params
);
387 gen6_blorp_emit_cc_state(struct brw_context
*brw
);
390 gen6_blorp_emit_wm_constants(struct brw_context
*brw
,
391 const brw_blorp_params
*params
);
394 gen6_blorp_emit_vs_disable(struct brw_context
*brw
,
395 const brw_blorp_params
*params
);
398 gen6_blorp_emit_binding_table(struct brw_context
*brw
,
399 uint32_t wm_surf_offset_renderbuffer
,
400 uint32_t wm_surf_offset_texture
);
403 gen6_blorp_emit_depth_stencil_state(struct brw_context
*brw
,
404 const brw_blorp_params
*params
);
407 gen6_blorp_emit_gs_disable(struct brw_context
*brw
,
408 const brw_blorp_params
*params
);
411 gen6_blorp_emit_clip_disable(struct brw_context
*brw
);
414 gen6_blorp_emit_drawing_rectangle(struct brw_context
*brw
,
415 const brw_blorp_params
*params
);
418 gen6_blorp_emit_sampler_state(struct brw_context
*brw
,
419 unsigned tex_filter
, unsigned max_lod
,
420 bool non_normalized_coords
);
424 #endif /* __cplusplus */