2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "intel_mipmap_tree.h"
38 brw_blorp_blit_miptrees(struct brw_context
*brw
,
39 struct intel_mipmap_tree
*src_mt
,
40 unsigned src_level
, unsigned src_layer
,
41 mesa_format src_format
, int src_swizzle
,
42 struct intel_mipmap_tree
*dst_mt
,
43 unsigned dst_level
, unsigned dst_layer
,
44 mesa_format dst_format
,
45 float src_x0
, float src_y0
,
46 float src_x1
, float src_y1
,
47 float dst_x0
, float dst_y0
,
48 float dst_x1
, float dst_y1
,
49 GLenum filter
, bool mirror_x
, bool mirror_y
,
50 bool decode_srgb
, bool encode_srgb
);
53 brw_blorp_clear_color(struct brw_context
*brw
, struct gl_framebuffer
*fb
,
54 GLbitfield mask
, bool partial_clear
, bool encode_srgb
);
57 brw_blorp_resolve_color(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
);
61 * Binding table indices used by BLORP.
64 BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
,
65 BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
,
66 BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
69 struct brw_blorp_surface_info
71 struct intel_mipmap_tree
*mt
;
74 * The miplevel to use.
79 * The 2D layer within the miplevel. Combined, level and layer define the
80 * 2D miptree slice to use.
82 * Note: if mt is a 2D multisample array texture on Gen7+ using
83 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, layer is the physical
84 * layer holding sample 0. So, for example, if mt->num_samples == 4, then
85 * logical layer n corresponds to layer == 4*n.
90 * Width of the miplevel to be used. For surfaces using
91 * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
96 * Height of the miplevel to be used. For surfaces using
97 * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
102 * X offset within the surface to texture from (or render to). For
103 * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
109 * Y offset within the surface to texture from (or render to). For
110 * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
115 /* Setting this flag indicates that the buffer's contents are W-tiled
116 * stencil data, but the surface state should be set up for Y tiled
117 * MESA_FORMAT_R_UNORM8 data (this is necessary because surface states don't
120 * Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of
121 * MESA_FORMAT_R_UNORM8 data are 128 pixels wide by 32 pixels high, the width and
122 * pitch stored in the surface state will be multiplied by 2, and the
123 * height will be halved. Also, since W and Y tiles store their data in a
124 * different order, the width and height will be rounded up to a multiple
125 * of the tile size, to ensure that the WM program can access the full
126 * width and height of the buffer.
128 bool map_stencil_as_y_tiled
;
130 unsigned num_samples
;
133 * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
134 * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
136 * If ALL_SLICES_AT_EACH_LOD is set, then ARYSPC_LOD0 can be used. Ignored
139 enum miptree_array_layout array_layout
;
142 * Format that should be used when setting up the surface state for this
143 * surface. Should correspond to one of the BRW_SURFACEFORMAT_* enums.
145 uint32_t brw_surfaceformat
;
148 * For MSAA surfaces, MSAA layout that should be used when setting up the
149 * surface state for this surface.
151 enum intel_msaa_layout msaa_layout
;
154 * In order to support cases where RGBA format is backing client requested
155 * RGB, one needs to have means to force alpha channel to one when user
156 * requested RGB surface is used as blit source. This is possible by
157 * setting source swizzle for the texture surface.
163 brw_blorp_surface_info_init(struct brw_context
*brw
,
164 struct brw_blorp_surface_info
*info
,
165 struct intel_mipmap_tree
*mt
,
166 unsigned int level
, unsigned int layer
,
167 mesa_format format
, bool is_render_target
);
170 brw_blorp_compute_tile_offsets(const struct brw_blorp_surface_info
*info
,
171 uint32_t *tile_x
, uint32_t *tile_y
);
175 struct brw_blorp_coord_transform
181 struct brw_blorp_wm_push_constants
187 /* Top right coordinates of the rectangular grid used for scaled blitting */
190 struct brw_blorp_coord_transform x_transform
;
191 struct brw_blorp_coord_transform y_transform
;
193 /* Minimum layer setting works for all the textures types but texture_3d
194 * for which the setting has no effect. Use the z-coordinate instead.
198 /* Pad out to an integral number of registers */
202 #define BRW_BLORP_NUM_PUSH_CONSTANT_DWORDS \
203 (sizeof(struct brw_blorp_wm_push_constants) / 4)
205 /* Every 32 bytes of push constant data constitutes one GEN register. */
206 static const unsigned int BRW_BLORP_NUM_PUSH_CONST_REGS
=
207 sizeof(struct brw_blorp_wm_push_constants
) / 32;
209 struct brw_blorp_prog_data
214 uint8_t first_curbe_grf_0
;
215 uint8_t first_curbe_grf_2
;
217 uint32_t ksp_offset_2
;
220 * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
221 * than one sample per pixel.
223 bool persample_msaa_dispatch
;
225 /* The compiler will re-arrange push constants and store the upload order
226 * here. Given an index 'i' in the final upload buffer, param[i] gives the
227 * index in the uniform store. In other words, the value to be uploaded can
228 * be found by brw_blorp_params::wm_push_consts[param[i]].
231 uint8_t param
[BRW_BLORP_NUM_PUSH_CONSTANT_DWORDS
];
234 void brw_blorp_prog_data_init(struct brw_blorp_prog_data
*prog_data
);
236 struct brw_blorp_params
242 struct brw_blorp_surface_info depth
;
243 uint32_t depth_format
;
244 struct brw_blorp_surface_info src
;
245 struct brw_blorp_surface_info dst
;
246 enum gen6_hiz_op hiz_op
;
248 unsigned fast_clear_op
;
249 unsigned resolve_type
;
251 bool color_write_disable
[4];
252 struct brw_blorp_wm_push_constants wm_push_consts
;
253 unsigned num_varyings
;
254 unsigned num_draw_buffers
;
256 uint32_t wm_prog_kernel
;
257 struct brw_blorp_prog_data
*wm_prog_data
;
261 brw_blorp_params_init(struct brw_blorp_params
*params
);
264 brw_blorp_exec(struct brw_context
*brw
, const struct brw_blorp_params
*params
);
267 gen6_blorp_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
268 unsigned level
, unsigned layer
, enum gen6_hiz_op op
);
271 gen6_blorp_exec(struct brw_context
*brw
,
272 const struct brw_blorp_params
*params
);
275 gen7_blorp_exec(struct brw_context
*brw
,
276 const struct brw_blorp_params
*params
);
279 gen8_blorp_exec(struct brw_context
*brw
, const struct brw_blorp_params
*params
);
281 struct brw_blorp_blit_prog_key
283 /* Number of samples per pixel that have been configured in the surface
284 * state for texturing from.
286 unsigned tex_samples
;
288 /* MSAA layout that has been configured in the surface state for texturing
291 enum intel_msaa_layout tex_layout
;
293 /* Actual number of samples per pixel in the source image. */
294 unsigned src_samples
;
296 /* Actual MSAA layout used by the source image. */
297 enum intel_msaa_layout src_layout
;
299 /* Number of samples per pixel that have been configured in the render
304 /* MSAA layout that has been configured in the render target. */
305 enum intel_msaa_layout rt_layout
;
307 /* Actual number of samples per pixel in the destination image. */
308 unsigned dst_samples
;
310 /* Actual MSAA layout used by the destination image. */
311 enum intel_msaa_layout dst_layout
;
313 /* Type of the data to be read from the texture (one of
314 * BRW_REGISTER_TYPE_{UD,D,F}).
316 enum brw_reg_type texture_data_type
;
318 /* True if the source image is W tiled. If true, the surface state for the
319 * source image must be configured as Y tiled, and tex_samples must be 0.
323 /* True if the destination image is W tiled. If true, the surface state
324 * for the render target must be configured as Y tiled, and rt_samples must
329 /* True if all source samples should be blended together to produce each
330 * destination pixel. If true, src_tiled_w must be false, tex_samples must
331 * equal src_samples, and tex_samples must be nonzero.
335 /* True if the rectangle being sent through the rendering pipeline might be
336 * larger than the destination rectangle, so the WM program should kill any
337 * pixels that are outside the destination rectangle.
342 * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
343 * than one sample per pixel.
345 bool persample_msaa_dispatch
;
347 /* True for scaled blitting. */
350 /* Scale factors between the pixel grid and the grid of samples. We're
351 * using grid of samples for bilinear filetring in multisample scaled blits.
356 /* True for blits with filter = GL_LINEAR. */
357 bool bilinear_filter
;
361 * \name BLORP internals
364 * Used internally by gen6_blorp_exec() and gen7_blorp_exec().
368 gen6_blorp_init(struct brw_context
*brw
);
371 gen6_blorp_emit_vertices(struct brw_context
*brw
,
372 const struct brw_blorp_params
*params
);
375 gen6_blorp_emit_blend_state(struct brw_context
*brw
,
376 const struct brw_blorp_params
*params
);
379 gen6_blorp_emit_cc_state(struct brw_context
*brw
);
382 gen6_blorp_emit_wm_constants(struct brw_context
*brw
,
383 const struct brw_blorp_params
*params
);
386 gen6_blorp_emit_vs_disable(struct brw_context
*brw
,
387 const struct brw_blorp_params
*params
);
390 gen6_blorp_emit_binding_table(struct brw_context
*brw
,
391 uint32_t wm_surf_offset_renderbuffer
,
392 uint32_t wm_surf_offset_texture
);
395 gen6_blorp_emit_depth_stencil_state(struct brw_context
*brw
,
396 const struct brw_blorp_params
*params
);
399 gen6_blorp_emit_gs_disable(struct brw_context
*brw
,
400 const struct brw_blorp_params
*params
);
403 gen6_blorp_emit_clip_disable(struct brw_context
*brw
);
406 gen6_blorp_emit_drawing_rectangle(struct brw_context
*brw
,
407 const struct brw_blorp_params
*params
);
410 gen6_blorp_emit_sampler_state(struct brw_context
*brw
,
411 unsigned tex_filter
, unsigned max_lod
,
412 bool non_normalized_coords
);
414 gen7_blorp_emit_urb_config(struct brw_context
*brw
);
417 gen7_blorp_emit_blend_state_pointer(struct brw_context
*brw
,
418 uint32_t cc_blend_state_offset
);
421 gen7_blorp_emit_cc_state_pointer(struct brw_context
*brw
,
422 uint32_t cc_state_offset
);
425 gen7_blorp_emit_cc_viewport(struct brw_context
*brw
);
428 gen7_blorp_emit_te_disable(struct brw_context
*brw
);
431 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context
*brw
,
432 uint32_t wm_bind_bo_offset
);
435 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context
*brw
,
436 uint32_t sampler_offset
);
439 gen7_blorp_emit_clear_params(struct brw_context
*brw
,
440 const struct brw_blorp_params
*params
);
443 gen7_blorp_emit_constant_ps(struct brw_context
*brw
,
444 uint32_t wm_push_const_offset
);
447 gen7_blorp_emit_constant_ps_disable(struct brw_context
*brw
);
450 gen7_blorp_emit_primitive(struct brw_context
*brw
,
451 const struct brw_blorp_params
*params
);
456 } /* end extern "C" */
457 #endif /* __cplusplus */