src/mesa/drivers/dri/i965/brw_blorp.h

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #pragma once
  25
  26 #include <stdint.h>
  27
  28 #include "brw_context.h"
  29 #include "intel_mipmap_tree.h"
  30
  31 struct brw_context;
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 void
  38 brw_blorp_blit_miptrees(struct intel_context *intel,
  39                         struct intel_mipmap_tree *src_mt,
  40                         unsigned src_level, unsigned src_layer,
  41                         struct intel_mipmap_tree *dst_mt,
  42                         unsigned dst_level, unsigned dst_layer,
  43                         float src_x0, float src_y0,
  44                         float src_x1, float src_y1,
  45                         float dst_x0, float dst_y0,
  46                         float dst_x1, float dst_y1,
  47                         bool mirror_x, bool mirror_y);
  48
  49 bool
  50 brw_blorp_clear_color(struct intel_context *intel, struct gl_framebuffer *fb,
  51                       bool partial_clear);
  52
  53 void
  54 brw_blorp_resolve_color(struct intel_context *intel,
  55                         struct intel_mipmap_tree *mt);
  56
  57 #ifdef __cplusplus
  58 } /* end extern "C" */
  59
  60 /**
  61  * Binding table indices used by BLORP.
  62  */
  63 enum {
  64    BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX,
  65    BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
  66    BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
  67 };
  68
  69
  70 class brw_blorp_mip_info
  71 {
  72 public:
  73    brw_blorp_mip_info();
  74
  75    void set(struct intel_mipmap_tree *mt,
  76             unsigned int level, unsigned int layer);
  77
  78    struct intel_mipmap_tree *mt;
  79
  80    /**
  81     * The miplevel to use.
  82     */
  83    uint32_t level;
  84
  85    /**
  86     * The 2D layer within the miplevel. Combined, level and layer define the
  87     * 2D miptree slice to use.
  88     */
  89    uint32_t layer;
  90
  91    /**
  92     * Width of the miplevel to be used.  For surfaces using
  93     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
  94     */
  95    uint32_t width;
  96
  97    /**
  98     * Height of the miplevel to be used.  For surfaces using
  99     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
 100     */
 101    uint32_t height;
 102
 103    /**
 104     * X offset within the surface to texture from (or render to).  For
 105     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
 106     * pixels.
 107     */
 108    uint32_t x_offset;
 109
 110    /**
 111     * Y offset within the surface to texture from (or render to).  For
 112     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
 113     * pixels.
 114     */
 115    uint32_t y_offset;
 116 };
 117
 118 class brw_blorp_surface_info : public brw_blorp_mip_info
 119 {
 120 public:
 121    brw_blorp_surface_info();
 122
 123    void set(struct brw_context *brw,
 124             struct intel_mipmap_tree *mt,
 125             unsigned int level, unsigned int layer);
 126
 127    uint32_t compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const;
 128
 129    /* Setting this flag indicates that the buffer's contents are W-tiled
 130     * stencil data, but the surface state should be set up for Y tiled
 131     * MESA_FORMAT_R8 data (this is necessary because surface states don't
 132     * support W tiling).
 133     *
 134     * Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of
 135     * MESA_FORMAT_R8 data are 128 pixels wide by 32 pixels high, the width and
 136     * pitch stored in the surface state will be multiplied by 2, and the
 137     * height will be halved.  Also, since W and Y tiles store their data in a
 138     * different order, the width and height will be rounded up to a multiple
 139     * of the tile size, to ensure that the WM program can access the full
 140     * width and height of the buffer.
 141     */
 142    bool map_stencil_as_y_tiled;
 143
 144    unsigned num_samples;
 145
 146    /* Setting this flag indicates that the surface should be set up in
 147     * ARYSPC_LOD0 mode.  Ignored prior to Gen7.
 148     */
 149    bool array_spacing_lod0;
 150
 151    /**
 152     * Format that should be used when setting up the surface state for this
 153     * surface.  Should correspond to one of the BRW_SURFACEFORMAT_* enums.
 154     */
 155    uint32_t brw_surfaceformat;
 156
 157    /**
 158     * For MSAA surfaces, MSAA layout that should be used when setting up the
 159     * surface state for this surface.
 160     */
 161    intel_msaa_layout msaa_layout;
 162 };
 163
 164
 165 struct brw_blorp_coord_transform_params
 166 {
 167    void setup(GLfloat src0, GLfloat src1, GLfloat dst0, GLfloat dst1,
 168               bool mirror);
 169
 170    float multiplier;
 171    float offset;
 172 };
 173
 174
 175 struct brw_blorp_wm_push_constants
 176 {
 177    uint32_t dst_x0;
 178    uint32_t dst_x1;
 179    uint32_t dst_y0;
 180    uint32_t dst_y1;
 181    brw_blorp_coord_transform_params x_transform;
 182    brw_blorp_coord_transform_params y_transform;
 183 };
 184
 185 /* Every 32 bytes of push constant data constitutes one GEN register. */
 186 const unsigned int BRW_BLORP_NUM_PUSH_CONST_REGS =
 187    sizeof(brw_blorp_wm_push_constants) / 32;
 188
 189 struct brw_blorp_prog_data
 190 {
 191    unsigned int first_curbe_grf;
 192
 193    /**
 194     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 195     * than one sample per pixel.
 196     */
 197    bool persample_msaa_dispatch;
 198 };
 199
 200
 201 enum gen7_fast_clear_op {
 202    GEN7_FAST_CLEAR_OP_NONE,
 203    GEN7_FAST_CLEAR_OP_FAST_CLEAR,
 204    GEN7_FAST_CLEAR_OP_RESOLVE,
 205 };
 206
 207
 208 class brw_blorp_params
 209 {
 210 public:
 211    brw_blorp_params();
 212
 213    virtual uint32_t get_wm_prog(struct brw_context *brw,
 214                                 brw_blorp_prog_data **prog_data) const = 0;
 215
 216    uint32_t x0;
 217    uint32_t y0;
 218    uint32_t x1;
 219    uint32_t y1;
 220    brw_blorp_mip_info depth;
 221    uint32_t depth_format;
 222    brw_blorp_surface_info src;
 223    brw_blorp_surface_info dst;
 224    enum gen6_hiz_op hiz_op;
 225    enum gen7_fast_clear_op fast_clear_op;
 226    unsigned num_samples;
 227    bool use_wm_prog;
 228    brw_blorp_wm_push_constants wm_push_consts;
 229    bool color_write_disable[4];
 230 };
 231
 232
 233 void
 234 brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params);
 235
 236
 237 /**
 238  * Parameters for a HiZ or depth resolve operation.
 239  *
 240  * For an overview of HiZ ops, see the following sections of the Sandy Bridge
 241  * PRM, Volume 1, Part 2:
 242  *   - 7.5.3.1 Depth Buffer Clear
 243  *   - 7.5.3.2 Depth Buffer Resolve
 244  *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
 245  */
 246 class brw_hiz_op_params : public brw_blorp_params
 247 {
 248 public:
 249    brw_hiz_op_params(struct intel_mipmap_tree *mt,
 250                      unsigned int level, unsigned int layer,
 251                      gen6_hiz_op op);
 252
 253    virtual uint32_t get_wm_prog(struct brw_context *brw,
 254                                 brw_blorp_prog_data **prog_data) const;
 255 };
 256
 257 struct brw_blorp_blit_prog_key
 258 {
 259    /* Number of samples per pixel that have been configured in the surface
 260     * state for texturing from.
 261     */
 262    unsigned tex_samples;
 263
 264    /* MSAA layout that has been configured in the surface state for texturing
 265     * from.
 266     */
 267    intel_msaa_layout tex_layout;
 268
 269    /* Actual number of samples per pixel in the source image. */
 270    unsigned src_samples;
 271
 272    /* Actual MSAA layout used by the source image. */
 273    intel_msaa_layout src_layout;
 274
 275    /* Number of samples per pixel that have been configured in the render
 276     * target.
 277     */
 278    unsigned rt_samples;
 279
 280    /* MSAA layout that has been configured in the render target. */
 281    intel_msaa_layout rt_layout;
 282
 283    /* Actual number of samples per pixel in the destination image. */
 284    unsigned dst_samples;
 285
 286    /* Actual MSAA layout used by the destination image. */
 287    intel_msaa_layout dst_layout;
 288
 289    /* Type of the data to be read from the texture (one of
 290     * BRW_REGISTER_TYPE_{UD,D,F}).
 291     */
 292    unsigned texture_data_type;
 293
 294    /* True if the source image is W tiled.  If true, the surface state for the
 295     * source image must be configured as Y tiled, and tex_samples must be 0.
 296     */
 297    bool src_tiled_w;
 298
 299    /* True if the destination image is W tiled.  If true, the surface state
 300     * for the render target must be configured as Y tiled, and rt_samples must
 301     * be 0.
 302     */
 303    bool dst_tiled_w;
 304
 305    /* True if all source samples should be blended together to produce each
 306     * destination pixel.  If true, src_tiled_w must be false, tex_samples must
 307     * equal src_samples, and tex_samples must be nonzero.
 308     */
 309    bool blend;
 310
 311    /* True if the rectangle being sent through the rendering pipeline might be
 312     * larger than the destination rectangle, so the WM program should kill any
 313     * pixels that are outside the destination rectangle.
 314     */
 315    bool use_kill;
 316
 317    /**
 318     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 319     * than one sample per pixel.
 320     */
 321    bool persample_msaa_dispatch;
 322 };
 323
 324 class brw_blorp_blit_params : public brw_blorp_params
 325 {
 326 public:
 327    brw_blorp_blit_params(struct brw_context *brw,
 328                          struct intel_mipmap_tree *src_mt,
 329                          unsigned src_level, unsigned src_layer,
 330                          struct intel_mipmap_tree *dst_mt,
 331                          unsigned dst_level, unsigned dst_layer,
 332                          GLfloat src_x0, GLfloat src_y0,
 333                          GLfloat src_x1, GLfloat src_y1,
 334                          GLfloat dst_x0, GLfloat dst_y0,
 335                          GLfloat dst_x1, GLfloat dst_y1,
 336                          bool mirror_x, bool mirror_y);
 337
 338    virtual uint32_t get_wm_prog(struct brw_context *brw,
 339                                 brw_blorp_prog_data **prog_data) const;
 340
 341 private:
 342    brw_blorp_blit_prog_key wm_prog_key;
 343 };
 344
 345 /**
 346  * \name BLORP internals
 347  * \{
 348  *
 349  * Used internally by gen6_blorp_exec() and gen7_blorp_exec().
 350  */
 351
 352 void
 353 gen6_blorp_init(struct brw_context *brw);
 354
 355 void
 356 gen6_blorp_emit_batch_head(struct brw_context *brw,
 357                            const brw_blorp_params *params);
 358
 359 void
 360 gen6_blorp_emit_state_base_address(struct brw_context *brw,
 361                                    const brw_blorp_params *params);
 362
 363 void
 364 gen6_blorp_emit_vertices(struct brw_context *brw,
 365                          const brw_blorp_params *params);
 366
 367 uint32_t
 368 gen6_blorp_emit_blend_state(struct brw_context *brw,
 369                             const brw_blorp_params *params);
 370
 371 uint32_t
 372 gen6_blorp_emit_cc_state(struct brw_context *brw,
 373                          const brw_blorp_params *params);
 374
 375 uint32_t
 376 gen6_blorp_emit_wm_constants(struct brw_context *brw,
 377                              const brw_blorp_params *params);
 378
 379 void
 380 gen6_blorp_emit_vs_disable(struct brw_context *brw,
 381                            const brw_blorp_params *params);
 382
 383 uint32_t
 384 gen6_blorp_emit_binding_table(struct brw_context *brw,
 385                               const brw_blorp_params *params,
 386                               uint32_t wm_surf_offset_renderbuffer,
 387                               uint32_t wm_surf_offset_texture);
 388
 389 uint32_t
 390 gen6_blorp_emit_depth_stencil_state(struct brw_context *brw,
 391                                     const brw_blorp_params *params);
 392
 393 void
 394 gen6_blorp_emit_gs_disable(struct brw_context *brw,
 395                            const brw_blorp_params *params);
 396
 397 void
 398 gen6_blorp_emit_clip_disable(struct brw_context *brw,
 399                              const brw_blorp_params *params);
 400
 401 void
 402 gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
 403                                   const brw_blorp_params *params);
 404 /** \} */
 405
 406 #endif /* __cplusplus */