src/mesa/drivers/dri/i965/brw_blorp.h

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #pragma once
  25
  26 #include <stdint.h>
  27
  28 #include "brw_context.h"
  29 #include "intel_mipmap_tree.h"
  30
  31 struct brw_context;
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 void
  38 brw_blorp_blit_miptrees(struct intel_context *intel,
  39                         struct intel_mipmap_tree *src_mt,
  40                         unsigned src_level, unsigned src_layer,
  41                         struct intel_mipmap_tree *dst_mt,
  42                         unsigned dst_level, unsigned dst_layer,
  43                         int src_x0, int src_y0,
  44                         int dst_x0, int dst_y0,
  45                         int dst_x1, int dst_y1,
  46                         bool mirror_x, bool mirror_y);
  47
  48 #ifdef __cplusplus
  49 } /* end extern "C" */
  50
  51 /**
  52  * Binding table indices used by BLORP.
  53  */
  54 enum {
  55    BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX,
  56    BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
  57    BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
  58 };
  59
  60
  61 class brw_blorp_mip_info
  62 {
  63 public:
  64    brw_blorp_mip_info();
  65
  66    void set(struct intel_mipmap_tree *mt,
  67             unsigned int level, unsigned int layer);
  68
  69    struct intel_mipmap_tree *mt;
  70
  71    /**
  72     * Width of the miplevel to be used.  For surfaces using
  73     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
  74     */
  75    uint32_t width;
  76
  77    /**
  78     * Height of the miplevel to be used.  For surfaces using
  79     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
  80     */
  81    uint32_t height;
  82
  83    /**
  84     * X offset within the surface to texture from (or render to).  For
  85     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
  86     * pixels.
  87     */
  88    uint32_t x_offset;
  89
  90    /**
  91     * Y offset within the surface to texture from (or render to).  For
  92     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
  93     * pixels.
  94     */
  95    uint32_t y_offset;
  96 };
  97
  98 class brw_blorp_surface_info : public brw_blorp_mip_info
  99 {
 100 public:
 101    brw_blorp_surface_info();
 102
 103    void set(struct brw_context *brw,
 104             struct intel_mipmap_tree *mt,
 105             unsigned int level, unsigned int layer);
 106
 107    uint32_t compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const;
 108
 109    /* Setting this flag indicates that the buffer's contents are W-tiled
 110     * stencil data, but the surface state should be set up for Y tiled
 111     * MESA_FORMAT_R8 data (this is necessary because surface states don't
 112     * support W tiling).
 113     *
 114     * Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of
 115     * MESA_FORMAT_R8 data are 128 pixels wide by 32 pixels high, the width and
 116     * pitch stored in the surface state will be multiplied by 2, and the
 117     * height will be halved.  Also, since W and Y tiles store their data in a
 118     * different order, the width and height will be rounded up to a multiple
 119     * of the tile size, to ensure that the WM program can access the full
 120     * width and height of the buffer.
 121     */
 122    bool map_stencil_as_y_tiled;
 123
 124    unsigned num_samples;
 125
 126    /* Setting this flag indicates that the surface should be set up in
 127     * ARYSPC_LOD0 mode.  Ignored prior to Gen7.
 128     */
 129    bool array_spacing_lod0;
 130
 131    /**
 132     * Format that should be used when setting up the surface state for this
 133     * surface.  Should correspond to one of the BRW_SURFACEFORMAT_* enums.
 134     */
 135    uint32_t brw_surfaceformat;
 136
 137    /**
 138     * For MSAA surfaces, MSAA layout that should be used when setting up the
 139     * surface state for this surface.
 140     */
 141    intel_msaa_layout msaa_layout;
 142 };
 143
 144
 145 struct brw_blorp_coord_transform_params
 146 {
 147    void setup(GLuint src0, GLuint dst0, GLuint dst1,
 148               bool mirror);
 149
 150    int16_t multiplier;
 151    int16_t offset;
 152 };
 153
 154
 155 struct brw_blorp_wm_push_constants
 156 {
 157    uint16_t dst_x0;
 158    uint16_t dst_x1;
 159    uint16_t dst_y0;
 160    uint16_t dst_y1;
 161    brw_blorp_coord_transform_params x_transform;
 162    brw_blorp_coord_transform_params y_transform;
 163
 164    /* Pad out to an integral number of registers */
 165    uint16_t pad[8];
 166 };
 167
 168 /* Every 32 bytes of push constant data constitutes one GEN register. */
 169 const unsigned int BRW_BLORP_NUM_PUSH_CONST_REGS =
 170    sizeof(brw_blorp_wm_push_constants) / 32;
 171
 172 struct brw_blorp_prog_data
 173 {
 174    unsigned int first_curbe_grf;
 175
 176    /**
 177     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 178     * than one sample per pixel.
 179     */
 180    bool persample_msaa_dispatch;
 181 };
 182
 183 class brw_blorp_params
 184 {
 185 public:
 186    brw_blorp_params();
 187
 188    virtual uint32_t get_wm_prog(struct brw_context *brw,
 189                                 brw_blorp_prog_data **prog_data) const = 0;
 190
 191    uint32_t x0;
 192    uint32_t y0;
 193    uint32_t x1;
 194    uint32_t y1;
 195    brw_blorp_mip_info depth;
 196    uint32_t depth_format;
 197    brw_blorp_surface_info src;
 198    brw_blorp_surface_info dst;
 199    enum gen6_hiz_op hiz_op;
 200    unsigned num_samples;
 201    bool use_wm_prog;
 202    brw_blorp_wm_push_constants wm_push_consts;
 203 };
 204
 205
 206 void
 207 brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params);
 208
 209
 210 /**
 211  * Parameters for a HiZ or depth resolve operation.
 212  *
 213  * For an overview of HiZ ops, see the following sections of the Sandy Bridge
 214  * PRM, Volume 1, Part 2:
 215  *   - 7.5.3.1 Depth Buffer Clear
 216  *   - 7.5.3.2 Depth Buffer Resolve
 217  *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
 218  */
 219 class brw_hiz_op_params : public brw_blorp_params
 220 {
 221 public:
 222    brw_hiz_op_params(struct intel_mipmap_tree *mt,
 223                      unsigned int level, unsigned int layer,
 224                      gen6_hiz_op op);
 225
 226    virtual uint32_t get_wm_prog(struct brw_context *brw,
 227                                 brw_blorp_prog_data **prog_data) const;
 228 };
 229
 230 struct brw_blorp_blit_prog_key
 231 {
 232    /* Number of samples per pixel that have been configured in the surface
 233     * state for texturing from.
 234     */
 235    unsigned tex_samples;
 236
 237    /* MSAA layout that has been configured in the surface state for texturing
 238     * from.
 239     */
 240    intel_msaa_layout tex_layout;
 241
 242    /* Actual number of samples per pixel in the source image. */
 243    unsigned src_samples;
 244
 245    /* Actual MSAA layout used by the source image. */
 246    intel_msaa_layout src_layout;
 247
 248    /* Number of samples per pixel that have been configured in the render
 249     * target.
 250     */
 251    unsigned rt_samples;
 252
 253    /* MSAA layout that has been configured in the render target. */
 254    intel_msaa_layout rt_layout;
 255
 256    /* Actual number of samples per pixel in the destination image. */
 257    unsigned dst_samples;
 258
 259    /* Actual MSAA layout used by the destination image. */
 260    intel_msaa_layout dst_layout;
 261
 262    /* Type of the data to be read from the texture (one of
 263     * BRW_REGISTER_TYPE_{UD,D,F}).
 264     */
 265    unsigned texture_data_type;
 266
 267    /* True if the source image is W tiled.  If true, the surface state for the
 268     * source image must be configured as Y tiled, and tex_samples must be 0.
 269     */
 270    bool src_tiled_w;
 271
 272    /* True if the destination image is W tiled.  If true, the surface state
 273     * for the render target must be configured as Y tiled, and rt_samples must
 274     * be 0.
 275     */
 276    bool dst_tiled_w;
 277
 278    /* True if all source samples should be blended together to produce each
 279     * destination pixel.  If true, src_tiled_w must be false, tex_samples must
 280     * equal src_samples, and tex_samples must be nonzero.
 281     */
 282    bool blend;
 283
 284    /* True if the rectangle being sent through the rendering pipeline might be
 285     * larger than the destination rectangle, so the WM program should kill any
 286     * pixels that are outside the destination rectangle.
 287     */
 288    bool use_kill;
 289
 290    /**
 291     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 292     * than one sample per pixel.
 293     */
 294    bool persample_msaa_dispatch;
 295 };
 296
 297 class brw_blorp_blit_params : public brw_blorp_params
 298 {
 299 public:
 300    brw_blorp_blit_params(struct brw_context *brw,
 301                          struct intel_mipmap_tree *src_mt,
 302                          unsigned src_level, unsigned src_layer,
 303                          struct intel_mipmap_tree *dst_mt,
 304                          unsigned dst_level, unsigned dst_layer,
 305                          GLuint src_x0, GLuint src_y0,
 306                          GLuint dst_x0, GLuint dst_y0,
 307                          GLuint width, GLuint height,
 308                          bool mirror_x, bool mirror_y);
 309
 310    virtual uint32_t get_wm_prog(struct brw_context *brw,
 311                                 brw_blorp_prog_data **prog_data) const;
 312
 313 private:
 314    brw_blorp_blit_prog_key wm_prog_key;
 315 };
 316
 317 /**
 318  * \name BLORP internals
 319  * \{
 320  *
 321  * Used internally by gen6_blorp_exec() and gen7_blorp_exec().
 322  */
 323
 324 void
 325 gen6_blorp_init(struct brw_context *brw);
 326
 327 void
 328 gen6_blorp_emit_batch_head(struct brw_context *brw,
 329                            const brw_blorp_params *params);
 330
 331 void
 332 gen6_blorp_emit_state_base_address(struct brw_context *brw,
 333                                    const brw_blorp_params *params);
 334
 335 void
 336 gen6_blorp_emit_vertices(struct brw_context *brw,
 337                          const brw_blorp_params *params);
 338
 339 uint32_t
 340 gen6_blorp_emit_blend_state(struct brw_context *brw,
 341                             const brw_blorp_params *params);
 342
 343 uint32_t
 344 gen6_blorp_emit_cc_state(struct brw_context *brw,
 345                          const brw_blorp_params *params);
 346
 347 uint32_t
 348 gen6_blorp_emit_wm_constants(struct brw_context *brw,
 349                              const brw_blorp_params *params);
 350
 351 void
 352 gen6_blorp_emit_vs_disable(struct brw_context *brw,
 353                            const brw_blorp_params *params);
 354
 355 uint32_t
 356 gen6_blorp_emit_binding_table(struct brw_context *brw,
 357                               const brw_blorp_params *params,
 358                               uint32_t wm_surf_offset_renderbuffer,
 359                               uint32_t wm_surf_offset_texture);
 360
 361 uint32_t
 362 gen6_blorp_emit_depth_stencil_state(struct brw_context *brw,
 363                                     const brw_blorp_params *params);
 364
 365 void
 366 gen6_blorp_emit_gs_disable(struct brw_context *brw,
 367                            const brw_blorp_params *params);
 368
 369 void
 370 gen6_blorp_emit_clip_disable(struct brw_context *brw,
 371                              const brw_blorp_params *params);
 372
 373 void
 374 gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
 375                                   const brw_blorp_params *params);
 376 /** \} */
 377
 378 #endif /* __cplusplus */