src/mesa/drivers/dri/i965/brw_blorp.h

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #pragma once
  25
  26 #include <stdint.h>
  27
  28 #include "brw_reg.h"
  29 #include "intel_mipmap_tree.h"
  30
  31 struct brw_context;
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 void
  38 brw_blorp_blit_miptrees(struct brw_context *brw,
  39                         struct intel_mipmap_tree *src_mt,
  40                         unsigned src_level, unsigned src_layer,
  41                         mesa_format src_format,
  42                         struct intel_mipmap_tree *dst_mt,
  43                         unsigned dst_level, unsigned dst_layer,
  44                         mesa_format dst_format,
  45                         float src_x0, float src_y0,
  46                         float src_x1, float src_y1,
  47                         float dst_x0, float dst_y0,
  48                         float dst_x1, float dst_y1,
  49                         GLenum filter, bool mirror_x, bool mirror_y,
  50                         bool decode_srgb, bool encode_srgb);
  51
  52 #ifdef __cplusplus
  53 } /* end extern "C" */
  54
  55 /**
  56  * Binding table indices used by BLORP.
  57  */
  58 enum {
  59    BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX,
  60    BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
  61    BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
  62 };
  63
  64
  65 class brw_blorp_mip_info
  66 {
  67 public:
  68    brw_blorp_mip_info();
  69
  70    void set(struct intel_mipmap_tree *mt,
  71             unsigned int level, unsigned int layer);
  72
  73    struct intel_mipmap_tree *mt;
  74
  75    /**
  76     * The miplevel to use.
  77     */
  78    uint32_t level;
  79
  80    /**
  81     * The 2D layer within the miplevel. Combined, level and layer define the
  82     * 2D miptree slice to use.
  83     *
  84     * Note: if mt is a 2D multisample array texture on Gen7+ using
  85     * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, layer is the physical
  86     * layer holding sample 0.  So, for example, if mt->num_samples == 4, then
  87     * logical layer n corresponds to layer == 4*n.
  88     */
  89    uint32_t layer;
  90
  91    /**
  92     * Width of the miplevel to be used.  For surfaces using
  93     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
  94     */
  95    uint32_t width;
  96
  97    /**
  98     * Height of the miplevel to be used.  For surfaces using
  99     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
 100     */
 101    uint32_t height;
 102
 103    /**
 104     * X offset within the surface to texture from (or render to).  For
 105     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
 106     * pixels.
 107     */
 108    uint32_t x_offset;
 109
 110    /**
 111     * Y offset within the surface to texture from (or render to).  For
 112     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
 113     * pixels.
 114     */
 115    uint32_t y_offset;
 116 };
 117
 118 class brw_blorp_surface_info : public brw_blorp_mip_info
 119 {
 120 public:
 121    brw_blorp_surface_info();
 122
 123    void set(struct brw_context *brw,
 124             struct intel_mipmap_tree *mt,
 125             unsigned int level, unsigned int layer,
 126             mesa_format format, bool is_render_target);
 127
 128    uint32_t compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const;
 129
 130    /* Setting this flag indicates that the buffer's contents are W-tiled
 131     * stencil data, but the surface state should be set up for Y tiled
 132     * MESA_FORMAT_R_UNORM8 data (this is necessary because surface states don't
 133     * support W tiling).
 134     *
 135     * Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of
 136     * MESA_FORMAT_R_UNORM8 data are 128 pixels wide by 32 pixels high, the width and
 137     * pitch stored in the surface state will be multiplied by 2, and the
 138     * height will be halved.  Also, since W and Y tiles store their data in a
 139     * different order, the width and height will be rounded up to a multiple
 140     * of the tile size, to ensure that the WM program can access the full
 141     * width and height of the buffer.
 142     */
 143    bool map_stencil_as_y_tiled;
 144
 145    unsigned num_samples;
 146
 147    /**
 148     * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
 149     * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
 150     *
 151     * If ALL_SLICES_AT_EACH_LOD is set, then ARYSPC_LOD0 can be used. Ignored
 152     * prior to Gen7.
 153     */
 154    enum miptree_array_layout array_layout;
 155
 156    /**
 157     * Format that should be used when setting up the surface state for this
 158     * surface.  Should correspond to one of the BRW_SURFACEFORMAT_* enums.
 159     */
 160    uint32_t brw_surfaceformat;
 161
 162    /**
 163     * For MSAA surfaces, MSAA layout that should be used when setting up the
 164     * surface state for this surface.
 165     */
 166    intel_msaa_layout msaa_layout;
 167 };
 168
 169
 170 struct brw_blorp_coord_transform_params
 171 {
 172    void setup(GLfloat src0, GLfloat src1, GLfloat dst0, GLfloat dst1,
 173               bool mirror);
 174
 175    float multiplier;
 176    float offset;
 177 };
 178
 179
 180 struct brw_blorp_wm_push_constants
 181 {
 182    uint32_t dst_x0;
 183    uint32_t dst_x1;
 184    uint32_t dst_y0;
 185    uint32_t dst_y1;
 186    /* Top right coordinates of the rectangular grid used for scaled blitting */
 187    float rect_grid_x1;
 188    float rect_grid_y1;
 189    brw_blorp_coord_transform_params x_transform;
 190    brw_blorp_coord_transform_params y_transform;
 191    /* Pad out to an integral number of registers */
 192    uint32_t pad[6];
 193 };
 194
 195 /* Every 32 bytes of push constant data constitutes one GEN register. */
 196 const unsigned int BRW_BLORP_NUM_PUSH_CONST_REGS =
 197    sizeof(brw_blorp_wm_push_constants) / 32;
 198
 199 struct brw_blorp_prog_data
 200 {
 201    unsigned int first_curbe_grf;
 202
 203    /**
 204     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 205     * than one sample per pixel.
 206     */
 207    bool persample_msaa_dispatch;
 208 };
 209
 210
 211 class brw_blorp_params
 212 {
 213 public:
 214    brw_blorp_params(unsigned num_varyings = 0,
 215                     unsigned num_draw_buffers = 1,
 216                     unsigned num_layers = 1);
 217
 218    virtual uint32_t get_wm_prog(struct brw_context *brw,
 219                                 brw_blorp_prog_data **prog_data) const = 0;
 220
 221    uint32_t x0;
 222    uint32_t y0;
 223    uint32_t x1;
 224    uint32_t y1;
 225    brw_blorp_mip_info depth;
 226    uint32_t depth_format;
 227    brw_blorp_surface_info src;
 228    brw_blorp_surface_info dst;
 229    enum gen6_hiz_op hiz_op;
 230    bool use_wm_prog;
 231    brw_blorp_wm_push_constants wm_push_consts;
 232    const unsigned num_varyings;
 233    const unsigned num_draw_buffers;
 234    const unsigned num_layers;
 235 };
 236
 237
 238 void
 239 brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params);
 240
 241 void
 242 gen6_blorp_exec(struct brw_context *brw,
 243                 const brw_blorp_params *params);
 244
 245 void
 246 gen7_blorp_exec(struct brw_context *brw,
 247                 const brw_blorp_params *params);
 248
 249 /**
 250  * Parameters for a HiZ or depth resolve operation.
 251  *
 252  * For an overview of HiZ ops, see the following sections of the Sandy Bridge
 253  * PRM, Volume 1, Part 2:
 254  *   - 7.5.3.1 Depth Buffer Clear
 255  *   - 7.5.3.2 Depth Buffer Resolve
 256  *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
 257  */
 258 class brw_hiz_op_params : public brw_blorp_params
 259 {
 260 public:
 261    brw_hiz_op_params(struct intel_mipmap_tree *mt,
 262                      unsigned int level, unsigned int layer,
 263                      gen6_hiz_op op);
 264
 265    virtual uint32_t get_wm_prog(struct brw_context *brw,
 266                                 brw_blorp_prog_data **prog_data) const;
 267 };
 268
 269 struct brw_blorp_blit_prog_key
 270 {
 271    /* Number of samples per pixel that have been configured in the surface
 272     * state for texturing from.
 273     */
 274    unsigned tex_samples;
 275
 276    /* MSAA layout that has been configured in the surface state for texturing
 277     * from.
 278     */
 279    intel_msaa_layout tex_layout;
 280
 281    /* Actual number of samples per pixel in the source image. */
 282    unsigned src_samples;
 283
 284    /* Actual MSAA layout used by the source image. */
 285    intel_msaa_layout src_layout;
 286
 287    /* Number of samples per pixel that have been configured in the render
 288     * target.
 289     */
 290    unsigned rt_samples;
 291
 292    /* MSAA layout that has been configured in the render target. */
 293    intel_msaa_layout rt_layout;
 294
 295    /* Actual number of samples per pixel in the destination image. */
 296    unsigned dst_samples;
 297
 298    /* Actual MSAA layout used by the destination image. */
 299    intel_msaa_layout dst_layout;
 300
 301    /* Type of the data to be read from the texture (one of
 302     * BRW_REGISTER_TYPE_{UD,D,F}).
 303     */
 304    enum brw_reg_type texture_data_type;
 305
 306    /* True if the source image is W tiled.  If true, the surface state for the
 307     * source image must be configured as Y tiled, and tex_samples must be 0.
 308     */
 309    bool src_tiled_w;
 310
 311    /* True if the destination image is W tiled.  If true, the surface state
 312     * for the render target must be configured as Y tiled, and rt_samples must
 313     * be 0.
 314     */
 315    bool dst_tiled_w;
 316
 317    /* True if all source samples should be blended together to produce each
 318     * destination pixel.  If true, src_tiled_w must be false, tex_samples must
 319     * equal src_samples, and tex_samples must be nonzero.
 320     */
 321    bool blend;
 322
 323    /* True if the rectangle being sent through the rendering pipeline might be
 324     * larger than the destination rectangle, so the WM program should kill any
 325     * pixels that are outside the destination rectangle.
 326     */
 327    bool use_kill;
 328
 329    /**
 330     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 331     * than one sample per pixel.
 332     */
 333    bool persample_msaa_dispatch;
 334
 335    /* True for scaled blitting. */
 336    bool blit_scaled;
 337
 338    /* Scale factors between the pixel grid and the grid of samples. We're
 339     * using grid of samples for bilinear filetring in multisample scaled blits.
 340     */
 341    float x_scale;
 342    float y_scale;
 343
 344    /* True for blits with filter = GL_LINEAR. */
 345    bool bilinear_filter;
 346 };
 347
 348 class brw_blorp_blit_params : public brw_blorp_params
 349 {
 350 public:
 351    brw_blorp_blit_params(struct brw_context *brw,
 352                          struct intel_mipmap_tree *src_mt,
 353                          unsigned src_level, unsigned src_layer,
 354                          mesa_format src_format,
 355                          struct intel_mipmap_tree *dst_mt,
 356                          unsigned dst_level, unsigned dst_layer,
 357                          mesa_format dst_format,
 358                          GLfloat src_x0, GLfloat src_y0,
 359                          GLfloat src_x1, GLfloat src_y1,
 360                          GLfloat dst_x0, GLfloat dst_y0,
 361                          GLfloat dst_x1, GLfloat dst_y1,
 362                          GLenum filter, bool mirror_x, bool mirror_y);
 363
 364    virtual uint32_t get_wm_prog(struct brw_context *brw,
 365                                 brw_blorp_prog_data **prog_data) const;
 366
 367 private:
 368    brw_blorp_blit_prog_key wm_prog_key;
 369 };
 370
 371 /**
 372  * \name BLORP internals
 373  * \{
 374  *
 375  * Used internally by gen6_blorp_exec() and gen7_blorp_exec().
 376  */
 377
 378 void
 379 gen6_blorp_init(struct brw_context *brw);
 380
 381 void
 382 gen6_blorp_emit_state_base_address(struct brw_context *brw,
 383                                    const brw_blorp_params *params);
 384
 385 void
 386 gen6_blorp_emit_vertices(struct brw_context *brw,
 387                          const brw_blorp_params *params);
 388
 389 uint32_t
 390 gen6_blorp_emit_blend_state(struct brw_context *brw,
 391                             const brw_blorp_params *params);
 392
 393 uint32_t
 394 gen6_blorp_emit_cc_state(struct brw_context *brw);
 395
 396 uint32_t
 397 gen6_blorp_emit_wm_constants(struct brw_context *brw,
 398                              const brw_blorp_params *params);
 399
 400 void
 401 gen6_blorp_emit_vs_disable(struct brw_context *brw,
 402                            const brw_blorp_params *params);
 403
 404 uint32_t
 405 gen6_blorp_emit_binding_table(struct brw_context *brw,
 406                               uint32_t wm_surf_offset_renderbuffer,
 407                               uint32_t wm_surf_offset_texture);
 408
 409 uint32_t
 410 gen6_blorp_emit_depth_stencil_state(struct brw_context *brw,
 411                                     const brw_blorp_params *params);
 412
 413 void
 414 gen6_blorp_emit_gs_disable(struct brw_context *brw,
 415                            const brw_blorp_params *params);
 416
 417 void
 418 gen6_blorp_emit_clip_disable(struct brw_context *brw);
 419
 420 void
 421 gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
 422                                   const brw_blorp_params *params);
 423
 424 uint32_t
 425 gen6_blorp_emit_sampler_state(struct brw_context *brw,
 426                               unsigned tex_filter, unsigned max_lod,
 427                               bool non_normalized_coords);
 428
 429 /** \} */
 430
 431 #endif /* __cplusplus */