src/mesa/drivers/dri/i965/brw_blorp.h

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #pragma once
  25
  26 #include <stdint.h>
  27
  28 #include "brw_context.h"
  29 #include "intel_mipmap_tree.h"
  30
  31 struct brw_context;
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 void
  38 brw_blorp_blit_miptrees(struct intel_context *intel,
  39                         struct intel_mipmap_tree *src_mt,
  40                         unsigned src_level, unsigned src_layer,
  41                         struct intel_mipmap_tree *dst_mt,
  42                         unsigned dst_level, unsigned dst_layer,
  43                         int src_x0, int src_y0,
  44                         int dst_x0, int dst_y0,
  45                         int dst_x1, int dst_y1,
  46                         bool mirror_x, bool mirror_y);
  47
  48 #ifdef __cplusplus
  49 } /* end extern "C" */
  50
  51 /**
  52  * Binding table indices used by BLORP.
  53  */
  54 enum {
  55    BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX,
  56    BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
  57    BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
  58 };
  59
  60
  61 class brw_blorp_mip_info
  62 {
  63 public:
  64    brw_blorp_mip_info();
  65
  66    void set(struct intel_mipmap_tree *mt,
  67             unsigned int level, unsigned int layer);
  68
  69    struct intel_mipmap_tree *mt;
  70
  71    /**
  72     * The miplevel to use.
  73     */
  74    uint32_t level;
  75
  76    /**
  77     * The 2D layer within the miplevel. Combined, level and layer define the
  78     * 2D miptree slice to use.
  79     */
  80    uint32_t layer;
  81
  82    /**
  83     * Width of the miplevel to be used.  For surfaces using
  84     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
  85     */
  86    uint32_t width;
  87
  88    /**
  89     * Height of the miplevel to be used.  For surfaces using
  90     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
  91     */
  92    uint32_t height;
  93
  94    /**
  95     * X offset within the surface to texture from (or render to).  For
  96     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
  97     * pixels.
  98     */
  99    uint32_t x_offset;
 100
 101    /**
 102     * Y offset within the surface to texture from (or render to).  For
 103     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
 104     * pixels.
 105     */
 106    uint32_t y_offset;
 107 };
 108
 109 class brw_blorp_surface_info : public brw_blorp_mip_info
 110 {
 111 public:
 112    brw_blorp_surface_info();
 113
 114    void set(struct brw_context *brw,
 115             struct intel_mipmap_tree *mt,
 116             unsigned int level, unsigned int layer);
 117
 118    uint32_t compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const;
 119
 120    /* Setting this flag indicates that the buffer's contents are W-tiled
 121     * stencil data, but the surface state should be set up for Y tiled
 122     * MESA_FORMAT_R8 data (this is necessary because surface states don't
 123     * support W tiling).
 124     *
 125     * Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of
 126     * MESA_FORMAT_R8 data are 128 pixels wide by 32 pixels high, the width and
 127     * pitch stored in the surface state will be multiplied by 2, and the
 128     * height will be halved.  Also, since W and Y tiles store their data in a
 129     * different order, the width and height will be rounded up to a multiple
 130     * of the tile size, to ensure that the WM program can access the full
 131     * width and height of the buffer.
 132     */
 133    bool map_stencil_as_y_tiled;
 134
 135    unsigned num_samples;
 136
 137    /* Setting this flag indicates that the surface should be set up in
 138     * ARYSPC_LOD0 mode.  Ignored prior to Gen7.
 139     */
 140    bool array_spacing_lod0;
 141
 142    /**
 143     * Format that should be used when setting up the surface state for this
 144     * surface.  Should correspond to one of the BRW_SURFACEFORMAT_* enums.
 145     */
 146    uint32_t brw_surfaceformat;
 147
 148    /**
 149     * For MSAA surfaces, MSAA layout that should be used when setting up the
 150     * surface state for this surface.
 151     */
 152    intel_msaa_layout msaa_layout;
 153 };
 154
 155
 156 struct brw_blorp_coord_transform_params
 157 {
 158    void setup(GLuint src0, GLuint dst0, GLuint dst1,
 159               bool mirror);
 160
 161    int16_t multiplier;
 162    int16_t offset;
 163 };
 164
 165
 166 struct brw_blorp_wm_push_constants
 167 {
 168    uint16_t dst_x0;
 169    uint16_t dst_x1;
 170    uint16_t dst_y0;
 171    uint16_t dst_y1;
 172    brw_blorp_coord_transform_params x_transform;
 173    brw_blorp_coord_transform_params y_transform;
 174
 175    /* Pad out to an integral number of registers */
 176    uint16_t pad[8];
 177 };
 178
 179 /* Every 32 bytes of push constant data constitutes one GEN register. */
 180 const unsigned int BRW_BLORP_NUM_PUSH_CONST_REGS =
 181    sizeof(brw_blorp_wm_push_constants) / 32;
 182
 183 struct brw_blorp_prog_data
 184 {
 185    unsigned int first_curbe_grf;
 186
 187    /**
 188     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 189     * than one sample per pixel.
 190     */
 191    bool persample_msaa_dispatch;
 192 };
 193
 194 class brw_blorp_params
 195 {
 196 public:
 197    brw_blorp_params();
 198
 199    virtual uint32_t get_wm_prog(struct brw_context *brw,
 200                                 brw_blorp_prog_data **prog_data) const = 0;
 201
 202    uint32_t x0;
 203    uint32_t y0;
 204    uint32_t x1;
 205    uint32_t y1;
 206    brw_blorp_mip_info depth;
 207    uint32_t depth_format;
 208    brw_blorp_surface_info src;
 209    brw_blorp_surface_info dst;
 210    enum gen6_hiz_op hiz_op;
 211    unsigned num_samples;
 212    bool use_wm_prog;
 213    brw_blorp_wm_push_constants wm_push_consts;
 214 };
 215
 216
 217 void
 218 brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params);
 219
 220
 221 /**
 222  * Parameters for a HiZ or depth resolve operation.
 223  *
 224  * For an overview of HiZ ops, see the following sections of the Sandy Bridge
 225  * PRM, Volume 1, Part 2:
 226  *   - 7.5.3.1 Depth Buffer Clear
 227  *   - 7.5.3.2 Depth Buffer Resolve
 228  *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
 229  */
 230 class brw_hiz_op_params : public brw_blorp_params
 231 {
 232 public:
 233    brw_hiz_op_params(struct intel_mipmap_tree *mt,
 234                      unsigned int level, unsigned int layer,
 235                      gen6_hiz_op op);
 236
 237    virtual uint32_t get_wm_prog(struct brw_context *brw,
 238                                 brw_blorp_prog_data **prog_data) const;
 239 };
 240
 241 struct brw_blorp_blit_prog_key
 242 {
 243    /* Number of samples per pixel that have been configured in the surface
 244     * state for texturing from.
 245     */
 246    unsigned tex_samples;
 247
 248    /* MSAA layout that has been configured in the surface state for texturing
 249     * from.
 250     */
 251    intel_msaa_layout tex_layout;
 252
 253    /* Actual number of samples per pixel in the source image. */
 254    unsigned src_samples;
 255
 256    /* Actual MSAA layout used by the source image. */
 257    intel_msaa_layout src_layout;
 258
 259    /* Number of samples per pixel that have been configured in the render
 260     * target.
 261     */
 262    unsigned rt_samples;
 263
 264    /* MSAA layout that has been configured in the render target. */
 265    intel_msaa_layout rt_layout;
 266
 267    /* Actual number of samples per pixel in the destination image. */
 268    unsigned dst_samples;
 269
 270    /* Actual MSAA layout used by the destination image. */
 271    intel_msaa_layout dst_layout;
 272
 273    /* Type of the data to be read from the texture (one of
 274     * BRW_REGISTER_TYPE_{UD,D,F}).
 275     */
 276    unsigned texture_data_type;
 277
 278    /* True if the source image is W tiled.  If true, the surface state for the
 279     * source image must be configured as Y tiled, and tex_samples must be 0.
 280     */
 281    bool src_tiled_w;
 282
 283    /* True if the destination image is W tiled.  If true, the surface state
 284     * for the render target must be configured as Y tiled, and rt_samples must
 285     * be 0.
 286     */
 287    bool dst_tiled_w;
 288
 289    /* True if all source samples should be blended together to produce each
 290     * destination pixel.  If true, src_tiled_w must be false, tex_samples must
 291     * equal src_samples, and tex_samples must be nonzero.
 292     */
 293    bool blend;
 294
 295    /* True if the rectangle being sent through the rendering pipeline might be
 296     * larger than the destination rectangle, so the WM program should kill any
 297     * pixels that are outside the destination rectangle.
 298     */
 299    bool use_kill;
 300
 301    /**
 302     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 303     * than one sample per pixel.
 304     */
 305    bool persample_msaa_dispatch;
 306 };
 307
 308 class brw_blorp_blit_params : public brw_blorp_params
 309 {
 310 public:
 311    brw_blorp_blit_params(struct brw_context *brw,
 312                          struct intel_mipmap_tree *src_mt,
 313                          unsigned src_level, unsigned src_layer,
 314                          struct intel_mipmap_tree *dst_mt,
 315                          unsigned dst_level, unsigned dst_layer,
 316                          GLuint src_x0, GLuint src_y0,
 317                          GLuint dst_x0, GLuint dst_y0,
 318                          GLuint width, GLuint height,
 319                          bool mirror_x, bool mirror_y);
 320
 321    virtual uint32_t get_wm_prog(struct brw_context *brw,
 322                                 brw_blorp_prog_data **prog_data) const;
 323
 324 private:
 325    brw_blorp_blit_prog_key wm_prog_key;
 326 };
 327
 328 /**
 329  * \name BLORP internals
 330  * \{
 331  *
 332  * Used internally by gen6_blorp_exec() and gen7_blorp_exec().
 333  */
 334
 335 void
 336 gen6_blorp_init(struct brw_context *brw);
 337
 338 void
 339 gen6_blorp_emit_batch_head(struct brw_context *brw,
 340                            const brw_blorp_params *params);
 341
 342 void
 343 gen6_blorp_emit_state_base_address(struct brw_context *brw,
 344                                    const brw_blorp_params *params);
 345
 346 void
 347 gen6_blorp_emit_vertices(struct brw_context *brw,
 348                          const brw_blorp_params *params);
 349
 350 uint32_t
 351 gen6_blorp_emit_blend_state(struct brw_context *brw,
 352                             const brw_blorp_params *params);
 353
 354 uint32_t
 355 gen6_blorp_emit_cc_state(struct brw_context *brw,
 356                          const brw_blorp_params *params);
 357
 358 uint32_t
 359 gen6_blorp_emit_wm_constants(struct brw_context *brw,
 360                              const brw_blorp_params *params);
 361
 362 void
 363 gen6_blorp_emit_vs_disable(struct brw_context *brw,
 364                            const brw_blorp_params *params);
 365
 366 uint32_t
 367 gen6_blorp_emit_binding_table(struct brw_context *brw,
 368                               const brw_blorp_params *params,
 369                               uint32_t wm_surf_offset_renderbuffer,
 370                               uint32_t wm_surf_offset_texture);
 371
 372 uint32_t
 373 gen6_blorp_emit_depth_stencil_state(struct brw_context *brw,
 374                                     const brw_blorp_params *params);
 375
 376 void
 377 gen6_blorp_emit_gs_disable(struct brw_context *brw,
 378                            const brw_blorp_params *params);
 379
 380 void
 381 gen6_blorp_emit_clip_disable(struct brw_context *brw,
 382                              const brw_blorp_params *params);
 383
 384 void
 385 gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
 386                                   const brw_blorp_params *params);
 387 /** \} */
 388
 389 #endif /* __cplusplus */