src/mesa/drivers/dri/i965/brw_blorp.h

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #pragma once
  25
  26 #include <stdint.h>
  27
  28 #include "brw_context.h"
  29 #include "intel_mipmap_tree.h"
  30
  31 struct brw_context;
  32
  33
  34 /**
  35  * Binding table indices used by BLORP.
  36  */
  37 enum {
  38    BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX,
  39    BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
  40    BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
  41 };
  42
  43
  44 class brw_blorp_mip_info
  45 {
  46 public:
  47    brw_blorp_mip_info();
  48
  49    virtual void set(struct intel_mipmap_tree *mt,
  50                     unsigned int level, unsigned int layer);
  51    void get_draw_offsets(uint32_t *draw_x, uint32_t *draw_y) const;
  52
  53    void get_miplevel_dims(uint32_t *width, uint32_t *height) const
  54    {
  55       *width = mt->level[level].width;
  56       *height = mt->level[level].height;
  57    }
  58
  59    struct intel_mipmap_tree *mt;
  60    unsigned int level;
  61    unsigned int layer;
  62 };
  63
  64 class brw_blorp_surface_info : public brw_blorp_mip_info
  65 {
  66 public:
  67    brw_blorp_surface_info();
  68
  69    virtual void set(struct intel_mipmap_tree *mt,
  70                     unsigned int level, unsigned int layer);
  71
  72    /* Setting this flag indicates that the buffer's contents are W-tiled
  73     * stencil data, but the surface state should be set up for Y tiled
  74     * MESA_FORMAT_R8 data (this is necessary because surface states don't
  75     * support W tiling).
  76     *
  77     * Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of
  78     * MESA_FORMAT_R8 data are 128 pixels wide by 32 pixels high, the width and
  79     * pitch stored in the surface state will be multiplied by 2, and the
  80     * height will be halved.  Also, since W and Y tiles store their data in a
  81     * different order, the width and height will be rounded up to a multiple
  82     * of the tile size, to ensure that the WM program can access the full
  83     * width and height of the buffer.
  84     */
  85    bool map_stencil_as_y_tiled;
  86
  87    unsigned num_samples;
  88
  89    /* Setting this flag indicates that the surface should be set up in
  90     * ARYSPC_LOD0 mode.  Ignored prior to Gen7.
  91     */
  92    bool array_spacing_lod0;
  93 };
  94
  95
  96 struct brw_blorp_coord_transform_params
  97 {
  98    void setup(GLuint src0, GLuint dst0, GLuint dst1,
  99               bool mirror);
 100
 101    int16_t multiplier;
 102    int16_t offset;
 103 };
 104
 105
 106 struct brw_blorp_wm_push_constants
 107 {
 108    uint16_t dst_x0;
 109    uint16_t dst_x1;
 110    uint16_t dst_y0;
 111    uint16_t dst_y1;
 112    brw_blorp_coord_transform_params x_transform;
 113    brw_blorp_coord_transform_params y_transform;
 114
 115    /* Pad out to an integral number of registers */
 116    uint16_t pad[8];
 117 };
 118
 119 /* Every 32 bytes of push constant data constitutes one GEN register. */
 120 const unsigned int BRW_BLORP_NUM_PUSH_CONST_REGS =
 121    sizeof(brw_blorp_wm_push_constants) / 32;
 122
 123 struct brw_blorp_prog_data
 124 {
 125    unsigned int first_curbe_grf;
 126
 127    /**
 128     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 129     * than one sample per pixel.
 130     */
 131    bool persample_msaa_dispatch;
 132 };
 133
 134 class brw_blorp_params
 135 {
 136 public:
 137    brw_blorp_params();
 138
 139    virtual uint32_t get_wm_prog(struct brw_context *brw,
 140                                 brw_blorp_prog_data **prog_data) const = 0;
 141
 142    uint32_t x0;
 143    uint32_t y0;
 144    uint32_t x1;
 145    uint32_t y1;
 146    brw_blorp_mip_info depth;
 147    uint32_t depth_format;
 148    brw_blorp_surface_info src;
 149    brw_blorp_surface_info dst;
 150    enum gen6_hiz_op hiz_op;
 151    unsigned num_samples;
 152    bool use_wm_prog;
 153    brw_blorp_wm_push_constants wm_push_consts;
 154 };
 155
 156
 157 void
 158 brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params);
 159
 160
 161 /**
 162  * Parameters for a HiZ or depth resolve operation.
 163  *
 164  * For an overview of HiZ ops, see the following sections of the Sandy Bridge
 165  * PRM, Volume 1, Part 2:
 166  *   - 7.5.3.1 Depth Buffer Clear
 167  *   - 7.5.3.2 Depth Buffer Resolve
 168  *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
 169  */
 170 class brw_hiz_op_params : public brw_blorp_params
 171 {
 172 public:
 173    brw_hiz_op_params(struct intel_mipmap_tree *mt,
 174                      unsigned int level, unsigned int layer,
 175                      gen6_hiz_op op);
 176
 177    virtual uint32_t get_wm_prog(struct brw_context *brw,
 178                                 brw_blorp_prog_data **prog_data) const;
 179 };
 180
 181 struct brw_blorp_blit_prog_key
 182 {
 183    /* Number of samples per pixel that have been configured in the surface
 184     * state for texturing from.
 185     */
 186    unsigned tex_samples;
 187
 188    /* Actual number of samples per pixel in the source image. */
 189    unsigned src_samples;
 190
 191    /* If src_samples > 0, whether or not the source image uses an interleaved
 192     * MSAA layout.  False if src_samples == 0.
 193     */
 194    bool src_interleaved;
 195
 196    /* Number of samples per pixel that have been configured in the render
 197     * target.
 198     */
 199    unsigned rt_samples;
 200
 201    /* Actual number of samples per pixel in the destination image. */
 202    unsigned dst_samples;
 203
 204    /* If dst_samples > 0, whether or not the destination image uses an
 205     * interleaved MSAA layout.  False if dst_samples == 0.
 206     */
 207    bool dst_interleaved;
 208
 209    /* True if the source image is W tiled.  If true, the surface state for the
 210     * source image must be configured as Y tiled, and tex_samples must be 0.
 211     */
 212    bool src_tiled_w;
 213
 214    /* True if the destination image is W tiled.  If true, the surface state
 215     * for the render target must be configured as Y tiled, and rt_samples must
 216     * be 0.
 217     */
 218    bool dst_tiled_w;
 219
 220    /* True if all source samples should be blended together to produce each
 221     * destination pixel.  If true, src_tiled_w must be false, tex_samples must
 222     * equal src_samples, and tex_samples must be nonzero.
 223     */
 224    bool blend;
 225
 226    /* True if the rectangle being sent through the rendering pipeline might be
 227     * larger than the destination rectangle, so the WM program should kill any
 228     * pixels that are outside the destination rectangle.
 229     */
 230    bool use_kill;
 231
 232    /**
 233     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 234     * than one sample per pixel.
 235     */
 236    bool persample_msaa_dispatch;
 237 };
 238
 239 class brw_blorp_blit_params : public brw_blorp_params
 240 {
 241 public:
 242    brw_blorp_blit_params(struct brw_context *brw,
 243                          struct intel_mipmap_tree *src_mt,
 244                          struct intel_mipmap_tree *dst_mt,
 245                          GLuint src_x0, GLuint src_y0,
 246                          GLuint dst_x0, GLuint dst_y0,
 247                          GLuint width, GLuint height,
 248                          bool mirror_x, bool mirror_y);
 249
 250    virtual uint32_t get_wm_prog(struct brw_context *brw,
 251                                 brw_blorp_prog_data **prog_data) const;
 252
 253 private:
 254    brw_blorp_blit_prog_key wm_prog_key;
 255 };
 256
 257 /**
 258  * \name BLORP internals
 259  * \{
 260  *
 261  * Used internally by gen6_blorp_exec() and gen7_blorp_exec().
 262  */
 263
 264 void
 265 gen6_blorp_init(struct brw_context *brw);
 266
 267 void
 268 gen6_blorp_compute_tile_masks(const brw_blorp_params *params,
 269                               uint32_t *tile_mask_x, uint32_t *tile_mask_y);
 270
 271 void
 272 gen6_blorp_emit_batch_head(struct brw_context *brw,
 273                            const brw_blorp_params *params);
 274
 275 void
 276 gen6_blorp_emit_state_base_address(struct brw_context *brw,
 277                                    const brw_blorp_params *params);
 278
 279 void
 280 gen6_blorp_emit_vertices(struct brw_context *brw,
 281                          const brw_blorp_params *params);
 282
 283 uint32_t
 284 gen6_blorp_emit_blend_state(struct brw_context *brw,
 285                             const brw_blorp_params *params);
 286
 287 uint32_t
 288 gen6_blorp_emit_cc_state(struct brw_context *brw,
 289                          const brw_blorp_params *params);
 290
 291 uint32_t
 292 gen6_blorp_emit_wm_constants(struct brw_context *brw,
 293                              const brw_blorp_params *params);
 294
 295 void
 296 gen6_blorp_emit_vs_disable(struct brw_context *brw,
 297                            const brw_blorp_params *params);
 298
 299 uint32_t
 300 gen6_blorp_emit_binding_table(struct brw_context *brw,
 301                               const brw_blorp_params *params,
 302                               uint32_t wm_surf_offset_renderbuffer,
 303                               uint32_t wm_surf_offset_texture);
 304
 305 uint32_t
 306 gen6_blorp_emit_depth_stencil_state(struct brw_context *brw,
 307                                     const brw_blorp_params *params);
 308
 309 void
 310 gen6_blorp_emit_gs_disable(struct brw_context *brw,
 311                            const brw_blorp_params *params);
 312
 313 void
 314 gen6_blorp_emit_clip_disable(struct brw_context *brw,
 315                              const brw_blorp_params *params);
 316
 317 void
 318 gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
 319                                   const brw_blorp_params *params);
 320 /** \} */