src/mesa/drivers/dri/i965/brw_blorp.h

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #pragma once
  25
  26 #include <stdint.h>
  27
  28 #include "brw_reg.h"
  29 #include "intel_mipmap_tree.h"
  30
  31 struct brw_context;
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 void
  38 brw_blorp_blit_miptrees(struct brw_context *brw,
  39                         struct intel_mipmap_tree *src_mt,
  40                         unsigned src_level, unsigned src_layer,
  41                         mesa_format src_format, int src_swizzle,
  42                         struct intel_mipmap_tree *dst_mt,
  43                         unsigned dst_level, unsigned dst_layer,
  44                         mesa_format dst_format,
  45                         float src_x0, float src_y0,
  46                         float src_x1, float src_y1,
  47                         float dst_x0, float dst_y0,
  48                         float dst_x1, float dst_y1,
  49                         GLenum filter, bool mirror_x, bool mirror_y,
  50                         bool decode_srgb, bool encode_srgb);
  51
  52 bool
  53 brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb,
  54                       GLbitfield mask, bool partial_clear, bool encode_srgb);
  55
  56 void
  57 brw_blorp_resolve_color(struct brw_context *brw,
  58                         struct intel_mipmap_tree *mt);
  59
  60 #ifdef __cplusplus
  61 } /* end extern "C" */
  62
  63 /**
  64  * Binding table indices used by BLORP.
  65  */
  66 enum {
  67    BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
  68    BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX,
  69    BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
  70 };
  71
  72 struct brw_blorp_surface_info
  73 {
  74    struct intel_mipmap_tree *mt;
  75
  76    /**
  77     * The miplevel to use.
  78     */
  79    uint32_t level;
  80
  81    /**
  82     * The 2D layer within the miplevel. Combined, level and layer define the
  83     * 2D miptree slice to use.
  84     *
  85     * Note: if mt is a 2D multisample array texture on Gen7+ using
  86     * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, layer is the physical
  87     * layer holding sample 0.  So, for example, if mt->num_samples == 4, then
  88     * logical layer n corresponds to layer == 4*n.
  89     */
  90    uint32_t layer;
  91
  92    /**
  93     * Width of the miplevel to be used.  For surfaces using
  94     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
  95     */
  96    uint32_t width;
  97
  98    /**
  99     * Height of the miplevel to be used.  For surfaces using
 100     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
 101     */
 102    uint32_t height;
 103
 104    /**
 105     * X offset within the surface to texture from (or render to).  For
 106     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
 107     * pixels.
 108     */
 109    uint32_t x_offset;
 110
 111    /**
 112     * Y offset within the surface to texture from (or render to).  For
 113     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
 114     * pixels.
 115     */
 116    uint32_t y_offset;
 117
 118    /* Setting this flag indicates that the buffer's contents are W-tiled
 119     * stencil data, but the surface state should be set up for Y tiled
 120     * MESA_FORMAT_R_UNORM8 data (this is necessary because surface states don't
 121     * support W tiling).
 122     *
 123     * Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of
 124     * MESA_FORMAT_R_UNORM8 data are 128 pixels wide by 32 pixels high, the width and
 125     * pitch stored in the surface state will be multiplied by 2, and the
 126     * height will be halved.  Also, since W and Y tiles store their data in a
 127     * different order, the width and height will be rounded up to a multiple
 128     * of the tile size, to ensure that the WM program can access the full
 129     * width and height of the buffer.
 130     */
 131    bool map_stencil_as_y_tiled;
 132
 133    unsigned num_samples;
 134
 135    /**
 136     * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
 137     * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
 138     *
 139     * If ALL_SLICES_AT_EACH_LOD is set, then ARYSPC_LOD0 can be used. Ignored
 140     * prior to Gen7.
 141     */
 142    enum miptree_array_layout array_layout;
 143
 144    /**
 145     * Format that should be used when setting up the surface state for this
 146     * surface.  Should correspond to one of the BRW_SURFACEFORMAT_* enums.
 147     */
 148    uint32_t brw_surfaceformat;
 149
 150    /**
 151     * For MSAA surfaces, MSAA layout that should be used when setting up the
 152     * surface state for this surface.
 153     */
 154    enum intel_msaa_layout msaa_layout;
 155
 156    /**
 157     * In order to support cases where RGBA format is backing client requested
 158     * RGB, one needs to have means to force alpha channel to one when user
 159     * requested RGB surface is used as blit source. This is possible by
 160     * setting source swizzle for the texture surface.
 161     */
 162    int swizzle;
 163 };
 164
 165 void
 166 brw_blorp_surface_info_init(struct brw_context *brw,
 167                             struct brw_blorp_surface_info *info,
 168                             struct intel_mipmap_tree *mt,
 169                             unsigned int level, unsigned int layer,
 170                             mesa_format format, bool is_render_target);
 171
 172 uint32_t
 173 brw_blorp_compute_tile_offsets(const struct brw_blorp_surface_info *info,
 174                                uint32_t *tile_x, uint32_t *tile_y);
 175
 176
 177
 178 struct brw_blorp_coord_transform
 179 {
 180    float multiplier;
 181    float offset;
 182 };
 183
 184 struct brw_blorp_wm_push_constants
 185 {
 186    uint32_t dst_x0;
 187    uint32_t dst_x1;
 188    uint32_t dst_y0;
 189    uint32_t dst_y1;
 190    /* Top right coordinates of the rectangular grid used for scaled blitting */
 191    float rect_grid_x1;
 192    float rect_grid_y1;
 193    struct brw_blorp_coord_transform x_transform;
 194    struct brw_blorp_coord_transform y_transform;
 195
 196    /* Minimum layer setting works for all the textures types but texture_3d
 197     * for which the setting has no effect. Use the z-coordinate instead.
 198     */
 199    uint32_t src_z;
 200
 201    /* Pad out to an integral number of registers */
 202    uint32_t pad[5];
 203 };
 204
 205 /* Every 32 bytes of push constant data constitutes one GEN register. */
 206 const unsigned int BRW_BLORP_NUM_PUSH_CONST_REGS =
 207    sizeof(brw_blorp_wm_push_constants) / 32;
 208
 209 struct brw_blorp_prog_data
 210 {
 211    unsigned int first_curbe_grf;
 212
 213    /**
 214     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 215     * than one sample per pixel.
 216     */
 217    bool persample_msaa_dispatch;
 218 };
 219
 220 struct brw_blorp_params
 221 {
 222    uint32_t x0;
 223    uint32_t y0;
 224    uint32_t x1;
 225    uint32_t y1;
 226    struct brw_blorp_surface_info depth;
 227    uint32_t depth_format;
 228    struct brw_blorp_surface_info src;
 229    struct brw_blorp_surface_info dst;
 230    enum gen6_hiz_op hiz_op;
 231    unsigned fast_clear_op;
 232    bool color_write_disable[4];
 233    struct brw_blorp_wm_push_constants wm_push_consts;
 234    unsigned num_varyings;
 235    unsigned num_draw_buffers;
 236    unsigned num_layers;
 237    uint32_t wm_prog_kernel;
 238    struct brw_blorp_prog_data *wm_prog_data;
 239 };
 240
 241 void
 242 brw_blorp_params_init(struct brw_blorp_params *params);
 243
 244 void
 245 brw_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params);
 246
 247 void
 248 gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 249                     unsigned level, unsigned layer, enum gen6_hiz_op op);
 250
 251 void
 252 gen6_blorp_exec(struct brw_context *brw,
 253                 const struct brw_blorp_params *params);
 254
 255 void
 256 gen7_blorp_exec(struct brw_context *brw,
 257                 const struct brw_blorp_params *params);
 258
 259 void
 260 gen8_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params);
 261
 262 struct brw_blorp_blit_prog_key
 263 {
 264    /* Number of samples per pixel that have been configured in the surface
 265     * state for texturing from.
 266     */
 267    unsigned tex_samples;
 268
 269    /* MSAA layout that has been configured in the surface state for texturing
 270     * from.
 271     */
 272    intel_msaa_layout tex_layout;
 273
 274    /* Actual number of samples per pixel in the source image. */
 275    unsigned src_samples;
 276
 277    /* Actual MSAA layout used by the source image. */
 278    intel_msaa_layout src_layout;
 279
 280    /* Number of samples per pixel that have been configured in the render
 281     * target.
 282     */
 283    unsigned rt_samples;
 284
 285    /* MSAA layout that has been configured in the render target. */
 286    intel_msaa_layout rt_layout;
 287
 288    /* Actual number of samples per pixel in the destination image. */
 289    unsigned dst_samples;
 290
 291    /* Actual MSAA layout used by the destination image. */
 292    intel_msaa_layout dst_layout;
 293
 294    /* Type of the data to be read from the texture (one of
 295     * BRW_REGISTER_TYPE_{UD,D,F}).
 296     */
 297    enum brw_reg_type texture_data_type;
 298
 299    /* True if the source image is W tiled.  If true, the surface state for the
 300     * source image must be configured as Y tiled, and tex_samples must be 0.
 301     */
 302    bool src_tiled_w;
 303
 304    /* True if the destination image is W tiled.  If true, the surface state
 305     * for the render target must be configured as Y tiled, and rt_samples must
 306     * be 0.
 307     */
 308    bool dst_tiled_w;
 309
 310    /* True if all source samples should be blended together to produce each
 311     * destination pixel.  If true, src_tiled_w must be false, tex_samples must
 312     * equal src_samples, and tex_samples must be nonzero.
 313     */
 314    bool blend;
 315
 316    /* True if the rectangle being sent through the rendering pipeline might be
 317     * larger than the destination rectangle, so the WM program should kill any
 318     * pixels that are outside the destination rectangle.
 319     */
 320    bool use_kill;
 321
 322    /**
 323     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 324     * than one sample per pixel.
 325     */
 326    bool persample_msaa_dispatch;
 327
 328    /* True for scaled blitting. */
 329    bool blit_scaled;
 330
 331    /* Scale factors between the pixel grid and the grid of samples. We're
 332     * using grid of samples for bilinear filetring in multisample scaled blits.
 333     */
 334    float x_scale;
 335    float y_scale;
 336
 337    /* True for blits with filter = GL_LINEAR. */
 338    bool bilinear_filter;
 339 };
 340
 341 /**
 342  * \name BLORP internals
 343  * \{
 344  *
 345  * Used internally by gen6_blorp_exec() and gen7_blorp_exec().
 346  */
 347
 348 void
 349 gen6_blorp_init(struct brw_context *brw);
 350
 351 void
 352 gen6_blorp_emit_vertices(struct brw_context *brw,
 353                          const struct brw_blorp_params *params);
 354
 355 uint32_t
 356 gen6_blorp_emit_blend_state(struct brw_context *brw,
 357                             const struct brw_blorp_params *params);
 358
 359 uint32_t
 360 gen6_blorp_emit_cc_state(struct brw_context *brw);
 361
 362 uint32_t
 363 gen6_blorp_emit_wm_constants(struct brw_context *brw,
 364                              const struct brw_blorp_params *params);
 365
 366 void
 367 gen6_blorp_emit_vs_disable(struct brw_context *brw,
 368                            const struct brw_blorp_params *params);
 369
 370 uint32_t
 371 gen6_blorp_emit_binding_table(struct brw_context *brw,
 372                               uint32_t wm_surf_offset_renderbuffer,
 373                               uint32_t wm_surf_offset_texture);
 374
 375 uint32_t
 376 gen6_blorp_emit_depth_stencil_state(struct brw_context *brw,
 377                                     const struct brw_blorp_params *params);
 378
 379 void
 380 gen6_blorp_emit_gs_disable(struct brw_context *brw,
 381                            const struct brw_blorp_params *params);
 382
 383 void
 384 gen6_blorp_emit_clip_disable(struct brw_context *brw);
 385
 386 void
 387 gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
 388                                   const struct brw_blorp_params *params);
 389
 390 uint32_t
 391 gen6_blorp_emit_sampler_state(struct brw_context *brw,
 392                               unsigned tex_filter, unsigned max_lod,
 393                               bool non_normalized_coords);
 394 void
 395 gen7_blorp_emit_urb_config(struct brw_context *brw);
 396
 397 void
 398 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
 399                                     uint32_t cc_blend_state_offset);
 400
 401 void
 402 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
 403                                  uint32_t cc_state_offset);
 404
 405 void
 406 gen7_blorp_emit_cc_viewport(struct brw_context *brw);
 407
 408 void
 409 gen7_blorp_emit_te_disable(struct brw_context *brw);
 410
 411 void
 412 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 413                                           uint32_t wm_bind_bo_offset);
 414
 415 void
 416 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 417                                           uint32_t sampler_offset);
 418
 419 void
 420 gen7_blorp_emit_clear_params(struct brw_context *brw,
 421                              const struct brw_blorp_params *params);
 422
 423 void
 424 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 425                             uint32_t wm_push_const_offset);
 426
 427 void
 428 gen7_blorp_emit_constant_ps_disable(struct brw_context *brw);
 429
 430 void
 431 gen7_blorp_emit_primitive(struct brw_context *brw,
 432                           const struct brw_blorp_params *params);
 433
 434 /** \} */
 435
 436 #endif /* __cplusplus */