src/mesa/drivers/dri/i965/brw_blorp.h

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #pragma once
  25
  26 #include <stdint.h>
  27
  28 #include "brw_reg.h"
  29 #include "intel_mipmap_tree.h"
  30
  31 struct brw_context;
  32 struct brw_wm_prog_key;
  33
  34 #ifdef __cplusplus
  35 extern "C" {
  36 #endif
  37
  38 void
  39 brw_blorp_blit_miptrees(struct brw_context *brw,
  40                         struct intel_mipmap_tree *src_mt,
  41                         unsigned src_level, unsigned src_layer,
  42                         mesa_format src_format, int src_swizzle,
  43                         struct intel_mipmap_tree *dst_mt,
  44                         unsigned dst_level, unsigned dst_layer,
  45                         mesa_format dst_format,
  46                         float src_x0, float src_y0,
  47                         float src_x1, float src_y1,
  48                         float dst_x0, float dst_y0,
  49                         float dst_x1, float dst_y1,
  50                         GLenum filter, bool mirror_x, bool mirror_y,
  51                         bool decode_srgb, bool encode_srgb);
  52
  53 bool
  54 brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb,
  55                       GLbitfield mask, bool partial_clear, bool encode_srgb);
  56
  57 void
  58 brw_blorp_resolve_color(struct brw_context *brw,
  59                         struct intel_mipmap_tree *mt);
  60
  61 /**
  62  * Binding table indices used by BLORP.
  63  */
  64 enum {
  65    BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
  66    BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX,
  67    BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
  68 };
  69
  70 struct brw_blorp_surface_info
  71 {
  72    struct intel_mipmap_tree *mt;
  73
  74    struct isl_surf surf;
  75
  76    struct isl_surf aux_surf;
  77    enum isl_aux_usage aux_usage;
  78
  79    /**
  80     * The miplevel to use.
  81     */
  82    uint32_t level;
  83
  84    /**
  85     * The 2D layer within the miplevel. Combined, level and layer define the
  86     * 2D miptree slice to use.
  87     *
  88     * Note: if mt is a 2D multisample array texture on Gen7+ using
  89     * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, layer is the physical
  90     * layer holding sample 0.  So, for example, if mt->num_samples == 4, then
  91     * logical layer n corresponds to layer == 4*n.
  92     */
  93    uint32_t layer;
  94
  95    /**
  96     * Width of the miplevel to be used.  For surfaces using
  97     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
  98     */
  99    uint32_t width;
 100
 101    /**
 102     * Height of the miplevel to be used.  For surfaces using
 103     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
 104     */
 105    uint32_t height;
 106
 107    /**
 108     * X offset within the surface to texture from (or render to).  For
 109     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
 110     * pixels.
 111     */
 112    uint32_t x_offset;
 113
 114    /**
 115     * Y offset within the surface to texture from (or render to).  For
 116     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
 117     * pixels.
 118     */
 119    uint32_t y_offset;
 120
 121    /* Setting this flag indicates that the buffer's contents are W-tiled
 122     * stencil data, but the surface state should be set up for Y tiled
 123     * MESA_FORMAT_R_UNORM8 data (this is necessary because surface states don't
 124     * support W tiling).
 125     *
 126     * Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of
 127     * MESA_FORMAT_R_UNORM8 data are 128 pixels wide by 32 pixels high, the width and
 128     * pitch stored in the surface state will be multiplied by 2, and the
 129     * height will be halved.  Also, since W and Y tiles store their data in a
 130     * different order, the width and height will be rounded up to a multiple
 131     * of the tile size, to ensure that the WM program can access the full
 132     * width and height of the buffer.
 133     */
 134    bool map_stencil_as_y_tiled;
 135
 136    unsigned num_samples;
 137
 138    /**
 139     * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
 140     * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
 141     *
 142     * If ALL_SLICES_AT_EACH_LOD is set, then ARYSPC_LOD0 can be used. Ignored
 143     * prior to Gen7.
 144     */
 145    enum miptree_array_layout array_layout;
 146
 147    /**
 148     * Format that should be used when setting up the surface state for this
 149     * surface.  Should correspond to one of the BRW_SURFACEFORMAT_* enums.
 150     */
 151    uint32_t brw_surfaceformat;
 152
 153    /**
 154     * For MSAA surfaces, MSAA layout that should be used when setting up the
 155     * surface state for this surface.
 156     */
 157    enum intel_msaa_layout msaa_layout;
 158
 159    /**
 160     * In order to support cases where RGBA format is backing client requested
 161     * RGB, one needs to have means to force alpha channel to one when user
 162     * requested RGB surface is used as blit source. This is possible by
 163     * setting source swizzle for the texture surface.
 164     */
 165    int swizzle;
 166 };
 167
 168 void
 169 brw_blorp_surface_info_init(struct brw_context *brw,
 170                             struct brw_blorp_surface_info *info,
 171                             struct intel_mipmap_tree *mt,
 172                             unsigned int level, unsigned int layer,
 173                             mesa_format format, bool is_render_target);
 174
 175 uint32_t
 176 brw_blorp_compute_tile_offsets(const struct brw_blorp_surface_info *info,
 177                                uint32_t *tile_x, uint32_t *tile_y);
 178
 179
 180
 181 struct brw_blorp_coord_transform
 182 {
 183    float multiplier;
 184    float offset;
 185 };
 186
 187 /**
 188  * Bounding rectangle telling pixel discard which pixels are not to be
 189  * touched. This is needed in when surfaces are configured as something else
 190  * what they really are:
 191  *
 192  *    - writing W-tiled stencil as Y-tiled
 193  *    - writing interleaved multisampled as single sampled.
 194  *
 195  * See blorp_nir_discard_if_outside_rect().
 196  */
 197 struct brw_blorp_discard_rect
 198 {
 199    uint32_t x0;
 200    uint32_t x1;
 201    uint32_t y0;
 202    uint32_t y1;
 203 };
 204
 205 /**
 206  * Grid needed for blended and scaled blits of integer formats, see
 207  * blorp_nir_manual_blend_bilinear().
 208  */
 209 struct brw_blorp_rect_grid
 210 {
 211    float x1;
 212    float y1;
 213    float pad[2];
 214 };
 215
 216 struct brw_blorp_wm_inputs
 217 {
 218    struct brw_blorp_discard_rect discard_rect;
 219    struct brw_blorp_rect_grid rect_grid;
 220    struct brw_blorp_coord_transform coord_transform[2];
 221
 222    /* Minimum layer setting works for all the textures types but texture_3d
 223     * for which the setting has no effect. Use the z-coordinate instead.
 224     */
 225    uint32_t src_z;
 226
 227    /* Pad out to an integral number of registers */
 228    uint32_t pad[3];
 229 };
 230
 231 struct brw_blorp_prog_data
 232 {
 233    bool dispatch_8;
 234    bool dispatch_16;
 235
 236    uint8_t first_curbe_grf_0;
 237    uint8_t first_curbe_grf_2;
 238
 239    uint32_t ksp_offset_2;
 240
 241    /**
 242     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 243     * than one sample per pixel.
 244     */
 245    bool persample_msaa_dispatch;
 246
 247    /**
 248     * Mask of which FS inputs are marked flat by the shader source.  This is
 249     * needed for setting up 3DSTATE_SF/SBE.
 250     */
 251    uint32_t flat_inputs;
 252    unsigned num_varying_inputs;
 253    GLbitfield64 inputs_read;
 254 };
 255
 256 static inline unsigned
 257 brw_blorp_get_urb_length(const struct brw_blorp_prog_data *prog_data)
 258 {
 259    if (prog_data == NULL)
 260       return 1;
 261
 262    /* From the BSpec: 3D Pipeline - Strips and Fans - 3DSTATE_SBE
 263     *
 264     * read_length = ceiling((max_source_attr+1)/2)
 265     */
 266    return MAX2((prog_data->num_varying_inputs + 1) / 2, 1);
 267 }
 268
 269 struct brw_blorp_params
 270 {
 271    uint32_t x0;
 272    uint32_t y0;
 273    uint32_t x1;
 274    uint32_t y1;
 275    struct brw_blorp_surface_info depth;
 276    uint32_t depth_format;
 277    struct brw_blorp_surface_info src;
 278    struct brw_blorp_surface_info dst;
 279    enum gen6_hiz_op hiz_op;
 280    union {
 281       unsigned fast_clear_op;
 282       unsigned resolve_type;
 283    };
 284    bool color_write_disable[4];
 285    struct brw_blorp_wm_inputs wm_inputs;
 286    unsigned num_draw_buffers;
 287    unsigned num_layers;
 288    uint32_t wm_prog_kernel;
 289    struct brw_blorp_prog_data *wm_prog_data;
 290 };
 291
 292 void
 293 brw_blorp_params_init(struct brw_blorp_params *params);
 294
 295 void
 296 brw_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params);
 297
 298 void
 299 gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 300                     unsigned level, unsigned layer, enum gen6_hiz_op op);
 301
 302 void
 303 gen6_blorp_exec(struct brw_context *brw,
 304                 const struct brw_blorp_params *params);
 305
 306 void
 307 gen7_blorp_exec(struct brw_context *brw,
 308                 const struct brw_blorp_params *params);
 309
 310 void
 311 gen8_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params);
 312
 313 struct brw_blorp_blit_prog_key
 314 {
 315    /* Number of samples per pixel that have been configured in the surface
 316     * state for texturing from.
 317     */
 318    unsigned tex_samples;
 319
 320    /* MSAA layout that has been configured in the surface state for texturing
 321     * from.
 322     */
 323    enum intel_msaa_layout tex_layout;
 324
 325    /* Actual number of samples per pixel in the source image. */
 326    unsigned src_samples;
 327
 328    /* Actual MSAA layout used by the source image. */
 329    enum intel_msaa_layout src_layout;
 330
 331    /* Number of samples per pixel that have been configured in the render
 332     * target.
 333     */
 334    unsigned rt_samples;
 335
 336    /* MSAA layout that has been configured in the render target. */
 337    enum intel_msaa_layout rt_layout;
 338
 339    /* Actual number of samples per pixel in the destination image. */
 340    unsigned dst_samples;
 341
 342    /* Actual MSAA layout used by the destination image. */
 343    enum intel_msaa_layout dst_layout;
 344
 345    /* Type of the data to be read from the texture (one of
 346     * BRW_REGISTER_TYPE_{UD,D,F}).
 347     */
 348    enum brw_reg_type texture_data_type;
 349
 350    /* True if the source image is W tiled.  If true, the surface state for the
 351     * source image must be configured as Y tiled, and tex_samples must be 0.
 352     */
 353    bool src_tiled_w;
 354
 355    /* True if the destination image is W tiled.  If true, the surface state
 356     * for the render target must be configured as Y tiled, and rt_samples must
 357     * be 0.
 358     */
 359    bool dst_tiled_w;
 360
 361    /* True if all source samples should be blended together to produce each
 362     * destination pixel.  If true, src_tiled_w must be false, tex_samples must
 363     * equal src_samples, and tex_samples must be nonzero.
 364     */
 365    bool blend;
 366
 367    /* True if the rectangle being sent through the rendering pipeline might be
 368     * larger than the destination rectangle, so the WM program should kill any
 369     * pixels that are outside the destination rectangle.
 370     */
 371    bool use_kill;
 372
 373    /**
 374     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 375     * than one sample per pixel.
 376     */
 377    bool persample_msaa_dispatch;
 378
 379    /* True for scaled blitting. */
 380    bool blit_scaled;
 381
 382    /* Scale factors between the pixel grid and the grid of samples. We're
 383     * using grid of samples for bilinear filetring in multisample scaled blits.
 384     */
 385    float x_scale;
 386    float y_scale;
 387
 388    /* True for blits with filter = GL_LINEAR. */
 389    bool bilinear_filter;
 390 };
 391
 392 /**
 393  * \name BLORP internals
 394  * \{
 395  *
 396  * Used internally by gen6_blorp_exec() and gen7_blorp_exec().
 397  */
 398
 399 void brw_blorp_init_wm_prog_key(struct brw_wm_prog_key *wm_key);
 400
 401 const unsigned *
 402 brw_blorp_compile_nir_shader(struct brw_context *brw, struct nir_shader *nir,
 403                              const struct brw_wm_prog_key *wm_key,
 404                              bool use_repclear,
 405                              struct brw_blorp_prog_data *prog_data,
 406                              unsigned *program_size);
 407
 408 uint32_t
 409 brw_blorp_emit_surface_state(struct brw_context *brw,
 410                              const struct brw_blorp_surface_info *surface,
 411                              uint32_t read_domains, uint32_t write_domain,
 412                              bool is_render_target);
 413
 414 void
 415 gen6_blorp_init(struct brw_context *brw);
 416
 417 void
 418 gen6_blorp_emit_vertices(struct brw_context *brw,
 419                          const struct brw_blorp_params *params);
 420
 421 uint32_t
 422 gen6_blorp_emit_blend_state(struct brw_context *brw,
 423                             const struct brw_blorp_params *params);
 424
 425 uint32_t
 426 gen6_blorp_emit_cc_state(struct brw_context *brw);
 427
 428 uint32_t
 429 gen6_blorp_emit_wm_constants(struct brw_context *brw,
 430                              const struct brw_blorp_params *params);
 431
 432 void
 433 gen6_blorp_emit_vs_disable(struct brw_context *brw,
 434                            const struct brw_blorp_params *params);
 435
 436 uint32_t
 437 gen6_blorp_emit_binding_table(struct brw_context *brw,
 438                               uint32_t wm_surf_offset_renderbuffer,
 439                               uint32_t wm_surf_offset_texture);
 440
 441 uint32_t
 442 gen6_blorp_emit_depth_stencil_state(struct brw_context *brw,
 443                                     const struct brw_blorp_params *params);
 444
 445 void
 446 gen6_blorp_emit_gs_disable(struct brw_context *brw,
 447                            const struct brw_blorp_params *params);
 448
 449 void
 450 gen6_blorp_emit_clip_disable(struct brw_context *brw);
 451
 452 void
 453 gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
 454                                   const struct brw_blorp_params *params);
 455
 456 uint32_t
 457 gen6_blorp_emit_sampler_state(struct brw_context *brw,
 458                               unsigned tex_filter, unsigned max_lod,
 459                               bool non_normalized_coords);
 460 void
 461 gen7_blorp_emit_urb_config(struct brw_context *brw,
 462                            const struct brw_blorp_params *params);
 463
 464 void
 465 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
 466                                     uint32_t cc_blend_state_offset);
 467
 468 void
 469 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
 470                                  uint32_t cc_state_offset);
 471
 472 void
 473 gen7_blorp_emit_cc_viewport(struct brw_context *brw);
 474
 475 void
 476 gen7_blorp_emit_te_disable(struct brw_context *brw);
 477
 478 void
 479 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 480                                           uint32_t wm_bind_bo_offset);
 481
 482 void
 483 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 484                                           uint32_t sampler_offset);
 485
 486 void
 487 gen7_blorp_emit_clear_params(struct brw_context *brw,
 488                              const struct brw_blorp_params *params);
 489
 490 void
 491 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 492                             uint32_t wm_push_const_offset);
 493
 494 void
 495 gen7_blorp_emit_constant_ps_disable(struct brw_context *brw);
 496
 497 void
 498 gen7_blorp_emit_primitive(struct brw_context *brw,
 499                           const struct brw_blorp_params *params);
 500
 501 /** \} */
 502
 503 #ifdef __cplusplus
 504 } /* end extern "C" */
 505 #endif /* __cplusplus */