2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/teximage.h"
25 #include "main/fbobject.h"
26 #include "main/renderbuffer.h"
28 #include "intel_fbo.h"
30 #include "brw_blorp.h"
31 #include "brw_context.h"
32 #include "brw_blorp_blit_eu.h"
33 #include "brw_state.h"
34 #include "brw_meta_util.h"
36 #define FILE_DEBUG_FLAG DEBUG_BLORP
38 static struct intel_mipmap_tree
*
39 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
41 struct intel_mipmap_tree
*mt
= irb
->mt
;
42 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
49 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
50 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
51 * the physical layer holding sample 0. So, for example, if
52 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
56 brw_blorp_blit_miptrees(struct brw_context
*brw
,
57 struct intel_mipmap_tree
*src_mt
,
58 unsigned src_level
, unsigned src_layer
,
59 struct intel_mipmap_tree
*dst_mt
,
60 unsigned dst_level
, unsigned dst_layer
,
61 float src_x0
, float src_y0
,
62 float src_x1
, float src_y1
,
63 float dst_x0
, float dst_y0
,
64 float dst_x1
, float dst_y1
,
65 GLenum filter
, bool mirror_x
, bool mirror_y
)
67 /* Get ready to blit. This includes depth resolving the src and dst
68 * buffers if necessary. Note: it's not necessary to do a color resolve on
69 * the destination buffer because we use the standard render path to render
70 * to destination color buffers, and the standard render path is
73 intel_miptree_resolve_color(brw
, src_mt
);
74 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_layer
);
75 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_layer
);
77 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
78 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
80 src_mt
->num_samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
81 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
82 dst_mt
->num_samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
83 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
86 brw_blorp_blit_params
params(brw
,
87 src_mt
, src_level
, src_layer
,
88 dst_mt
, dst_level
, dst_layer
,
93 filter
, mirror_x
, mirror_y
);
94 brw_blorp_exec(brw
, ¶ms
);
96 intel_miptree_slice_set_needs_hiz_resolve(dst_mt
, dst_level
, dst_layer
);
100 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
101 struct intel_renderbuffer
*src_irb
,
102 struct intel_renderbuffer
*dst_irb
,
103 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
104 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
105 GLenum filter
, bool mirror_x
, bool mirror_y
)
107 /* Find source/dst miptrees */
108 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
109 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
112 brw_blorp_blit_miptrees(brw
,
113 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
114 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
115 srcX0
, srcY0
, srcX1
, srcY1
,
116 dstX0
, dstY0
, dstX1
, dstY1
,
117 filter
, mirror_x
, mirror_y
);
119 dst_irb
->need_downsample
= true;
123 color_formats_match(mesa_format src_format
, mesa_format dst_format
)
125 mesa_format linear_src_format
= _mesa_get_srgb_format_linear(src_format
);
126 mesa_format linear_dst_format
= _mesa_get_srgb_format_linear(dst_format
);
128 /* Normally, we require the formats to be equal. However, we also support
129 * blitting from ARGB to XRGB (discarding alpha), and from XRGB to ARGB
130 * (overriding alpha to 1.0 via blending).
132 return linear_src_format
== linear_dst_format
||
133 (linear_src_format
== MESA_FORMAT_B8G8R8X8_UNORM
&&
134 linear_dst_format
== MESA_FORMAT_B8G8R8A8_UNORM
) ||
135 (linear_src_format
== MESA_FORMAT_B8G8R8A8_UNORM
&&
136 linear_dst_format
== MESA_FORMAT_B8G8R8X8_UNORM
);
140 formats_match(GLbitfield buffer_bit
, struct intel_renderbuffer
*src_irb
,
141 struct intel_renderbuffer
*dst_irb
)
143 /* Note: don't just check gl_renderbuffer::Format, because in some cases
144 * multiple gl_formats resolve to the same native type in the miptree (for
145 * example MESA_FORMAT_Z24_UNORM_X8_UINT and MESA_FORMAT_Z24_UNORM_S8_UINT), and we can blit
146 * between those formats.
148 mesa_format src_format
= find_miptree(buffer_bit
, src_irb
)->format
;
149 mesa_format dst_format
= find_miptree(buffer_bit
, dst_irb
)->format
;
151 return color_formats_match(src_format
, dst_format
);
155 try_blorp_blit(struct brw_context
*brw
,
156 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
157 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
158 GLenum filter
, GLbitfield buffer_bit
)
160 struct gl_context
*ctx
= &brw
->ctx
;
162 /* Sync up the state of window system buffers. We need to do this before
163 * we go looking for the buffers.
165 intel_prepare_render(brw
);
167 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
168 const struct gl_framebuffer
*draw_fb
= ctx
->DrawBuffer
;
170 bool mirror_x
, mirror_y
;
171 if (brw_meta_mirror_clip_and_scissor(ctx
,
172 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
173 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
174 &mirror_x
, &mirror_y
))
178 struct intel_renderbuffer
*src_irb
;
179 struct intel_renderbuffer
*dst_irb
;
180 switch (buffer_bit
) {
181 case GL_COLOR_BUFFER_BIT
:
182 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
183 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
184 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
185 if (dst_irb
&& !formats_match(buffer_bit
, src_irb
, dst_irb
))
188 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
189 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
191 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
192 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
193 filter
, mirror_x
, mirror_y
);
196 case GL_DEPTH_BUFFER_BIT
:
198 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
200 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
201 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
203 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
204 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
205 filter
, mirror_x
, mirror_y
);
207 case GL_STENCIL_BUFFER_BIT
:
209 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
211 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
212 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
214 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
215 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
216 filter
, mirror_x
, mirror_y
);
226 brw_blorp_copytexsubimage(struct brw_context
*brw
,
227 struct gl_renderbuffer
*src_rb
,
228 struct gl_texture_image
*dst_image
,
230 int srcX0
, int srcY0
,
231 int dstX0
, int dstY0
,
232 int width
, int height
)
234 struct gl_context
*ctx
= &brw
->ctx
;
235 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
236 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
238 /* Sync up the state of window system buffers. We need to do this before
239 * we go looking at the src renderbuffer's miptree.
241 intel_prepare_render(brw
);
243 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
244 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
246 /* BLORP is not supported before Gen6. */
247 if (brw
->gen
< 6 || brw
->gen
>= 8)
250 if (_mesa_get_format_base_format(src_mt
->format
) !=
251 _mesa_get_format_base_format(dst_mt
->format
)) {
255 /* We can't handle format conversions between Z24 and other formats since
256 * we have to lie about the surface format. See the comments in
257 * brw_blorp_surface_info::set().
259 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
260 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
)) {
264 if (!brw
->format_supported_as_render_target
[dst_mt
->format
])
267 /* Source clipping shouldn't be necessary, since copytexsubimage (in
268 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
271 * Destination clipping shouldn't be necessary since the restrictions on
272 * glCopyTexSubImage prevent the user from specifying a destination rectangle
273 * that falls outside the bounds of the destination texture.
274 * See error_check_subtexture_dimensions().
277 int srcY1
= srcY0
+ height
;
278 int srcX1
= srcX0
+ width
;
279 int dstX1
= dstX0
+ width
;
280 int dstY1
= dstY0
+ height
;
282 /* Account for the fact that in the system framebuffer, the origin is at
285 bool mirror_y
= false;
286 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
287 GLint tmp
= src_rb
->Height
- srcY0
;
288 srcY0
= src_rb
->Height
- srcY1
;
293 /* Account for face selection and texture view MinLayer */
294 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
295 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
297 brw_blorp_blit_miptrees(brw
,
298 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
299 dst_mt
, dst_level
, dst_slice
,
300 srcX0
, srcY0
, srcX1
, srcY1
,
301 dstX0
, dstY0
, dstX1
, dstY1
,
302 GL_NEAREST
, false, mirror_y
);
304 /* If we're copying to a packed depth stencil texture and the source
305 * framebuffer has separate stencil, we need to also copy the stencil data
308 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
309 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
311 src_irb
= intel_renderbuffer(src_rb
);
312 src_mt
= src_irb
->mt
;
314 if (src_mt
->stencil_mt
)
315 src_mt
= src_mt
->stencil_mt
;
316 if (dst_mt
->stencil_mt
)
317 dst_mt
= dst_mt
->stencil_mt
;
319 if (src_mt
!= dst_mt
) {
320 brw_blorp_blit_miptrees(brw
,
321 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
322 dst_mt
, dst_level
, dst_slice
,
323 srcX0
, srcY0
, srcX1
, srcY1
,
324 dstX0
, dstY0
, dstX1
, dstY1
,
325 GL_NEAREST
, false, mirror_y
);
334 brw_blorp_framebuffer(struct brw_context
*brw
,
335 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
336 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
337 GLbitfield mask
, GLenum filter
)
339 /* BLORP is not supported before Gen6. */
340 if (brw
->gen
< 6 || brw
->gen
>= 8)
343 static GLbitfield buffer_bits
[] = {
346 GL_STENCIL_BUFFER_BIT
,
349 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
350 if ((mask
& buffer_bits
[i
]) &&
352 srcX0
, srcY0
, srcX1
, srcY1
,
353 dstX0
, dstY0
, dstX1
, dstY1
,
354 filter
, buffer_bits
[i
])) {
355 mask
&= ~buffer_bits
[i
];
364 * Enum to specify the order of arguments in a sampler message
366 enum sampler_message_arg
368 SAMPLER_MESSAGE_ARG_U_FLOAT
,
369 SAMPLER_MESSAGE_ARG_V_FLOAT
,
370 SAMPLER_MESSAGE_ARG_U_INT
,
371 SAMPLER_MESSAGE_ARG_V_INT
,
372 SAMPLER_MESSAGE_ARG_SI_INT
,
373 SAMPLER_MESSAGE_ARG_MCS_INT
,
374 SAMPLER_MESSAGE_ARG_ZERO_INT
,
378 * Generator for WM programs used in BLORP blits.
380 * The bulk of the work done by the WM program is to wrap and unwrap the
381 * coordinate transformations used by the hardware to store surfaces in
382 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
383 * sample index for a multisampled surface) to a memory offset by the
384 * following formulas:
386 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
387 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
389 * For a single-sampled surface, or for a multisampled surface using
390 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
393 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
394 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
395 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
396 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
398 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
399 * embeds the sample number into bit 1 of the X and Y coordinates:
401 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
402 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
403 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
404 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
405 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
406 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
407 * S = (Y & 0b10) | (X & 0b10) >> 1
409 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
410 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
413 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
414 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
415 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
416 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
417 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
418 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
419 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
421 * For X tiling, tile() combines together the low-order bits of the X and Y
422 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
423 * bytes wide and 8 rows high:
425 * tile(x_tiled, X, Y, S) = A
426 * where A = tile_num << 12 | offset
427 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
428 * offset = (Y' & 0b111) << 9
429 * | (X & 0b111111111)
431 * Y' = Y + S * qpitch
432 * detile(x_tiled, A) = (X, Y, S)
436 * Y' = (tile_num / tile_pitch) << 3
437 * | (A & 0b111000000000) >> 9
438 * X' = (tile_num % tile_pitch) << 9
439 * | (A & 0b111111111)
441 * (In all tiling formulas, cpp is the number of bytes occupied by a single
442 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
443 * to fill the width of the surface, and qpitch is the spacing (in rows)
444 * between array slices).
446 * For Y tiling, tile() combines together the low-order bits of the X and Y
447 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
448 * bytes wide and 32 rows high:
450 * tile(y_tiled, X, Y, S) = A
451 * where A = tile_num << 12 | offset
452 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
453 * offset = (X' & 0b1110000) << 5
454 * | (Y' & 0b11111) << 4
457 * Y' = Y + S * qpitch
458 * detile(y_tiled, A) = (X, Y, S)
462 * Y' = (tile_num / tile_pitch) << 5
463 * | (A & 0b111110000) >> 4
464 * X' = (tile_num % tile_pitch) << 7
465 * | (A & 0b111000000000) >> 5
468 * For W tiling, tile() combines together the low-order bits of the X and Y
469 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
470 * bytes wide and 64 rows high (note that W tiling is only used for stencil
471 * buffers, which always have cpp = 1 and S=0):
473 * tile(w_tiled, X, Y, S) = A
474 * where A = tile_num << 12 | offset
475 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
476 * offset = (X' & 0b111000) << 6
477 * | (Y' & 0b111100) << 3
478 * | (X' & 0b100) << 2
484 * Y' = Y + S * qpitch
485 * detile(w_tiled, A) = (X, Y, S)
486 * where X = X' / cpp = X'
487 * Y = Y' % qpitch = Y'
489 * Y' = (tile_num / tile_pitch) << 6
490 * | (A & 0b111100000) >> 3
491 * | (A & 0b1000) >> 2
493 * X' = (tile_num % tile_pitch) << 6
494 * | (A & 0b111000000000) >> 6
495 * | (A & 0b10000) >> 2
499 * Finally, for a non-tiled surface, tile() simply combines together the X and
500 * Y coordinates in the natural way:
502 * tile(untiled, X, Y, S) = A
503 * where A = Y * pitch + X'
505 * Y' = Y + S * qpitch
506 * detile(untiled, A) = (X, Y, S)
513 * (In these formulas, pitch is the number of bytes occupied by a single row
516 class brw_blorp_blit_program
: public brw_blorp_eu_emitter
519 brw_blorp_blit_program(struct brw_context
*brw
,
520 const brw_blorp_blit_prog_key
*key
, bool debug_flag
);
522 const GLuint
*compile(struct brw_context
*brw
, GLuint
*program_size
);
524 brw_blorp_prog_data prog_data
;
528 void alloc_push_const_regs(int base_reg
);
529 void compute_frag_coords();
530 void translate_tiling(bool old_tiled_w
, bool new_tiled_w
);
531 void encode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
532 void decode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
533 void translate_dst_to_src();
534 void clamp_tex_coords(struct brw_reg regX
, struct brw_reg regY
,
535 struct brw_reg clampX0
, struct brw_reg clampY0
,
536 struct brw_reg clampX1
, struct brw_reg clampY1
);
537 void single_to_blend();
538 void manual_blend_average(unsigned num_samples
);
539 void manual_blend_bilinear(unsigned num_samples
);
540 void sample(struct brw_reg dst
);
541 void texel_fetch(struct brw_reg dst
);
543 void texture_lookup(struct brw_reg dst
, enum opcode op
,
544 const sampler_message_arg
*args
, int num_args
);
545 void render_target_write();
548 * Base-2 logarithm of the maximum number of samples that can be blended.
550 static const unsigned LOG2_MAX_BLEND_SAMPLES
= 3;
552 struct brw_context
*brw
;
553 const brw_blorp_blit_prog_key
*key
;
555 /* Thread dispatch header */
558 /* Pixel X/Y coordinates (always in R1). */
562 struct brw_reg dst_x0
;
563 struct brw_reg dst_x1
;
564 struct brw_reg dst_y0
;
565 struct brw_reg dst_y1
;
566 /* Top right coordinates of the rectangular grid used for scaled blitting */
567 struct brw_reg rect_grid_x1
;
568 struct brw_reg rect_grid_y1
;
570 struct brw_reg multiplier
;
571 struct brw_reg offset
;
572 } x_transform
, y_transform
;
574 /* Data read from texture (4 vec16's per array element) */
575 struct brw_reg texture_data
[LOG2_MAX_BLEND_SAMPLES
+ 1];
577 /* Auxiliary storage for the contents of the MCS surface.
579 * Since the sampler always returns 8 registers worth of data, this is 8
580 * registers wide, even though we only use the first 2 registers of it.
582 struct brw_reg mcs_data
;
584 /* X coordinates. We have two of them so that we can perform coordinate
585 * transformations easily.
587 struct brw_reg x_coords
[2];
589 /* Y coordinates. We have two of them so that we can perform coordinate
590 * transformations easily.
592 struct brw_reg y_coords
[2];
594 /* X, Y coordinates of the pixel from which we need to fetch the specific
595 * sample. These are used for multisample scaled blitting.
597 struct brw_reg x_sample_coords
;
598 struct brw_reg y_sample_coords
;
600 /* Fractional parts of the x and y coordinates, used as bilinear interpolation coefficients */
601 struct brw_reg x_frac
;
602 struct brw_reg y_frac
;
604 /* Which element of x_coords and y_coords is currently in use.
608 /* True if, at the point in the program currently being compiled, the
609 * sample index is known to be zero.
613 /* Register storing the sample index when s_is_zero is false. */
614 struct brw_reg sample_index
;
620 /* MRF used for sampling and render target writes */
624 brw_blorp_blit_program::brw_blorp_blit_program(
625 struct brw_context
*brw
,
626 const brw_blorp_blit_prog_key
*key
,
628 : brw_blorp_eu_emitter(brw
, debug_flag
),
635 brw_blorp_blit_program::compile(struct brw_context
*brw
,
636 GLuint
*program_size
)
639 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
640 /* If the destination image is W tiled and multisampled, then the thread
641 * must be dispatched once per sample, not once per pixel. This is
642 * necessary because after conversion between W and Y tiling, there's no
643 * guarantee that all samples corresponding to a single pixel will still
646 assert(key
->persample_msaa_dispatch
);
650 /* We are blending, which means we won't have an opportunity to
651 * translate the tiling and sample count for the texture surface. So
652 * the surface state for the texture must be configured with the correct
653 * tiling and sample count.
655 assert(!key
->src_tiled_w
);
656 assert(key
->tex_samples
== key
->src_samples
);
657 assert(key
->tex_layout
== key
->src_layout
);
658 assert(key
->tex_samples
> 0);
661 if (key
->persample_msaa_dispatch
) {
662 /* It only makes sense to do persample dispatch if the render target is
663 * configured as multisampled.
665 assert(key
->rt_samples
> 0);
668 /* Make sure layout is consistent with sample count */
669 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
670 (key
->tex_samples
== 0));
671 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
672 (key
->rt_samples
== 0));
673 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
674 (key
->src_samples
== 0));
675 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
676 (key
->dst_samples
== 0));
678 /* Set up prog_data */
679 memset(&prog_data
, 0, sizeof(prog_data
));
680 prog_data
.persample_msaa_dispatch
= key
->persample_msaa_dispatch
;
683 compute_frag_coords();
685 /* Render target and texture hardware don't support W tiling. */
686 const bool rt_tiled_w
= false;
687 const bool tex_tiled_w
= false;
689 /* The address that data will be written to is determined by the
690 * coordinates supplied to the WM thread and the tiling and sample count of
691 * the render target, according to the formula:
693 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
695 * If the actual tiling and sample count of the destination surface are not
696 * the same as the configuration of the render target, then these
697 * coordinates are wrong and we have to adjust them to compensate for the
700 if (rt_tiled_w
!= key
->dst_tiled_w
||
701 key
->rt_samples
!= key
->dst_samples
||
702 key
->rt_layout
!= key
->dst_layout
) {
703 encode_msaa(key
->rt_samples
, key
->rt_layout
);
704 /* Now (X, Y, S) = detile(rt_tiling, offset) */
705 translate_tiling(rt_tiled_w
, key
->dst_tiled_w
);
706 /* Now (X, Y, S) = detile(dst_tiling, offset) */
707 decode_msaa(key
->dst_samples
, key
->dst_layout
);
710 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
712 * That is: X, Y and S now contain the true coordinates and sample index of
713 * the data that the WM thread should output.
715 * If we need to kill pixels that are outside the destination rectangle,
716 * now is the time to do it.
720 emit_kill_if_outside_rect(x_coords
[xy_coord_index
],
721 y_coords
[xy_coord_index
],
722 dst_x0
, dst_x1
, dst_y0
, dst_y1
);
724 /* Next, apply a translation to obtain coordinates in the source image. */
725 translate_dst_to_src();
727 /* If the source image is not multisampled, then we want to fetch sample
728 * number 0, because that's the only sample there is.
730 if (key
->src_samples
== 0)
733 /* X, Y, and S are now the coordinates of the pixel in the source image
734 * that we want to texture from. Exception: if we are blending, then S is
735 * irrelevant, because we are going to fetch all samples.
737 if (key
->blend
&& !key
->blit_scaled
) {
739 /* Gen6 hardware an automatically blend using the SAMPLE message */
741 sample(texture_data
[0]);
743 /* Gen7+ hardware doesn't automaticaly blend. */
744 manual_blend_average(key
->src_samples
);
746 } else if(key
->blend
&& key
->blit_scaled
) {
747 manual_blend_bilinear(key
->src_samples
);
749 /* We aren't blending, which means we just want to fetch a single sample
750 * from the source surface. The address that we want to fetch from is
751 * related to the X, Y and S values according to the formula:
753 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
755 * If the actual tiling and sample count of the source surface are not
756 * the same as the configuration of the texture, then we need to adjust
757 * the coordinates to compensate for the difference.
759 if ((tex_tiled_w
!= key
->src_tiled_w
||
760 key
->tex_samples
!= key
->src_samples
||
761 key
->tex_layout
!= key
->src_layout
) &&
762 !key
->bilinear_filter
) {
763 encode_msaa(key
->src_samples
, key
->src_layout
);
764 /* Now (X, Y, S) = detile(src_tiling, offset) */
765 translate_tiling(key
->src_tiled_w
, tex_tiled_w
);
766 /* Now (X, Y, S) = detile(tex_tiling, offset) */
767 decode_msaa(key
->tex_samples
, key
->tex_layout
);
770 if (key
->bilinear_filter
) {
771 sample(texture_data
[0]);
774 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
776 * In other words: X, Y, and S now contain values which, when passed to
777 * the texturing unit, will cause data to be read from the correct
778 * memory location. So we can fetch the texel now.
780 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
782 texel_fetch(texture_data
[0]);
786 /* Finally, write the fetched (or blended) value to the render target and
787 * terminate the thread.
789 render_target_write();
791 return get_program(program_size
);
795 brw_blorp_blit_program::alloc_push_const_regs(int base_reg
)
797 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
798 #define ALLOC_REG(name, type) \
800 retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, \
801 base_reg + CONST_LOC(name) / 32, \
802 (CONST_LOC(name) % 32) / 4), type)
804 ALLOC_REG(dst_x0
, BRW_REGISTER_TYPE_UD
);
805 ALLOC_REG(dst_x1
, BRW_REGISTER_TYPE_UD
);
806 ALLOC_REG(dst_y0
, BRW_REGISTER_TYPE_UD
);
807 ALLOC_REG(dst_y1
, BRW_REGISTER_TYPE_UD
);
808 ALLOC_REG(rect_grid_x1
, BRW_REGISTER_TYPE_F
);
809 ALLOC_REG(rect_grid_y1
, BRW_REGISTER_TYPE_F
);
810 ALLOC_REG(x_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
811 ALLOC_REG(x_transform
.offset
, BRW_REGISTER_TYPE_F
);
812 ALLOC_REG(y_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
813 ALLOC_REG(y_transform
.offset
, BRW_REGISTER_TYPE_F
);
819 brw_blorp_blit_program::alloc_regs()
822 this->R0
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
823 this->R1
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
824 prog_data
.first_curbe_grf
= reg
;
825 alloc_push_const_regs(reg
);
826 reg
+= BRW_BLORP_NUM_PUSH_CONST_REGS
;
827 for (unsigned i
= 0; i
< ARRAY_SIZE(texture_data
); ++i
) {
828 this->texture_data
[i
] =
829 retype(vec16(brw_vec8_grf(reg
, 0)), key
->texture_data_type
);
833 retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
); reg
+= 8;
835 for (int i
= 0; i
< 2; ++i
) {
837 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
840 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
844 if (key
->blit_scaled
&& key
->blend
) {
845 this->x_sample_coords
= brw_vec8_grf(reg
, 0);
847 this->y_sample_coords
= brw_vec8_grf(reg
, 0);
849 this->x_frac
= brw_vec8_grf(reg
, 0);
851 this->y_frac
= brw_vec8_grf(reg
, 0);
855 this->xy_coord_index
= 0;
857 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
859 this->t1
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
861 this->t2
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
864 /* Make sure we didn't run out of registers */
865 assert(reg
<= GEN7_MRF_HACK_START
);
868 this->base_mrf
= mrf
;
871 /* In the code that follows, X and Y can be used to quickly refer to the
872 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
873 * prime") to the inactive elements.
875 * S can be used to quickly refer to sample_index.
877 #define X x_coords[xy_coord_index]
878 #define Y y_coords[xy_coord_index]
879 #define Xp x_coords[!xy_coord_index]
880 #define Yp y_coords[!xy_coord_index]
881 #define S sample_index
883 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
884 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
886 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
889 * Emit code to compute the X and Y coordinates of the pixels being rendered
890 * by this WM invocation.
892 * Assuming the render target is set up for Y tiling, these (X, Y) values are
893 * related to the address offset where outputs will be written by the formula:
895 * (X, Y, S) = decode_msaa(detile(offset)).
897 * (See brw_blorp_blit_program).
900 brw_blorp_blit_program::compute_frag_coords()
902 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
903 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
904 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
905 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
907 * Pixels within a subspan are laid out in this arrangement:
911 * So, to compute the coordinates of each pixel, we need to read every 2nd
912 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
913 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
914 * In other words, the data we want to access is R1.4<2;4,0>UW.
916 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
917 * result, since pixels n+1 and n+3 are in the right half of the subspan.
919 emit_add(vec16(retype(X
, BRW_REGISTER_TYPE_UW
)),
920 stride(suboffset(R1
, 4), 2, 4, 0), brw_imm_v(0x10101010));
922 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
923 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
924 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
927 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
928 * pixels n+2 and n+3 are in the bottom half of the subspan.
930 emit_add(vec16(retype(Y
, BRW_REGISTER_TYPE_UW
)),
931 stride(suboffset(R1
, 5), 2, 4, 0), brw_imm_v(0x11001100));
933 /* Move the coordinates to UD registers. */
934 emit_mov(vec16(Xp
), retype(X
, BRW_REGISTER_TYPE_UW
));
935 emit_mov(vec16(Yp
), retype(Y
, BRW_REGISTER_TYPE_UW
));
938 if (key
->persample_msaa_dispatch
) {
939 switch (key
->rt_samples
) {
941 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
942 * Therefore, subspan 0 will represent sample 0, subspan 1 will
943 * represent sample 1, and so on.
945 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
946 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to
947 * populate a temporary variable with the sequence (0, 1, 2, 3), and
948 * then copy from it using vstride=1, width=4, hstride=0.
950 struct brw_reg t1_uw1
= retype(t1
, BRW_REGISTER_TYPE_UW
);
951 emit_mov(vec16(t1_uw1
), brw_imm_v(0x3210));
952 /* Move to UD sample_index register. */
953 emit_mov_8(S
, stride(t1_uw1
, 1, 4, 0));
954 emit_mov_8(offset(S
, 1), suboffset(stride(t1_uw1
, 1, 4, 0), 2));
958 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
959 * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
960 * subspan 1 will represent sample 1, and so on. We can find the
961 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair
962 * Index") and multiplying by two (since samples are always delivered
963 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 &
966 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
967 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
968 * variable with the sequence (0, 1, 2, 3), and then reading from it
969 * using vstride=1, width=4, hstride=0.
971 struct brw_reg t1_ud1
= vec1(retype(t1
, BRW_REGISTER_TYPE_UD
));
972 struct brw_reg t2_uw1
= retype(t2
, BRW_REGISTER_TYPE_UW
);
973 struct brw_reg r0_ud1
= vec1(retype(R0
, BRW_REGISTER_TYPE_UD
));
974 emit_and(t1_ud1
, r0_ud1
, brw_imm_ud(0xc0));
975 emit_shr(t1_ud1
, t1_ud1
, brw_imm_ud(5));
976 emit_mov(vec16(t2_uw1
), brw_imm_v(0x3210));
977 emit_add(vec16(S
), retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
978 stride(t2_uw1
, 1, 4, 0));
979 emit_add_8(offset(S
, 1),
980 retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
981 suboffset(stride(t2_uw1
, 1, 4, 0), 2));
985 assert(!"Unrecognized sample count in "
986 "brw_blorp_blit_program::compute_frag_coords()");
991 /* Either the destination surface is single-sampled, or the WM will be
992 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
993 * per pixel). In either case, it's not meaningful to compute a sample
994 * value. Just set it to 0.
1001 * Emit code to compensate for the difference between Y and W tiling.
1003 * This code modifies the X and Y coordinates according to the formula:
1005 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
1007 * (See brw_blorp_blit_program).
1009 * It can only translate between W and Y tiling, so new_tiling and old_tiling
1010 * are booleans where true represents W tiling and false represents Y tiling.
1013 brw_blorp_blit_program::translate_tiling(bool old_tiled_w
, bool new_tiled_w
)
1015 if (old_tiled_w
== new_tiled_w
)
1018 /* In the code that follows, we can safely assume that S = 0, because W
1019 * tiling formats always use IMS layout.
1024 /* Given X and Y coordinates that describe an address using Y tiling,
1025 * translate to the X and Y coordinates that describe the same address
1028 * If we break down the low order bits of X and Y, using a
1029 * single letter to represent each low-order bit:
1031 * X = A << 7 | 0bBCDEFGH
1032 * Y = J << 5 | 0bKLMNP (1)
1034 * Then we can apply the Y tiling formula to see the memory offset being
1037 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
1039 * If we apply the W detiling formula to this memory location, that the
1040 * corresponding X' and Y' coordinates are:
1042 * X' = A << 6 | 0bBCDPFH (3)
1043 * Y' = J << 6 | 0bKLMNEG
1045 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
1046 * we need to make the following computation:
1048 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
1049 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
1051 emit_and(t1
, X
, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
1052 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
1053 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1054 emit_shl(t2
, t2
, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
1055 emit_or(t1
, t1
, t2
); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
1056 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1057 emit_or(Xp
, t1
, t2
);
1058 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1059 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1060 emit_and(t2
, X
, brw_imm_uw(8)); /* X & 0b1000 */
1061 emit_shr(t2
, t2
, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
1062 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
1063 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1064 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1065 emit_or(Yp
, t1
, t2
);
1068 /* Applying the same logic as above, but in reverse, we obtain the
1071 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
1072 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
1074 emit_and(t1
, X
, brw_imm_uw(0xfffa)); /* X & ~0b101 */
1075 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
1076 emit_and(t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1077 emit_shl(t2
, t2
, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
1078 emit_or(t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
1079 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1080 emit_shl(t2
, t2
, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
1081 emit_or(t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
1083 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1084 emit_or(Xp
, t1
, t2
);
1085 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1086 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1087 emit_and(t2
, X
, brw_imm_uw(4)); /* X & 0b100 */
1088 emit_shr(t2
, t2
, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
1089 emit_or(Yp
, t1
, t2
);
1095 * Emit code to compensate for the difference between MSAA and non-MSAA
1098 * This code modifies the X and Y coordinates according to the formula:
1100 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
1102 * (See brw_blorp_blit_program).
1105 brw_blorp_blit_program::encode_msaa(unsigned num_samples
,
1106 intel_msaa_layout layout
)
1109 case INTEL_MSAA_LAYOUT_NONE
:
1110 /* No translation necessary, and S should already be zero. */
1113 case INTEL_MSAA_LAYOUT_CMS
:
1114 /* We can't compensate for compressed layout since at this point in the
1115 * program we haven't read from the MCS buffer.
1117 assert(!"Bad layout in encode_msaa");
1119 case INTEL_MSAA_LAYOUT_UMS
:
1120 /* No translation necessary. */
1122 case INTEL_MSAA_LAYOUT_IMS
:
1123 switch (num_samples
) {
1125 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1126 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1127 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1129 emit_and(t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1131 emit_and(t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1132 emit_or(t1
, t1
, t2
); /* (X & ~0b1) | (S & 0b1) */
1134 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1) << 1
1136 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1137 emit_or(Xp
, t1
, t2
);
1138 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1139 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1141 emit_and(t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1142 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1144 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1145 emit_or(Yp
, t1
, t2
);
1148 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1149 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
1151 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1153 emit_and(t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1154 emit_shl(t1
, t1
, brw_imm_uw(2)); /* (X & ~0b1) << 2 */
1156 emit_and(t2
, S
, brw_imm_uw(4)); /* S & 0b100 */
1157 emit_or(t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100) */
1158 emit_and(t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1159 emit_shl(t2
, t2
, brw_imm_uw(1)); /* (S & 0b1) << 1 */
1160 emit_or(t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100)
1163 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1164 emit_or(Xp
, t1
, t2
);
1165 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1166 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1168 emit_and(t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1169 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1171 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1172 emit_or(Yp
, t1
, t2
);
1182 * Emit code to compensate for the difference between MSAA and non-MSAA
1185 * This code modifies the X and Y coordinates according to the formula:
1187 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
1189 * (See brw_blorp_blit_program).
1192 brw_blorp_blit_program::decode_msaa(unsigned num_samples
,
1193 intel_msaa_layout layout
)
1196 case INTEL_MSAA_LAYOUT_NONE
:
1197 /* No translation necessary, and S should already be zero. */
1200 case INTEL_MSAA_LAYOUT_CMS
:
1201 /* We can't compensate for compressed layout since at this point in the
1202 * program we don't have access to the MCS buffer.
1204 assert(!"Bad layout in encode_msaa");
1206 case INTEL_MSAA_LAYOUT_UMS
:
1207 /* No translation necessary. */
1209 case INTEL_MSAA_LAYOUT_IMS
:
1211 switch (num_samples
) {
1213 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1214 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1215 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1216 * S = (Y & 0b10) | (X & 0b10) >> 1
1218 emit_and(t1
, X
, brw_imm_uw(0xfffc)); /* X & ~0b11 */
1219 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
1220 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1221 emit_or(Xp
, t1
, t2
);
1222 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1223 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1224 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1225 emit_or(Yp
, t1
, t2
);
1226 emit_and(t1
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1227 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1228 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1232 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1233 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1234 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1235 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1237 emit_and(t1
, X
, brw_imm_uw(0xfff8)); /* X & ~0b111 */
1238 emit_shr(t1
, t1
, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */
1239 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1240 emit_or(Xp
, t1
, t2
);
1241 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1242 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1243 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1244 emit_or(Yp
, t1
, t2
);
1245 emit_and(t1
, X
, brw_imm_uw(4)); /* X & 0b100 */
1246 emit_and(t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1247 emit_or(t1
, t1
, t2
); /* (X & 0b100) | (Y & 0b10) */
1248 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1249 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1260 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1264 brw_blorp_blit_program::translate_dst_to_src()
1266 struct brw_reg X_f
= retype(X
, BRW_REGISTER_TYPE_F
);
1267 struct brw_reg Y_f
= retype(Y
, BRW_REGISTER_TYPE_F
);
1268 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1269 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1271 /* Move the UD coordinates to float registers. */
1274 /* Scale and offset */
1275 emit_mul(X_f
, Xp_f
, x_transform
.multiplier
);
1276 emit_mul(Y_f
, Yp_f
, y_transform
.multiplier
);
1277 emit_add(X_f
, X_f
, x_transform
.offset
);
1278 emit_add(Y_f
, Y_f
, y_transform
.offset
);
1279 if (key
->blit_scaled
&& key
->blend
) {
1280 /* Translate coordinates to lay out the samples in a rectangular grid
1281 * roughly corresponding to sample locations.
1283 emit_mul(X_f
, X_f
, brw_imm_f(key
->x_scale
));
1284 emit_mul(Y_f
, Y_f
, brw_imm_f(key
->y_scale
));
1285 /* Adjust coordinates so that integers represent pixel centers rather
1288 emit_add(X_f
, X_f
, brw_imm_f(-0.5));
1289 emit_add(Y_f
, Y_f
, brw_imm_f(-0.5));
1291 /* Clamp the X, Y texture coordinates to properly handle the sampling of
1292 * texels on texture edges.
1294 clamp_tex_coords(X_f
, Y_f
,
1295 brw_imm_f(0.0), brw_imm_f(0.0),
1296 rect_grid_x1
, rect_grid_y1
);
1298 /* Store the fractional parts to be used as bilinear interpolation
1301 emit_frc(x_frac
, X_f
);
1302 emit_frc(y_frac
, Y_f
);
1304 /* Round the float coordinates down to nearest integer */
1305 emit_rndd(Xp_f
, X_f
);
1306 emit_rndd(Yp_f
, Y_f
);
1307 emit_mul(X_f
, Xp_f
, brw_imm_f(1 / key
->x_scale
));
1308 emit_mul(Y_f
, Yp_f
, brw_imm_f(1 / key
->y_scale
));
1310 } else if (!key
->bilinear_filter
) {
1311 /* Round the float coordinates down to nearest integer by moving to
1321 brw_blorp_blit_program::clamp_tex_coords(struct brw_reg regX
,
1322 struct brw_reg regY
,
1323 struct brw_reg clampX0
,
1324 struct brw_reg clampY0
,
1325 struct brw_reg clampX1
,
1326 struct brw_reg clampY1
)
1328 emit_cond_mov(regX
, clampX0
, BRW_CONDITIONAL_L
, regX
, clampX0
);
1329 emit_cond_mov(regX
, clampX1
, BRW_CONDITIONAL_G
, regX
, clampX1
);
1330 emit_cond_mov(regY
, clampY0
, BRW_CONDITIONAL_L
, regY
, clampY0
);
1331 emit_cond_mov(regY
, clampY1
, BRW_CONDITIONAL_G
, regY
, clampY1
);
1335 * Emit code to transform the X and Y coordinates as needed for blending
1336 * together the different samples in an MSAA texture.
1339 brw_blorp_blit_program::single_to_blend()
1341 /* When looking up samples in an MSAA texture using the SAMPLE message,
1342 * Gen6 requires the texture coordinates to be odd integers (so that they
1343 * correspond to the center of a 2x2 block representing the four samples
1344 * that maxe up a pixel). So we need to multiply our X and Y coordinates
1345 * each by 2 and then add 1.
1347 emit_shl(t1
, X
, brw_imm_w(1));
1348 emit_shl(t2
, Y
, brw_imm_w(1));
1349 emit_add(Xp
, t1
, brw_imm_w(1));
1350 emit_add(Yp
, t2
, brw_imm_w(1));
1356 * Count the number of trailing 1 bits in the given value. For example:
1358 * count_trailing_one_bits(0) == 0
1359 * count_trailing_one_bits(7) == 3
1360 * count_trailing_one_bits(11) == 2
1362 inline int count_trailing_one_bits(unsigned value
)
1364 #if defined(__GNUC__) && ((__GNUC__ * 100 + __GNUC_MINOR__) >= 304) /* gcc 3.4 or later */
1365 return __builtin_ctz(~value
);
1367 return _mesa_bitcount(value
& ~(value
+ 1));
1373 brw_blorp_blit_program::manual_blend_average(unsigned num_samples
)
1375 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1378 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
1380 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
1382 * This ensures that when all samples have the same value, no numerical
1383 * precision is lost, since each addition operation always adds two equal
1384 * values, and summing two equal floating point values does not lose
1387 * We perform this computation by treating the texture_data array as a
1388 * stack and performing the following operations:
1390 * - push sample 0 onto stack
1391 * - push sample 1 onto stack
1392 * - add top two stack entries
1393 * - push sample 2 onto stack
1394 * - push sample 3 onto stack
1395 * - add top two stack entries
1396 * - add top two stack entries
1397 * - divide top stack entry by 4
1399 * Note that after pushing sample i onto the stack, the number of add
1400 * operations we do is equal to the number of trailing 1 bits in i. This
1401 * works provided the total number of samples is a power of two, which it
1402 * always is for i965.
1404 * For integer formats, we replace the add operations with average
1405 * operations and skip the final division.
1407 unsigned stack_depth
= 0;
1408 for (unsigned i
= 0; i
< num_samples
; ++i
) {
1409 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
1411 /* Push sample i onto the stack */
1412 assert(stack_depth
< ARRAY_SIZE(texture_data
));
1417 emit_mov(vec16(S
), brw_imm_ud(i
));
1419 texel_fetch(texture_data
[stack_depth
++]);
1421 if (i
== 0 && key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
) {
1422 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
1423 * suggests an optimization:
1425 * "A simple optimization with probable large return in
1426 * performance is to compare the MCS value to zero (indicating
1427 * all samples are on sample slice 0), and sample only from
1428 * sample slice 0 using ld2dss if MCS is zero."
1430 * Note that in the case where the MCS value is zero, sampling from
1431 * sample slice 0 using ld2dss and sampling from sample 0 using
1432 * ld2dms are equivalent (since all samples are on sample slice 0).
1433 * Since we have already sampled from sample 0, all we need to do is
1434 * skip the remaining fetches and averaging if MCS is zero.
1436 emit_cmp_if(BRW_CONDITIONAL_NZ
, mcs_data
, brw_imm_ud(0));
1439 /* Do count_trailing_one_bits(i) times */
1440 for (int j
= count_trailing_one_bits(i
); j
-- > 0; ) {
1441 assert(stack_depth
>= 2);
1444 /* TODO: should use a smaller loop bound for non_RGBA formats */
1445 for (int k
= 0; k
< 4; ++k
) {
1446 emit_combine(key
->texture_data_type
== BRW_REGISTER_TYPE_F
?
1447 BRW_OPCODE_ADD
: BRW_OPCODE_AVG
,
1448 offset(texture_data
[stack_depth
- 1], 2*k
),
1449 offset(vec8(texture_data
[stack_depth
- 1]), 2*k
),
1450 offset(vec8(texture_data
[stack_depth
]), 2*k
));
1455 /* We should have just 1 sample on the stack now. */
1456 assert(stack_depth
== 1);
1458 if (key
->texture_data_type
== BRW_REGISTER_TYPE_F
) {
1459 /* Scale the result down by a factor of num_samples */
1460 /* TODO: should use a smaller loop bound for non-RGBA formats */
1461 for (int j
= 0; j
< 4; ++j
) {
1462 emit_mul(offset(texture_data
[0], 2*j
),
1463 offset(vec8(texture_data
[0]), 2*j
),
1464 brw_imm_f(1.0/num_samples
));
1468 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1473 brw_blorp_blit_program::manual_blend_bilinear(unsigned num_samples
)
1475 /* We do this computation by performing the following operations:
1477 * In case of 4x, 8x MSAA:
1478 * - Compute the pixel coordinates and sample numbers (a, b, c, d)
1479 * which are later used for interpolation
1480 * - linearly interpolate samples a and b in X
1481 * - linearly interpolate samples c and d in X
1482 * - linearly interpolate the results of last two operations in Y
1484 * result = lrp(lrp(a + b) + lrp(c + d))
1486 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1487 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1488 struct brw_reg t1_f
= retype(t1
, BRW_REGISTER_TYPE_F
);
1489 struct brw_reg t2_f
= retype(t2
, BRW_REGISTER_TYPE_F
);
1491 for (unsigned i
= 0; i
< 4; ++i
) {
1492 assert(i
< ARRAY_SIZE(texture_data
));
1495 /* Compute pixel coordinates */
1496 emit_add(vec16(x_sample_coords
), Xp_f
,
1497 brw_imm_f((float)(i
& 0x1) * (1.0 / key
->x_scale
)));
1498 emit_add(vec16(y_sample_coords
), Yp_f
,
1499 brw_imm_f((float)((i
>> 1) & 0x1) * (1.0 / key
->y_scale
)));
1500 emit_mov(vec16(X
), x_sample_coords
);
1501 emit_mov(vec16(Y
), y_sample_coords
);
1503 /* The MCS value we fetch has to match up with the pixel that we're
1504 * sampling from. Since we sample from different pixels in each
1505 * iteration of this "for" loop, the call to mcs_fetch() should be
1506 * here inside the loop after computing the pixel coordinates.
1508 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1511 /* Compute sample index and map the sample index to a sample number.
1512 * Sample index layout shows the numbering of slots in a rectangular
1513 * grid of samples with in a pixel. Sample number layout shows the
1514 * rectangular grid of samples roughly corresponding to the real sample
1515 * locations with in a pixel.
1516 * In case of 4x MSAA, layout of sample indices matches the layout of
1524 * In case of 8x MSAA the two layouts don't match.
1525 * sample index layout : --------- sample number layout : ---------
1526 * | 0 | 1 | | 5 | 2 |
1527 * --------- ---------
1528 * | 2 | 3 | | 4 | 6 |
1529 * --------- ---------
1530 * | 4 | 5 | | 0 | 3 |
1531 * --------- ---------
1532 * | 6 | 7 | | 7 | 1 |
1533 * --------- ---------
1535 emit_frc(vec16(t1_f
), x_sample_coords
);
1536 emit_frc(vec16(t2_f
), y_sample_coords
);
1537 emit_mul(vec16(t1_f
), t1_f
, brw_imm_f(key
->x_scale
));
1538 emit_mul(vec16(t2_f
), t2_f
, brw_imm_f(key
->x_scale
* key
->y_scale
));
1539 emit_add(vec16(t1_f
), t1_f
, t2_f
);
1540 emit_mov(vec16(S
), t1_f
);
1542 if (num_samples
== 8) {
1543 /* Map the sample index to a sample number */
1544 emit_cmp_if(BRW_CONDITIONAL_L
, S
, brw_imm_d(4));
1546 emit_mov(vec16(t2
), brw_imm_d(5));
1547 emit_if_eq_mov(S
, 1, vec16(t2
), 2);
1548 emit_if_eq_mov(S
, 2, vec16(t2
), 4);
1549 emit_if_eq_mov(S
, 3, vec16(t2
), 6);
1553 emit_mov(vec16(t2
), brw_imm_d(0));
1554 emit_if_eq_mov(S
, 5, vec16(t2
), 3);
1555 emit_if_eq_mov(S
, 6, vec16(t2
), 7);
1556 emit_if_eq_mov(S
, 7, vec16(t2
), 1);
1559 emit_mov(vec16(S
), t2
);
1561 texel_fetch(texture_data
[i
]);
1564 #define SAMPLE(x, y) offset(texture_data[x], y)
1565 for (int index
= 3; index
> 0; ) {
1566 /* Since we're doing SIMD16, 4 color channels fits in to 8 registers.
1567 * Counter value of 8 in 'for' loop below is used to interpolate all
1568 * the color components.
1570 for (int k
= 0; k
< 8; k
+= 2)
1571 emit_lrp(vec8(SAMPLE(index
- 1, k
)),
1573 vec8(SAMPLE(index
, k
)),
1574 vec8(SAMPLE(index
- 1, k
)));
1577 for (int k
= 0; k
< 8; k
+= 2)
1578 emit_lrp(vec8(SAMPLE(0, k
)),
1581 vec8(SAMPLE(0, k
)));
1586 * Emit code to look up a value in the texture using the SAMPLE message (which
1587 * does blending of MSAA surfaces).
1590 brw_blorp_blit_program::sample(struct brw_reg dst
)
1592 static const sampler_message_arg args
[2] = {
1593 SAMPLER_MESSAGE_ARG_U_FLOAT
,
1594 SAMPLER_MESSAGE_ARG_V_FLOAT
1597 texture_lookup(dst
, SHADER_OPCODE_TEX
, args
, ARRAY_SIZE(args
));
1601 * Emit code to look up a value in the texture using the SAMPLE_LD message
1602 * (which does a simple texel fetch).
1605 brw_blorp_blit_program::texel_fetch(struct brw_reg dst
)
1607 static const sampler_message_arg gen6_args
[5] = {
1608 SAMPLER_MESSAGE_ARG_U_INT
,
1609 SAMPLER_MESSAGE_ARG_V_INT
,
1610 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* R */
1611 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1612 SAMPLER_MESSAGE_ARG_SI_INT
1614 static const sampler_message_arg gen7_ld_args
[3] = {
1615 SAMPLER_MESSAGE_ARG_U_INT
,
1616 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1617 SAMPLER_MESSAGE_ARG_V_INT
1619 static const sampler_message_arg gen7_ld2dss_args
[3] = {
1620 SAMPLER_MESSAGE_ARG_SI_INT
,
1621 SAMPLER_MESSAGE_ARG_U_INT
,
1622 SAMPLER_MESSAGE_ARG_V_INT
1624 static const sampler_message_arg gen7_ld2dms_args
[4] = {
1625 SAMPLER_MESSAGE_ARG_SI_INT
,
1626 SAMPLER_MESSAGE_ARG_MCS_INT
,
1627 SAMPLER_MESSAGE_ARG_U_INT
,
1628 SAMPLER_MESSAGE_ARG_V_INT
1633 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen6_args
, s_is_zero
? 2 : 5);
1636 switch (key
->tex_layout
) {
1637 case INTEL_MSAA_LAYOUT_IMS
:
1638 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
1641 * If this field is MSFMT_DEPTH_STENCIL
1642 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
1643 * messages allowed are "ld2dms", "resinfo", and "sampleinfo".
1645 * So fall through to emit the same message as we use for
1646 * INTEL_MSAA_LAYOUT_CMS.
1648 case INTEL_MSAA_LAYOUT_CMS
:
1649 texture_lookup(dst
, SHADER_OPCODE_TXF_CMS
,
1650 gen7_ld2dms_args
, ARRAY_SIZE(gen7_ld2dms_args
));
1652 case INTEL_MSAA_LAYOUT_UMS
:
1653 texture_lookup(dst
, SHADER_OPCODE_TXF_UMS
,
1654 gen7_ld2dss_args
, ARRAY_SIZE(gen7_ld2dss_args
));
1656 case INTEL_MSAA_LAYOUT_NONE
:
1658 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen7_ld_args
,
1659 ARRAY_SIZE(gen7_ld_args
));
1664 assert(!"Should not get here.");
1670 brw_blorp_blit_program::mcs_fetch()
1672 static const sampler_message_arg gen7_ld_mcs_args
[2] = {
1673 SAMPLER_MESSAGE_ARG_U_INT
,
1674 SAMPLER_MESSAGE_ARG_V_INT
1676 texture_lookup(vec16(mcs_data
), SHADER_OPCODE_TXF_MCS
,
1677 gen7_ld_mcs_args
, ARRAY_SIZE(gen7_ld_mcs_args
));
1681 brw_blorp_blit_program::texture_lookup(struct brw_reg dst
,
1683 const sampler_message_arg
*args
,
1686 struct brw_reg mrf
=
1687 retype(vec16(brw_message_reg(base_mrf
)), BRW_REGISTER_TYPE_UD
);
1688 for (int arg
= 0; arg
< num_args
; ++arg
) {
1689 switch (args
[arg
]) {
1690 case SAMPLER_MESSAGE_ARG_U_FLOAT
:
1691 if (key
->bilinear_filter
)
1692 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
),
1693 retype(X
, BRW_REGISTER_TYPE_F
));
1695 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
), X
);
1697 case SAMPLER_MESSAGE_ARG_V_FLOAT
:
1698 if (key
->bilinear_filter
)
1699 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
),
1700 retype(Y
, BRW_REGISTER_TYPE_F
));
1702 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
), Y
);
1704 case SAMPLER_MESSAGE_ARG_U_INT
:
1707 case SAMPLER_MESSAGE_ARG_V_INT
:
1710 case SAMPLER_MESSAGE_ARG_SI_INT
:
1711 /* Note: on Gen7, this code may be reached with s_is_zero==true
1712 * because in Gen7's ld2dss message, the sample index is the first
1713 * argument. When this happens, we need to move a 0 into the
1714 * appropriate message register.
1717 emit_mov(mrf
, brw_imm_ud(0));
1721 case SAMPLER_MESSAGE_ARG_MCS_INT
:
1722 switch (key
->tex_layout
) {
1723 case INTEL_MSAA_LAYOUT_CMS
:
1724 emit_mov(mrf
, mcs_data
);
1726 case INTEL_MSAA_LAYOUT_IMS
:
1727 /* When sampling from an IMS surface, MCS data is not relevant,
1728 * and the hardware ignores it. So don't bother populating it.
1732 /* We shouldn't be trying to send MCS data with any other
1735 assert (!"Unsupported layout for MCS data");
1739 case SAMPLER_MESSAGE_ARG_ZERO_INT
:
1740 emit_mov(mrf
, brw_imm_ud(0));
1746 emit_texture_lookup(retype(dst
, BRW_REGISTER_TYPE_UW
) /* dest */,
1749 mrf
.nr
- base_mrf
/* msg_length */);
1757 #undef SWAP_XY_AND_XPYP
1760 brw_blorp_blit_program::render_target_write()
1762 struct brw_reg mrf_rt_write
=
1763 retype(vec16(brw_message_reg(base_mrf
)), key
->texture_data_type
);
1766 /* If we may have killed pixels, then we need to send R0 and R1 in a header
1767 * so that the render target knows which pixels we killed.
1769 bool use_header
= key
->use_kill
;
1771 /* Copy R0/1 to MRF */
1772 emit_mov(retype(mrf_rt_write
, BRW_REGISTER_TYPE_UD
),
1773 retype(R0
, BRW_REGISTER_TYPE_UD
));
1777 /* Copy texture data to MRFs */
1778 for (int i
= 0; i
< 4; ++i
) {
1779 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
1780 emit_mov(offset(mrf_rt_write
, mrf_offset
),
1781 offset(vec8(texture_data
[0]), 2*i
));
1785 /* Now write to the render target and terminate the thread */
1786 emit_render_target_write(
1789 mrf_offset
/* msg_length. TODO: Should be smaller for non-RGBA formats. */,
1795 brw_blorp_coord_transform_params::setup(GLfloat src0
, GLfloat src1
,
1796 GLfloat dst0
, GLfloat dst1
,
1799 float scale
= (src1
- src0
) / (dst1
- dst0
);
1801 /* When not mirroring a coordinate (say, X), we need:
1802 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1804 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1806 * blorp program uses "round toward zero" to convert the
1807 * transformed floating point coordinates to integer coordinates,
1808 * whereas the behaviour we actually want is "round to nearest",
1809 * so 0.5 provides the necessary correction.
1812 offset
= src0
+ (-dst0
+ 0.5) * scale
;
1814 /* When mirroring X we need:
1815 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1817 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1819 multiplier
= -scale
;
1820 offset
= src0
+ (dst1
- 0.5) * scale
;
1826 * Determine which MSAA layout the GPU pipeline should be configured for,
1827 * based on the chip generation, the number of samples, and the true layout of
1828 * the image in memory.
1830 inline intel_msaa_layout
1831 compute_msaa_layout_for_pipeline(struct brw_context
*brw
, unsigned num_samples
,
1832 intel_msaa_layout true_layout
)
1834 if (num_samples
<= 1) {
1835 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
1836 * format buffers, by transforming coordinates appropriately.
1838 assert(true_layout
== INTEL_MSAA_LAYOUT_NONE
||
1839 true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1840 return INTEL_MSAA_LAYOUT_NONE
;
1842 assert(true_layout
!= INTEL_MSAA_LAYOUT_NONE
);
1845 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
1846 if (brw
->gen
== 6) {
1847 assert(true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1854 brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context
*brw
,
1855 struct intel_mipmap_tree
*src_mt
,
1856 unsigned src_level
, unsigned src_layer
,
1857 struct intel_mipmap_tree
*dst_mt
,
1858 unsigned dst_level
, unsigned dst_layer
,
1859 GLfloat src_x0
, GLfloat src_y0
,
1860 GLfloat src_x1
, GLfloat src_y1
,
1861 GLfloat dst_x0
, GLfloat dst_y0
,
1862 GLfloat dst_x1
, GLfloat dst_y1
,
1864 bool mirror_x
, bool mirror_y
)
1866 src
.set(brw
, src_mt
, src_level
, src_layer
, false);
1867 dst
.set(brw
, dst_mt
, dst_level
, dst_layer
, true);
1869 /* Even though we do multisample resolves at the time of the blit, OpenGL
1870 * specification defines them as if they happen at the time of rendering,
1871 * which means that the type of averaging we do during the resolve should
1872 * only depend on the source format; the destination format should be
1873 * ignored. But, specification doesn't seem to be strict about it.
1875 * It has been observed that mulitisample resolves produce slightly better
1876 * looking images when averaging is done using destination format. NVIDIA's
1877 * proprietary OpenGL driver also follow this approach. So, we choose to
1878 * follow it in our driver.
1880 * When multisampling, if the source and destination formats are equal
1881 * (aside from the color space), we choose to blit in sRGB space to get
1882 * this higher quality image.
1884 if (src
.num_samples
> 1 &&
1885 _mesa_get_format_color_encoding(dst_mt
->format
) == GL_SRGB
&&
1886 _mesa_get_srgb_format_linear(src_mt
->format
) ==
1887 _mesa_get_srgb_format_linear(dst_mt
->format
)) {
1888 dst
.brw_surfaceformat
= brw_format_for_mesa_format(dst_mt
->format
);
1889 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
1892 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
1893 * texture, the above code configures the source format for L32_FLOAT or
1894 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
1895 * the SAMPLE message appears to handle multisampled L32_FLOAT and
1896 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
1897 * around the problem by using a source format of R32_FLOAT. This
1898 * shouldn't affect rendering correctness, since the destination format is
1899 * R32_FLOAT, so only the contents of the red channel matters.
1901 if (brw
->gen
== 6 && src
.num_samples
> 1 && dst
.num_samples
<= 1 &&
1902 src_mt
->format
== dst_mt
->format
&&
1903 dst
.brw_surfaceformat
== BRW_SURFACEFORMAT_R32_FLOAT
) {
1904 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
1908 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
1910 /* texture_data_type indicates the register type that should be used to
1911 * manipulate texture data.
1913 switch (_mesa_get_format_datatype(src_mt
->format
)) {
1914 case GL_UNSIGNED_NORMALIZED
:
1915 case GL_SIGNED_NORMALIZED
:
1917 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1919 case GL_UNSIGNED_INT
:
1920 if (src_mt
->format
== MESA_FORMAT_S_UINT8
) {
1921 /* We process stencil as though it's an unsigned normalized color */
1922 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1924 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_UD
;
1928 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_D
;
1931 assert(!"Unrecognized blorp format");
1936 /* Gen7's rendering hardware only supports the IMS layout for depth and
1937 * stencil render targets. Blorp always maps its destination surface as
1938 * a color render target (even if it's actually a depth or stencil
1939 * buffer). So if the destination is IMS, we'll have to map it as a
1940 * single-sampled texture and interleave the samples ourselves.
1942 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
1943 dst
.num_samples
= 0;
1946 if (dst
.map_stencil_as_y_tiled
&& dst
.num_samples
> 1) {
1947 /* If the destination surface is a W-tiled multisampled stencil buffer
1948 * that we're mapping as Y tiled, then we need to arrange for the WM
1949 * program to run once per sample rather than once per pixel, because
1950 * the memory layout of related samples doesn't match between W and Y
1953 wm_prog_key
.persample_msaa_dispatch
= true;
1956 if (src
.num_samples
> 0 && dst
.num_samples
> 1) {
1957 /* We are blitting from a multisample buffer to a multisample buffer, so
1958 * we must preserve samples within a pixel. This means we have to
1959 * arrange for the WM program to run once per sample rather than once
1962 wm_prog_key
.persample_msaa_dispatch
= true;
1965 /* Scaled blitting or not. */
1966 wm_prog_key
.blit_scaled
=
1967 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
1968 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
1970 /* Scaling factors used for bilinear filtering in multisample scaled
1973 wm_prog_key
.x_scale
= 2.0;
1974 wm_prog_key
.y_scale
= src_mt
->num_samples
/ 2.0;
1976 if (filter
== GL_LINEAR
&& src
.num_samples
<= 1 && dst
.num_samples
<= 1)
1977 wm_prog_key
.bilinear_filter
= true;
1979 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
1980 if (base_format
!= GL_DEPTH_COMPONENT
&& /* TODO: what about depth/stencil? */
1981 base_format
!= GL_STENCIL_INDEX
&&
1982 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1) {
1983 /* We are downsampling a color buffer, so blend. */
1984 wm_prog_key
.blend
= true;
1987 /* src_samples and dst_samples are the true sample counts */
1988 wm_prog_key
.src_samples
= src_mt
->num_samples
;
1989 wm_prog_key
.dst_samples
= dst_mt
->num_samples
;
1991 /* tex_samples and rt_samples are the sample counts that are set up in
1994 wm_prog_key
.tex_samples
= src
.num_samples
;
1995 wm_prog_key
.rt_samples
= dst
.num_samples
;
1997 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1998 * use to access the source and destination surfaces.
2000 wm_prog_key
.tex_layout
=
2001 compute_msaa_layout_for_pipeline(brw
, src
.num_samples
, src
.msaa_layout
);
2002 wm_prog_key
.rt_layout
=
2003 compute_msaa_layout_for_pipeline(brw
, dst
.num_samples
, dst
.msaa_layout
);
2005 /* src_layout and dst_layout indicate the true MSAA layout used by src and
2008 wm_prog_key
.src_layout
= src_mt
->msaa_layout
;
2009 wm_prog_key
.dst_layout
= dst_mt
->msaa_layout
;
2011 wm_prog_key
.src_tiled_w
= src
.map_stencil_as_y_tiled
;
2012 wm_prog_key
.dst_tiled_w
= dst
.map_stencil_as_y_tiled
;
2013 x0
= wm_push_consts
.dst_x0
= dst_x0
;
2014 y0
= wm_push_consts
.dst_y0
= dst_y0
;
2015 x1
= wm_push_consts
.dst_x1
= dst_x1
;
2016 y1
= wm_push_consts
.dst_y1
= dst_y1
;
2017 wm_push_consts
.rect_grid_x1
= (minify(src_mt
->logical_width0
, src_level
) *
2018 wm_prog_key
.x_scale
- 1.0);
2019 wm_push_consts
.rect_grid_y1
= (minify(src_mt
->logical_height0
, src_level
) *
2020 wm_prog_key
.y_scale
- 1.0);
2022 wm_push_consts
.x_transform
.setup(src_x0
, src_x1
, dst_x0
, dst_x1
, mirror_x
);
2023 wm_push_consts
.y_transform
.setup(src_y0
, src_y1
, dst_y0
, dst_y1
, mirror_y
);
2025 if (dst
.num_samples
<= 1 && dst_mt
->num_samples
> 1) {
2026 /* We must expand the rectangle we send through the rendering pipeline,
2027 * to account for the fact that we are mapping the destination region as
2028 * single-sampled when it is in fact multisampled. We must also align
2029 * it to a multiple of the multisampling pattern, because the
2030 * differences between multisampled and single-sampled surface formats
2031 * will mean that pixels are scrambled within the multisampling pattern.
2032 * TODO: what if this makes the coordinates too large?
2034 * Note: this only works if the destination surface uses the IMS layout.
2035 * If it's UMS, then we have no choice but to set up the rendering
2036 * pipeline as multisampled.
2038 assert(dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
);
2039 switch (dst_mt
->num_samples
) {
2041 x0
= ROUND_DOWN_TO(x0
* 2, 4);
2042 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2043 x1
= ALIGN(x1
* 2, 4);
2044 y1
= ALIGN(y1
* 2, 4);
2047 x0
= ROUND_DOWN_TO(x0
* 4, 8);
2048 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2049 x1
= ALIGN(x1
* 4, 8);
2050 y1
= ALIGN(y1
* 2, 4);
2053 assert(!"Unrecognized sample count in brw_blorp_blit_params ctor");
2056 wm_prog_key
.use_kill
= true;
2059 if (dst
.map_stencil_as_y_tiled
) {
2060 /* We must modify the rectangle we send through the rendering pipeline
2061 * (and the size and x/y offset of the destination surface), to account
2062 * for the fact that we are mapping it as Y-tiled when it is in fact
2065 * Both Y tiling and W tiling can be understood as organizations of
2066 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
2067 * is different, but the layout of the 32-byte sub-tiles within the 4k
2068 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
2069 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
2070 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
2072 * Therefore, to account for the layout differences within the 32-byte
2073 * sub-tiles, we must expand the rectangle so the X coordinates of its
2074 * edges are multiples of 8 (the W sub-tile width), and its Y
2075 * coordinates of its edges are multiples of 4 (the W sub-tile height).
2076 * Then we need to scale the X and Y coordinates of the rectangle to
2077 * account for the differences in aspect ratio between the Y and W
2078 * sub-tiles. We need to modify the layer width and height similarly.
2080 * A correction needs to be applied when MSAA is in use: since
2081 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
2082 * we need to align the Y coordinates to multiples of 8, so that when
2083 * they are divided by two they are still multiples of 4.
2085 * Note: Since the x/y offset of the surface will be applied using the
2086 * SURFACE_STATE command packet, it will be invisible to the swizzling
2087 * code in the shader; therefore it needs to be in a multiple of the
2088 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
2089 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
2090 * buffer), and the miplevel alignment used for stencil buffers is 8
2091 * pixels horizontally and either 4 or 8 pixels vertically (see
2092 * intel_horizontal_texture_alignment_unit() and
2093 * intel_vertical_texture_alignment_unit()).
2095 * Note: Also, since the SURFACE_STATE command packet can only apply
2096 * offsets that are multiples of 4 pixels horizontally and 2 pixels
2097 * vertically, it is important that the offsets will be multiples of
2098 * these sizes after they are converted into Y-tiled coordinates.
2099 * Fortunately they will be, since we know from above that the offsets
2100 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
2101 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
2103 * TODO: what if this makes the coordinates (or the texture size) too
2106 const unsigned x_align
= 8, y_align
= dst
.num_samples
!= 0 ? 8 : 4;
2107 x0
= ROUND_DOWN_TO(x0
, x_align
) * 2;
2108 y0
= ROUND_DOWN_TO(y0
, y_align
) / 2;
2109 x1
= ALIGN(x1
, x_align
) * 2;
2110 y1
= ALIGN(y1
, y_align
) / 2;
2111 dst
.width
= ALIGN(dst
.width
, x_align
) * 2;
2112 dst
.height
= ALIGN(dst
.height
, y_align
) / 2;
2115 wm_prog_key
.use_kill
= true;
2118 if (src
.map_stencil_as_y_tiled
) {
2119 /* We must modify the size and x/y offset of the source surface to
2120 * account for the fact that we are mapping it as Y-tiled when it is in
2123 * See the comments above concerning x/y offset alignment for the
2124 * destination surface.
2126 * TODO: what if this makes the texture size too large?
2128 const unsigned x_align
= 8, y_align
= src
.num_samples
!= 0 ? 8 : 4;
2129 src
.width
= ALIGN(src
.width
, x_align
) * 2;
2130 src
.height
= ALIGN(src
.height
, y_align
) / 2;
2137 brw_blorp_blit_params::get_wm_prog(struct brw_context
*brw
,
2138 brw_blorp_prog_data
**prog_data
) const
2140 uint32_t prog_offset
= 0;
2141 if (!brw_search_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2142 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2143 &prog_offset
, prog_data
)) {
2144 brw_blorp_blit_program
prog(brw
, &this->wm_prog_key
,
2145 INTEL_DEBUG
& DEBUG_BLORP
);
2146 GLuint program_size
;
2147 const GLuint
*program
= prog
.compile(brw
, &program_size
);
2148 brw_upload_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2149 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2150 program
, program_size
,
2151 &prog
.prog_data
, sizeof(prog
.prog_data
),
2152 &prog_offset
, prog_data
);